CN113539972A - Memory and manufacturing method thereof - Google Patents
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- CN113539972A CN113539972A CN202110790979.7A CN202110790979A CN113539972A CN 113539972 A CN113539972 A CN 113539972A CN 202110790979 A CN202110790979 A CN 202110790979A CN 113539972 A CN113539972 A CN 113539972A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 185
- 230000002093 peripheral effect Effects 0.000 claims abstract description 154
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 66
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 53
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000003860 storage Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 354
- 238000010586 diagram Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Abstract
The application provides a memory and a manufacturing method thereof, relates to the technical field of storage, and is used for solving the technical problem of large substrate loss in the memory. The manufacturing method of the memory comprises the following steps: providing a substrate, wherein the substrate comprises a core area and a peripheral area; the core area comprises a plurality of active areas and a shallow trench isolation area for isolating the active areas; forming a plurality of word line trenches in each of the active region and the peripheral region; forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer in the peripheral area to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core area to the upper surface of the substrate; forming a polycrystalline silicon layer on the conductive layer; removing part of the polycrystalline silicon layer in the core region and all the polycrystalline silicon layers in the peripheral region; a barrier layer is formed in the word line trenches of the core region and in the word line trenches of the peripheral region. By reducing the depth of the contact hole exposing the conductive layer in the peripheral area, the substrate loss caused by the formation of the contact hole is avoided, thereby improving the performance of devices such as transistors in a memory.
Description
Technical Field
The present application relates to the field of memory devices, and in particular, to a memory and a method for manufacturing the same.
Background
With the gradual development of Memory device technology, Dynamic Random Access Memory (DRAM) is gradually applied to various electronic devices with higher density and faster read/write speed. The dynamic random access memory is generally provided with a substrate and a dielectric layer arranged on the substrate, wherein a core region and a peripheral region arranged around the core region are arranged on the substrate, and both the core region and the peripheral region are provided with embedded word lines.
In the related art, the word line structure generally includes a conductive layer, a polysilicon layer, and a barrier layer sequentially stacked from bottom to top, typically, a contact hole exposing the conductive layer in the word line is formed on a dielectric layer corresponding to the word line in the peripheral region, a plurality of contact holes exposing the substrate are also formed on the dielectric layer corresponding to the substrate in the peripheral region, and the contact hole exposing the conductive layer of the word line in the peripheral region is communicated with the top of a portion of the contact hole corresponding to the substrate, so that the word line is electrically communicated with other devices through the contact structure.
However, as the density of circuit patterns increases, the word line structure in the memory makes the depth of each contact hole larger, resulting in large loss of the substrate when each contact hole is formed, thereby affecting the performance of devices such as transistors in the memory.
Disclosure of Invention
In view of the above problems, embodiments of the present application provide a memory and a method for manufacturing the same, which are used to reduce the loss of a substrate, thereby improving the performance of a transistor and other devices in the memory.
In order to achieve the above object, the embodiments of the present application provide the following technical solutions:
in a first aspect, an embodiment of the present application provides a method for manufacturing a memory, which includes:
providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the active regions; forming a plurality of word line trenches in each of the active regions and the peripheral region; forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer in the peripheral area to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core area to the upper surface of the substrate; forming a polysilicon layer on the substrate and the conductive layer; removing part of the polycrystalline silicon layer in the core region and all of the polycrystalline silicon layer in the peripheral region, and reserving part of the polycrystalline silicon layer which is positioned in the core region and positioned in the word line groove; forming a barrier layer in the word line trench of the core region and the word line trench of the peripheral region, the conductive layer, the polysilicon layer and the barrier layer in the core region forming a first word line, and the conductive layer and the barrier layer in the peripheral region forming a second word line.
In the above method for manufacturing a memory, forming a conductive layer in each of the word line trenches, and a distance from an upper surface of the conductive layer in the peripheral region to an upper surface of the substrate is smaller than a distance from an upper surface of the conductive layer in the core region to an upper surface of the substrate, the step includes: forming the conductive layer with a preset thickness in each word line groove of the core area and the word line grooves of the peripheral area; forming a first mask layer in the peripheral area, wherein the first mask layer covers the conducting layer in the peripheral area and the substrate in the peripheral area; removing a part of the conductive layer in the core area and in the word line groove by taking the first mask layer as a mask, and reserving a part of the conductive layer in the core area and in the word line groove; and removing the first mask layer.
In the above method for manufacturing a memory, the step of forming a conductive layer with a predetermined thickness in each trench includes: forming a conductive layer in the substrate and each of the word line trenches; and removing the substrate and a part of the conductive layer in each word line groove to form the conductive layer with the preset thickness in each word line groove.
In the method for manufacturing a memory device, the step of forming a plurality of word line trenches in each of the active region and the peripheral region includes: forming a second mask layer on the substrate; patterning the second mask layer to enable the patterned second mask layer to expose areas corresponding to the first word lines of the active area and the second word lines of the peripheral area; and removing part of the substrate by taking the patterned second mask layer as a mask so as to form the word line groove positioned in the active region and the word line groove positioned in the peripheral region.
According to the manufacturing method of the memory, the upper surface of the conductive layer in the second word line is formed to be higher than the upper surface of the part of the polycrystalline silicon layer which is finally remained in the first word line.
In the above method for manufacturing a memory, removing the core region and the portion of the conductive layer located in the word line trench, and leaving the portion of the conductive layer located in the core region and the word line trench specifically includes: and etching the core region and part of the conductive layer in the word line groove by adopting a wet method.
In the above method for manufacturing a memory, the step of forming a first mask layer in the peripheral region, where the first mask layer covers the conductive layer in the peripheral region and the substrate in the peripheral region includes: and forming a photoresist layer on the conducting layer of the peripheral area and the substrate of the peripheral area, wherein the photoresist layer covers the conducting layer of the peripheral area and the substrate of the peripheral area, and the photoresist layer forms the first mask layer.
In the above method for manufacturing a memory, the conductive layer is a titanium nitride layer; the barrier layer is a silicon nitride layer.
In the above method for fabricating a memory, after the steps of forming a first word line by the conductive layer, the polysilicon layer and the barrier layer in the core region and forming a second word line by the conductive layer and the barrier layer in the peripheral region, the method further includes: a first insulating layer is formed on the substrate.
In the above method for manufacturing a memory, after forming the first insulating layer on the substrate, the method further includes: forming a third mask layer on the first insulating layer; patterning the third mask layer to form a mask pattern; removing the first insulating layer by taking the third mask layer as a mask to form a gate groove exposing the substrate, wherein the gate groove corresponds to a region for forming a transistor structure; forming a gate structure in the gate trench; a second insulating layer is formed over the substrate and the gate structure.
In the above method for manufacturing a memory, after the step of forming the second insulating layer on the substrate and the gate structure, the method further includes: and forming a first contact hole exposing a part of the conductive layer in the second word line in the peripheral area, and simultaneously forming a second contact hole exposing a part of the substrate in the peripheral area.
In the method for manufacturing the memory described above, in the peripheral region, a first contact hole exposing a portion of the conductive layer in the second word line is formed, and the step of simultaneously forming a second contact hole exposing a portion of the substrate in the peripheral region includes: forming a fourth mask layer on the second insulating layer; patterning the fourth mask layer to form a mask pattern; sequentially removing the second insulating layer, the first insulating layer and the barrier layer in the area corresponding to the second word line by taking the fourth mask layer as a mask so as to form the first contact hole exposing part of the conducting layer; and synchronously and sequentially removing part of the second insulating layer and the first insulating layer in the corresponding area of the substrate to form a second contact hole exposing part of the substrate.
In the above method for manufacturing a memory, the first insulating layer is an oxide layer; the second insulating layer is a silicon nitride layer.
In a second aspect, an embodiment of the present application further provides a memory, which includes: a substrate comprising a core region and a peripheral region located outside the core region; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the active regions; the first word line is positioned in the active region, is arranged in the substrate corresponding to the active region and comprises a conductive layer, a polycrystalline silicon layer and a barrier layer which are sequentially stacked; and the second word line is positioned in the peripheral area and is arranged in the substrate corresponding to the peripheral area, and the second word line comprises a conductive layer and a barrier layer which are arranged in a stacked mode.
Compared with the related art, the memory and the manufacturing method thereof provided by the embodiment of the application have the following advantages at least:
the manufacturing method of the memory provided by the embodiment of the application comprises the following steps: providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core area comprises a plurality of active areas and a shallow trench isolation area for isolating the active areas; forming a plurality of word line trenches in each of the active region and the peripheral region; forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer in the peripheral area to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core area to the upper surface of the substrate; forming a polycrystalline silicon layer on the substrate and the conducting layer; removing part of the polycrystalline silicon layer in the core region and all the polycrystalline silicon layers in the peripheral region, and reserving part of the polycrystalline silicon layer which is positioned in the core region and positioned in the word line groove; and forming a barrier layer in the word line groove of the core area and the word line groove of the peripheral area, forming a first word line by the conductive layer, the polycrystalline silicon layer and the barrier layer positioned in the core area, and forming a second word line by the conductive layer and the barrier layer positioned in the peripheral area. By removing all the polysilicon layers on the conducting layer in the peripheral area, the distance from the upper surface of the conducting layer in the second word line to the upper surface of the substrate is smaller than the distance from the upper surface of the conducting layer in the core area to the upper surface of the substrate, so that the depth of the contact hole for exposing the conducting layer in the second word line can be reduced, the depth of other contact holes integrally formed with the contact hole in the substrate in the peripheral area can be reduced, the loss of the substrate caused by forming each contact hole can be avoided, and the performances of devices such as transistors in a memory can be improved.
In addition to the technical problems solved by the embodiments of the present application, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions described above, other technical problems that can be solved by the memory and the manufacturing method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram illustrating a structure of a memory according to the related art;
FIG. 2 is a flow chart of a method for fabricating a memory according to an embodiment of the present disclosure;
fig. 3 is a flowchart of forming conductive layers in a first word line and a second word line respectively in a method for manufacturing a memory according to an embodiment of the present disclosure;
fig. 4 is a flowchart illustrating a method for forming a conductive layer with a predetermined thickness in a method for manufacturing a memory according to an embodiment of the present disclosure;
fig. 5 is a flowchart illustrating a method for forming word line trenches in a memory according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram illustrating a conductive layer formed in a memory according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram illustrating a conductive layer with a predetermined thickness formed in a memory according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of forming a first mask layer in a peripheral region and etching a part of a conductive layer in a core region in a memory according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram illustrating a polysilicon layer formed in a memory according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of a memory according to an embodiment of the present disclosure, in which all of the polysilicon layer in the peripheral region and a part of the polysilicon layer in the core region are removed;
fig. 11 is a schematic structural diagram illustrating formation of a barrier layer in a memory according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a memory according to an embodiment of the present application.
Reference numerals:
10-a substrate; 11 — a first word line;
12-a second word line; 13-a conductive layer;
14-a polysilicon layer; 15-a barrier layer;
16-a first mask layer; 17-a second mask layer;
18-a first insulating layer; 19-a gate structure;
191-a dielectric layer; 192-work function adjusting layer;
193-first gate semiconductor layer; 194 — a second gate semiconductor layer;
195-a first electrically conductive layer; 196-a second electrically conductive layer;
197-an insulating capping layer; 20-a second insulating layer;
21-a first contact hole; 22-a second contact hole;
23-shallow trench isolation regions; 24-active region.
Detailed Description
The current dynamic random access memory includes a plurality of repeated memory cells, each memory cell includes a capacitor and a transistor, a gate of the transistor is connected to a Word Line (WL), a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor. The voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage. The Word line is connected to a Word line driver (Word line driver) through a contact structure (lcon) located in a peripheral region of the memory cell, so that the Word line driver can input a voltage signal into the Word line. As shown in fig. 1, a memory device is generally provided with a substrate, a core region (as shown in a in fig. 1) and a peripheral region (as shown in B in fig. 1) disposed around the core region, the core region including active regions arranged in an array and shallow trench isolation regions isolating the active regions, wherein the substrate comprises a P-type substrate and an N-type doped layer on the surface of the P-type substrate, and multiple word line trenches are formed in each active region and peripheral region, word line trenches formed in the active region separate the N-type doped layer into a source region and a drain region, and word lines are formed in the word line trenches, wherein the word line includes a conductive layer, and a polysilicon layer and a barrier layer disposed on the conductive layer, the conductive layer can be prevented from being electrically connected with the source region and the drain region, so as to prevent the performance of the transistor from being affected by the leakage current.
Because the word line of the peripheral area needs to be connected with the word line driver through the contact structure, in order to reduce the resistance value, the barrier layer and the polycrystalline silicon layer of the word line in the peripheral area and the corresponding part of the contact structure need to be removed, a contact hole is formed to expose the conducting layer of the word line of the peripheral area, so that the contact structure is in contact connection with the conducting layer in the word line, because the conducting layer has a larger distance from the surface of the substrate, the depth of the contact hole is larger, the depth of other contact holes integrally formed by the peripheral area and the contact hole is also deeper, when each contact hole is formed, certain loss is also caused on the surface layer of the substrate, and the deeper the contact hole is larger the loss of the substrate is; in addition, if the word line in the peripheral region includes the polysilicon layer, the etching selectivity between the polysilicon layer and the substrate is poor, and when the polysilicon layer is etched, the loss of the substrate is severe, and the loss of the substrate is severe, the loss of the N-type doping layer on the surface layer of the substrate is severe, so that the source region and the drain region of the N-type doping layer on the substrate are difficult to form, and the performance of devices such as transistors in the memory is affected.
In order to reduce the loss of the substrate and improve the performance of devices such as transistors in the memory, embodiments of the present application provide a method for manufacturing a memory, in which a distance from an upper surface of a conductive layer in a second word line to an upper surface of the substrate is smaller than a distance from an upper surface of a conductive layer in a core region to an upper surface of the substrate by removing all polysilicon layers on the conductive layer in a peripheral region, so that a depth of a contact hole for exposing the conductive layer in the second word line can be reduced, thereby reducing a depth of another contact hole integrally formed with the contact hole in the substrate in the peripheral region, avoiding the loss of the substrate caused when each contact hole is formed, and further improving the performance of devices such as transistors in the memory.
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
Referring to fig. 2, an embodiment of the present application provides a method for manufacturing a memory, where the method includes the following steps:
step S101, providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned in the core area; the core region includes a plurality of active regions and a shallow trench isolation region isolating the plurality of active regions.
Referring to fig. 6 to 12, a substrate 10 provided in this embodiment of the application is shown, where the substrate 10 includes a core region and a peripheral region located outside the core region, the core region is located at a shown in fig. 6 to 12, the peripheral region is located at B shown in fig. 6 to 12, a capacitor is subsequently formed above the core region of the substrate 10, and a peripheral circuit, for example, a transistor is subsequently formed above the peripheral region of the substrate 10.
The core region includes a plurality of active regions 24 and a shallow trench isolation region 23 isolating the active regions 24, a shallow trench isolation structure may be disposed in the shallow trench isolation region 23, the active regions 24 may be arranged in an array, a core region is formed in a region where the active regions 24 are arranged, and a peripheral region is formed in a region where the active regions 24 are not formed in the periphery of the core region, so that the peripheral region surrounds the periphery of the core region.
The substrate 10 may be a crystalline semiconductor material, such as a Silicon (Si) substrate 10, and the substrate 10 may also be a germanium (Ge) substrate, a Silicon On Insulator (SOI), a Silicon germanium (SiGe) substrate, a Silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate, which is not limited in this embodiment.
Step S102: a plurality of word line trenches are formed in each of the active region and the peripheral region.
Referring to fig. 6, a plurality of word line trenches are formed in each of the active region 24 and the peripheral region.
Referring to fig. 5, the step of forming a plurality of word line trenches in each of the active region and the peripheral region includes the following:
step S1021: a second mask layer is formed on the substrate.
Step S1022: and patterning the second mask layer to expose the first word line in the active region and the second word line in the peripheral region.
Step S1023: and removing part of the substrate by taking the patterned second mask layer as a mask to form a word line groove positioned in the active region and a word line groove positioned in the peripheral region.
Referring to fig. 6, specifically, a semiconductor layer may be disposed in the substrate 10, for example, the substrate 10 includes a P-type substrate 10 and an N-type doped layer, specifically, an ion doping process is performed on a surface of the P-type substrate 10, and the N-type doped layer is formed on the surface of the P-type substrate 10 to a certain thickness. After forming an N-type doped layer with a certain thickness on the surface of the P-type substrate 10, forming a second mask layer 17 on the substrate 10, patterning the second mask layer 17 to expose regions corresponding to word lines of the active region 24 and word lines of the peripheral region on the patterned second mask layer 17, etching the second mask layer 17 and the substrate 10 according to the pattern of the second mask layer 17 with the second mask layer 17 as a mask to form word line trenches located in the active region 24 and word line trenches located in the peripheral region, wherein the N-type doped layer is divided into a source region and a drain region by the word line trenches formed in each active region 24.
The second mask layer 17 may be an oxide layer, which is not limited in this embodiment.
Step S103: and forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer in the peripheral area to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core area to the upper surface of the substrate.
Referring to fig. 8, a conductive layer 13 is formed in each word line trench, and a distance from an upper surface of the conductive layer 13 in the peripheral region to an upper surface of the substrate 10 is smaller than a distance from an upper surface of the conductive layer 13 in the core region to an upper surface of the substrate 10, so that a distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is relatively small, and thus, loss of the substrate due to exposure of the conductive layer in the peripheral region in a subsequent process can be reduced.
The conductive layer 13 may be a conductive layer 13 made of a conductive material such as titanium nitride, which is not limited in this embodiment.
Referring to fig. 3, the step of forming a conductive layer in each word line trench, where a distance from the upper surface of the conductive layer in the peripheral region to the upper surface of the substrate is smaller than a distance from the upper surface of the conductive layer in the core region to the upper surface of the substrate, specifically includes:
step S1031: and forming a conductive layer with a preset thickness in each word line groove in the core area and the word line grooves in the peripheral area.
Referring to fig. 7, a conductive layer 13 is formed in the substrate 10 and each word line trench; the substrate 10 and a portion of the conductive layer 13 in each word line trench are removed to form a conductive layer 13 of a predetermined thickness in each word line trench.
Referring to fig. 4, the step of forming a conductive layer with a predetermined thickness in each word line trench in the core region and the word line trenches in the peripheral region specifically includes:
step S10311: a conductive layer is formed in the substrate and each word line trench.
Referring to fig. 6, a conductive layer 13 is formed in the substrate 10 and each word line trench.
Step S10311: and removing the substrate and part of the conductive layer in each word line groove to form a conductive layer with a preset thickness in each word line groove.
Referring to fig. 7, the substrate 10 and a portion of the conductive layer 13 in each word line trench may be removed by etching or the like to form the conductive layer 13 with a preset thickness in each word line trench, where the etching manner may be dry etching or wet etching, for example, laser etching, chemical liquid etching, and the like, and the embodiment is not limited in this respect.
Step S1032: and forming a first mask layer in the peripheral area, wherein the first mask layer covers the conducting layer in the peripheral area and the substrate in the peripheral area.
Referring to fig. 8, a first mask layer 16 is formed in the peripheral region, and the first mask layer 16 covers the conductive layer 13 in the peripheral region and the second mask layer 17 in the peripheral region, wherein the first mask layer 16 is formed by forming a photoresist layer on the conductive layer 13 in the peripheral region and the second mask layer 17 in the peripheral region, and the photoresist layer covers the conductive layer 13 in the peripheral region and the second mask layer 17 in the peripheral region.
Step S1032: and removing part of the conductive layer in the core area and in the word line groove by taking the first mask layer as a mask, and reserving part of the conductive layer in the core area and in the word line groove.
Step S1032: and removing the first mask layer.
Continuing to refer to fig. 8, using the first mask layer 16 as a mask, removing a portion of the conductive layer 13 in the core region and in the word line trench, and leaving a portion of the conductive layer 13 in the core region and in the word line trench; and removing the first mask layer 16 to form the conductive layer 13 in each word line trench in the peripheral region and the conductive layer 13 in each word line trench in the core region, wherein the distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is less than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10.
In addition, a part of the conductive layer 13 in the core region and in the word line trench is removed, and a part of the conductive layer 13 in the core region and in the word line trench is remained, and the conductive layer 13 may be etched specifically by wet etching or other etching methods, for example, chemical liquid etching or other methods, such as phosphoric acid wet etching the conductive layer 13, and thus, this embodiment is not limited specifically.
Step S104: and forming a polycrystalline silicon layer on the substrate and the conductive layer.
Referring to fig. 9, a polysilicon layer 14 is formed on the substrate 10 and the conductive layer 13. Wherein, the polysilicon layer 14 can be formed on the conductive layer 13 by spin coating or chemical deposition.
Step S105: and removing part of the polycrystalline silicon layer in the core region and all the polycrystalline silicon layers in the peripheral region, and reserving part of the polycrystalline silicon layer which is positioned in the core region and positioned in the word line groove.
Referring to fig. 10, a portion of the polysilicon layer 14 in the core region and all of the polysilicon layer 14 in the peripheral region are removed, and a portion of the polysilicon layer 14 in the core region and in the word line trench remains.
It should be noted that the polysilicon layer 14 and the blocking layer 15 in the core region mainly prevent the conductive layer 13 in the core region from being electrically connected with the source region and the drain region, which may cause leakage current, and in addition, the polysilicon layer is disposed on the conductive layer 13 in the first word line 11, which may also prevent leakage current and reduce the resistance value of the word line.
Illustratively, a wet etching method such as chemical liquid etching is used to remove a portion of the polysilicon layer 14 in the core region and all of the polysilicon layer 14 in the peripheral region, and a portion of the polysilicon layer 14 in the core region and in the word line trench is remained.
Wet etching can provide a different etch selectivity than dry etching, thereby reducing the loss of substrate 10 when etching polysilicon layer 14.
It is understood that the etching selectivity refers to the relative etching rate of one material to another material under the same etching condition, i.e. the ratio of the etching rate of the etched material to the etching rate of another material.
Step S106: and forming a barrier layer in the word line groove of the core area and the word line groove of the peripheral area, forming a first word line by the conductive layer, the polycrystalline silicon layer and the barrier layer positioned in the core area, and forming a second word line by the conductive layer and the barrier layer positioned in the peripheral area.
Referring to fig. 11, a barrier layer 15 is formed in the word line trench of the core region and the word line trench of the peripheral region, the conductive layer 13, the polysilicon layer 14, and the barrier layer 15 in the core region form a first word line 11, and the conductive layer 13 and the barrier layer 15 in the peripheral region form a second word line 12. By setting the structures of the first word line 11 and the second word line 12 to be different, it is possible to reduce the loss of the substrate 10 and improve the performance of a device such as a transistor in a memory, in addition to avoiding the occurrence of a leakage current between the conductive layer 13 and the source and drain regions in the first word line 11.
The barrier layer 15 may be made of an insulating material such as silicon nitride or silicon oxynitride.
The embodiment of the present application provides a method for manufacturing a memory, by removing all the polysilicon layer 14 on the conductive layer 13 in the peripheral region, a distance from the upper surface of the conductive layer 13 in the second word line 12 to the upper surface of the substrate 10 is smaller than a distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10, so that a depth of a contact hole for exposing the conductive layer 13 in the second word line 12 can be reduced, thereby reducing depths of other contact holes integrally formed with the contact hole in the substrate 10 in the peripheral region, and avoiding loss of the substrate 10 caused by forming each contact hole; in addition, the second word line 12 formed in the peripheral region does not have the polysilicon layer 14, so that the loss of the substrate 10 can be reduced, the source region and the drain region cannot be formed in the N-type doped layer of the substrate 10 due to the loss of the surface layer of the substrate 10, and the performance of devices such as transistors in a memory can be improved.
Further, in order to avoid forming polysilicon residue on the conductive layer 13 in the peripheral region, in the present embodiment, the upper surface of the conductive layer 13 formed in the second word line 12 is higher than the upper surface of the portion of the polysilicon layer 14 that finally remains in the formed first word line 11.
The conductive layer 13, the polysilicon layer 14 and the barrier layer 15 in the core region form a first word line 11, and the conductive layer 13 and the barrier layer 15 in the peripheral region form a second word line 12, which further includes: a first insulating layer 18 is formed on the substrate 10. The first insulating layer 18 may be an oxide layer, such as silicon dioxide.
Referring to fig. 12, after forming the first insulating layer 18 on the substrate 10, the memory manufacturing method further includes: forming a third mask layer on the first insulating layer 18; patterning the third mask layer to form a mask pattern; removing part of the first insulating layer 18 by taking the third mask layer as a mask to form a gate trench exposing the substrate 10, wherein the gate trench corresponds to a region where the transistor structure is formed; forming a gate structure 19 in the gate trench; the gate structure 19 in the peripheral region may include a dielectric layer 191, a metal-containing work function adjusting layer 192, a first gate semiconductor layer 193, a second gate semiconductor layer 194, a first conductive layer 195, a second conductive layer 196 and an insulating capping layer 197, which are sequentially stacked, wherein the dielectric layer 191 is formed at the bottom of the gate trench, and then the second insulating layer 20 is formed on the substrate 10 and the gate structure 19.
The second insulating layer 20 may be a silicon nitride layer or the like.
Further, after forming the second insulating layer 20 on the substrate 10 and the gate structure 19, a first contact hole 21 exposing a portion of the conductive layer 13 in the second word line 12 is formed in the peripheral region, and a second contact hole 22 exposing a portion of the substrate 10 is simultaneously formed in the peripheral region.
Because the upper surface of the conductive layer 13 in the second word line 12 is closer to the upper surface of the substrate 10, the depth of the formed first contact hole 21 is shallower, and thus, the time of the first contact hole 21 formed by etching and the like can be reduced, thereby reducing the etching of the surface layer of the substrate 10 and reducing the loss of the substrate 10, in addition, the distance from the conductive layer 13 in the second word line 12 to the upper surface of the substrate 10 is smaller, the thickness of the barrier layer 15 on the conductive layer 13 in the second word line 12 is smaller than that of the conductive layer 13, thereby reducing the resistance when the contact structure is in contact connection with the second word line 12, and further improving the reliability and stability of the electrical connection between the contact structure and the second word line 12.
Since the first contact hole 21 exposing a portion of the conductive layer 13 in the second word line 12 and the second contact hole 22 forming the exposed portion of the substrate 10 in the peripheral region are formed simultaneously, the depth of the first contact hole 21 is reduced, and the depth of the second contact hole 22 is also reduced, thereby avoiding the problem of large loss of the substrate 10 due to the deep depth of the first contact hole 21 and the deep depth of the second contact hole 22.
It is understood that the first contact hole 21 and the second contact hole 22 are formed simultaneously, that is, the first contact hole 21 and the second contact hole 22 are integrally formed, so that the number of processing steps can be reduced, and the processing cost can be reduced.
Specifically, forming the first contact hole 21 exposing a portion of the conductive layer 13 in the second word line 12 in the peripheral region, and simultaneously forming the second contact hole 22 exposing a portion of the substrate 10 in the peripheral region specifically includes: forming a fourth mask layer on the second insulating layer 20; patterning the fourth mask layer to form a mask pattern; sequentially removing the second insulating layer 20, the first insulating layer 18 and the barrier layer 15 in the region corresponding to the second word line 12 by using the fourth mask layer as a mask to form a first contact hole 21 exposing a part of the conductive layer 13; the second insulating layer 20 and the first insulating layer 18 are sequentially removed in a synchronous manner from the corresponding region of the portion of the substrate 10 to form a second contact hole 22 exposing the portion of the substrate 10.
A contact structure may be formed in the first contact hole 21 so that the second word line 12 is electrically connected to the gate structure 19 through the contact structure; the second contact hole 22 may also have a contact structure formed therein, so that the semiconductor layer in the substrate 10 is electrically connected to other devices through the contact structure, and the embodiment is not particularly limited.
The manufacturing method of the memory provided by the embodiment of the application comprises the following steps: providing a substrate 10, the substrate 10 comprising a core region and a peripheral region located outside the core region; the core region comprises a plurality of active regions 24 and shallow trench isolation regions 23 isolating the plurality of active regions 24; forming a plurality of word line trenches in each of the active region 24 and the peripheral region; forming a conductive layer 13 in each word line trench, wherein the distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is less than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10; forming a polysilicon layer 14 on the substrate 10 and the conductive layer 13; removing part of the polycrystalline silicon layer 14 in the core region and all the polycrystalline silicon layer 14 in the peripheral region, and reserving part of the polycrystalline silicon layer 14 which is positioned in the core region and is positioned in the word line groove; a barrier layer 15 is formed in the word line trench of the core region and the word line trench of the peripheral region, the conductive layer 13, the polysilicon layer 14, and the barrier layer 15 in the core region form the first word line 11, and the conductive layer 13 and the barrier layer 15 in the peripheral region form the second word line 12. By removing all the polysilicon layer 14 on the peripheral region conductive layer 13, the distance from the upper surface of the conductive layer 13 in the second word line 12 to the upper surface of the substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10, so that the depth of the contact hole for exposing the conductive layer 13 in the second word line 12 can be reduced, the depth of other contact holes integrally formed with the contact hole in the peripheral region substrate 10 can be reduced, the loss of the substrate 10 due to etching of the first contact hole 21 and the second contact hole 22 can be reduced, and the performance of devices such as transistors in a memory can be improved.
Example two
Referring to fig. 12, on the basis of the first embodiment, an embodiment of the present application provides a memory.
The memory includes a substrate 10, the substrate 10 including a core region and a peripheral region located outside the core region; the core region comprises a plurality of active regions 24 and shallow trench isolation regions 23 isolating the plurality of active regions 24; the first word line 11, the first word line 11 is located in the active area 24, the first word line 11 is arranged in the substrate 10 corresponding to the active area 24, and the first word line 11 comprises a conductive layer 13, a polysilicon layer 14 and a barrier layer 15 which are sequentially stacked; and a second word line 12, wherein the second word line 12 is located in the peripheral region and is disposed in the substrate 10 corresponding to the peripheral region, and the second word line 12 includes a conductive layer 13 and a barrier layer 15 which are stacked.
The distance from the upper surface of the conductive layer 13 in the second word line 12 to the upper surface of the substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in the first word line 11 to the upper surface of the substrate 10, so that the depth of the first contact hole 21 exposing the conductive layer 13 in the first word line 11 can be reduced, the loss of the substrate 10 caused by etching the first contact hole 21 is reduced, and the performance of devices such as transistors in a memory is improved.
The memory provided by the embodiment of the application comprises a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core area comprises a plurality of active areas and a shallow trench isolation area for isolating the active areas; the first word line is positioned in the active region and arranged in the substrate corresponding to the active region, and the first word line comprises a conductive layer, a polycrystalline silicon layer and a barrier layer which are sequentially stacked; the second word line is located in the peripheral area and arranged in the substrate corresponding to the peripheral area, and the second word line comprises a conducting layer and a blocking layer which are arranged in a stacked mode. By making the distance from the upper surface of the conducting layer in the second word line to the upper surface of the substrate smaller than the distance from the upper surface of the conducting layer in the first word line to the upper surface of the substrate, the depth of the first contact hole exposing the conducting layer in the first word line can be reduced, thereby reducing the loss of the substrate caused by etching the first contact hole and improving the performance of devices such as transistors in a memory.
In the description above, it should be understood that unless otherwise specifically stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning a fixed connection, an indirect connection through intervening media, a connection between two elements, or an interactive relationship between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically stated otherwise.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the essence of the corresponding technical solution.
Claims (14)
1. A method for manufacturing a memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the active regions;
forming a plurality of word line trenches in each of the active regions and the peripheral region;
forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer in the peripheral area to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core area to the upper surface of the substrate;
forming a polysilicon layer on the substrate and the conductive layer;
removing part of the polycrystalline silicon layer in the core region and all of the polycrystalline silicon layer in the peripheral region, and reserving part of the polycrystalline silicon layer which is positioned in the core region and positioned in the word line groove;
forming a barrier layer in the word line trench of the core region and the word line trench of the peripheral region, the conductive layer, the polysilicon layer and the barrier layer in the core region forming a first word line, and the conductive layer and the barrier layer in the peripheral region forming a second word line.
2. The method of claim 1, wherein forming a conductive layer in each of the word line trenches, wherein a distance from a top surface of the conductive layer in the peripheral region to a top surface of the substrate is less than a distance from a top surface of the conductive layer in the core region to a top surface of the substrate, comprises:
forming the conductive layer with a preset thickness in each word line groove of the core area and the word line grooves of the peripheral area;
forming a first mask layer in the peripheral area, wherein the first mask layer covers the conducting layer in the peripheral area and the substrate in the peripheral area;
removing a part of the conductive layer in the core area and in the word line groove by taking the first mask layer as a mask, and reserving a part of the conductive layer in the core area and in the word line groove;
and removing the first mask layer.
3. The method of claim 2, wherein the step of forming a conductive layer of a predetermined thickness in each of the word line trenches comprises:
forming a conductive layer in the substrate and each of the word line trenches;
and removing the substrate and a part of the conductive layer in each word line groove to form the conductive layer with the preset thickness in each word line groove.
4. The method of claim 1, wherein forming a plurality of word line trenches in each of the active region and the peripheral region comprises:
forming a second mask layer on the substrate;
patterning the second mask layer to enable the patterned second mask layer to expose areas corresponding to the first word lines of the active area and the second word lines of the peripheral area;
and removing part of the substrate by taking the patterned second mask layer as a mask so as to form the word line groove in the active region and the word line groove in the peripheral region.
5. The method for manufacturing the memory according to any one of claims 1 to 4, wherein an upper surface of the conductive layer in the second word line is formed to be higher than an upper surface of a portion of the polysilicon layer which is finally remained in the first word line.
6. The method of claim 2, wherein removing the portion of the conductive layer in the core region and in the word line trench and leaving the portion of the conductive layer in the core region and in the word line trench comprises:
and etching the core region and part of the conductive layer in the word line groove by adopting a wet method.
7. The method of claim 2, wherein forming a first mask layer in the peripheral region, the first mask layer covering the conductive layer in the peripheral region and the substrate in the peripheral region comprises:
and forming a photoresist layer on the conducting layer of the peripheral area and the substrate of the peripheral area, wherein the photoresist layer covers the conducting layer of the peripheral area and the substrate of the peripheral area, and the photoresist layer forms the first mask layer.
8. The method for manufacturing the memory according to any one of claims 1 to 4, wherein the conductive layer is a titanium nitride layer; the barrier layer is a silicon nitride layer.
9. The method of any of claims 1-4, wherein the conductive layer, the polysilicon layer, and the barrier layer in the core region form a first word line, and the conductive layer and the barrier layer in the peripheral region form a second word line, the method further comprising:
a first insulating layer is formed on the substrate.
10. The method of claim 9, wherein after forming the first insulating layer on the substrate, the method further comprises:
forming a third mask layer on the first insulating layer;
patterning the third mask layer to form a mask pattern;
removing the first insulating layer by taking the third mask layer as a mask to form a gate groove exposing the substrate, wherein the gate groove corresponds to a region for forming a transistor structure;
forming a gate structure in the gate trench;
a second insulating layer is formed over the substrate and the gate structure.
11. The method of claim 10, wherein after the step of forming a second insulating layer over the substrate and the gate structure, the method further comprises:
and forming a first contact hole exposing a part of the conductive layer in the second word line in the peripheral area, and simultaneously forming a second contact hole exposing a part of the substrate in the peripheral area.
12. The method of claim 11, wherein forming a first contact hole in the peripheral region exposing a portion of the conductive layer in the second word line, and forming a second contact hole in the peripheral region exposing a portion of the substrate simultaneously comprises:
forming a fourth mask layer on the second insulating layer;
patterning the fourth mask layer to form a mask pattern;
sequentially removing the second insulating layer, the first insulating layer and the barrier layer in the area corresponding to the second word line by taking the fourth mask layer as a mask so as to form the first contact hole exposing part of the conducting layer; and synchronously and sequentially removing the second insulating layer and the first insulating layer in the area corresponding to part of the substrate to form a second contact hole exposing part of the substrate.
13. The method of claim 12, wherein the first insulating layer is an oxide layer; the second insulating layer is a silicon nitride layer.
14. A memory, comprising:
a substrate comprising a core region and a peripheral region located outside the core region; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the active regions;
the first word line is positioned in the active region, is arranged in the substrate corresponding to the active region and comprises a conductive layer, a polycrystalline silicon layer and a barrier layer which are sequentially stacked;
and the second word line is positioned in the peripheral area and is arranged in the substrate corresponding to the peripheral area, and the second word line comprises a conductive layer and a barrier layer which are arranged in a stacked mode.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114068405A (en) * | 2022-01-07 | 2022-02-18 | 长鑫存储技术有限公司 | Semiconductor device forming method and semiconductor device |
| CN116489993A (en) * | 2023-06-21 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| WO2024021180A1 (en) * | 2022-07-28 | 2024-02-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| WO2024031818A1 (en) * | 2022-08-09 | 2024-02-15 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and memory |
| WO2024060541A1 (en) * | 2022-09-21 | 2024-03-28 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor, and memory |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055898A (en) * | 1991-04-30 | 1991-10-08 | International Business Machines Corporation | DRAM memory cell having a horizontal SOI transfer device disposed over a buried storage node and fabrication methods therefor |
| JP2002270797A (en) * | 2001-03-08 | 2002-09-20 | Sony Corp | Semiconductor device and method of manufacturing the same |
| CN1401139A (en) * | 2000-12-14 | 2003-03-05 | 索尼公司 | Semiconductor device and its manufacturing method |
| JP2004095745A (en) * | 2002-08-30 | 2004-03-25 | Sony Corp | Semiconductor device and method for manufacturing the same |
| US7034408B1 (en) * | 2004-12-07 | 2006-04-25 | Infineon Technologies, Ag | Memory device and method of manufacturing a memory device |
| CN1941301A (en) * | 2005-09-09 | 2007-04-04 | 奇梦达股份公司 | Method of manufacturing a transistor and a method of forming a memory device |
| US20110217820A1 (en) * | 2010-03-02 | 2011-09-08 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices |
| US20180158871A1 (en) * | 2016-12-02 | 2018-06-07 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of manufacturing the same |
| CN110211959A (en) * | 2018-02-28 | 2019-09-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110610940A (en) * | 2018-06-15 | 2019-12-24 | 长鑫存储技术有限公司 | Memory transistor, word line structure of memory transistor and word line preparation method |
| CN110896047A (en) * | 2018-09-12 | 2020-03-20 | 长鑫存储技术有限公司 | Shallow trench isolation structure and preparation method of semiconductor device |
-
2021
- 2021-07-13 CN CN202110790979.7A patent/CN113539972B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055898A (en) * | 1991-04-30 | 1991-10-08 | International Business Machines Corporation | DRAM memory cell having a horizontal SOI transfer device disposed over a buried storage node and fabrication methods therefor |
| CN1401139A (en) * | 2000-12-14 | 2003-03-05 | 索尼公司 | Semiconductor device and its manufacturing method |
| JP2002270797A (en) * | 2001-03-08 | 2002-09-20 | Sony Corp | Semiconductor device and method of manufacturing the same |
| JP2004095745A (en) * | 2002-08-30 | 2004-03-25 | Sony Corp | Semiconductor device and method for manufacturing the same |
| US7034408B1 (en) * | 2004-12-07 | 2006-04-25 | Infineon Technologies, Ag | Memory device and method of manufacturing a memory device |
| CN1941301A (en) * | 2005-09-09 | 2007-04-04 | 奇梦达股份公司 | Method of manufacturing a transistor and a method of forming a memory device |
| US20110217820A1 (en) * | 2010-03-02 | 2011-09-08 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices |
| US20180158871A1 (en) * | 2016-12-02 | 2018-06-07 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of manufacturing the same |
| CN110211959A (en) * | 2018-02-28 | 2019-09-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110610940A (en) * | 2018-06-15 | 2019-12-24 | 长鑫存储技术有限公司 | Memory transistor, word line structure of memory transistor and word line preparation method |
| CN110896047A (en) * | 2018-09-12 | 2020-03-20 | 长鑫存储技术有限公司 | Shallow trench isolation structure and preparation method of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114068405A (en) * | 2022-01-07 | 2022-02-18 | 长鑫存储技术有限公司 | Semiconductor device forming method and semiconductor device |
| WO2023130583A1 (en) * | 2022-01-07 | 2023-07-13 | 长鑫存储技术有限公司 | Method for forming semiconductor device, and semiconductor device |
| WO2024021180A1 (en) * | 2022-07-28 | 2024-02-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| WO2024031818A1 (en) * | 2022-08-09 | 2024-02-15 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and memory |
| WO2024060541A1 (en) * | 2022-09-21 | 2024-03-28 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor, and memory |
| CN116489993A (en) * | 2023-06-21 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116489993B (en) * | 2023-06-21 | 2023-11-14 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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