CN113539966A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN113539966A
CN113539966A CN202010292058.3A CN202010292058A CN113539966A CN 113539966 A CN113539966 A CN 113539966A CN 202010292058 A CN202010292058 A CN 202010292058A CN 113539966 A CN113539966 A CN 113539966A
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layer
channel
sacrificial
initial
forming
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张海洋
纪世良
苏博
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010292058.3A priority Critical patent/CN113539966A/en
Publication of CN113539966A publication Critical patent/CN113539966A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The application discloses a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: forming a substrate and an initial convex layer on the substrate; forming an initial isolation structure on the substrate to cover the side wall of the initial convex layer; after the initial isolation structure is formed, etching back part of the initial convex layer to form a groove in the initial isolation structure and enable the initial convex layer to form a convex layer positioned at the bottom of the groove; and forming a first sacrificial layer, a first channel layer, a second sacrificial layer and a second channel layer in the groove from bottom to top in sequence. The semiconductor structure and the forming method thereof improve the performance of the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor structure.
Background
The gate of a conventional Fin Field Effect Transistor (FinFET) surrounds the channel region on three sides only, with its bottom connected to the semiconductor substrate, which makes possible leakage currents when the FinFET is off. Therefore, a Complementary Field Effect Transistor (CFET) is proposed in the prior art, which employs a gate surrounding technology to stack the channel regions of a sheet-type n-type Field Effect Transistor and a sheet-type p-type Field Effect Transistor up and down and make the gate completely surround the channel region, thereby not only effectively solving the problem of leakage current, but also reducing the size of the Transistor by nearly one third.
However, the conventional CFET has technical problems such as narrowing of the sacrificial layer, non-uniform trench depth and/or insufficient remaining thickness of the hard mask layer during the manufacturing process. Therefore, there is a need for improvement in the CFET formation method to eliminate the problems of the current process.
Disclosure of Invention
The following presents a simplified summary of the application in order to provide a basic understanding of some aspects of the application. It should be understood that this section is not intended to identify key or critical elements of the application, nor is it intended to be limiting as to the scope of the application. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
The method aims to solve the technical problems of narrow sacrificial layer, uneven groove depth and/or insufficient residual thickness of the hard mask layer in the manufacturing process of the CFET.
In order to solve some or all of the above technical problems, an aspect of the present application provides a method for forming a semiconductor structure, the method including: forming a substrate and an initial convex layer on the substrate; forming an initial isolation structure on the substrate to cover the side wall of the initial convex layer; after the initial isolation structure is formed, etching back part of the initial convex layer to form a groove in the initial isolation structure and enable the initial convex layer to form a convex layer positioned at the bottom of the groove; and forming a first sacrificial layer, a first channel layer, a second sacrificial layer and a second channel layer in the groove from bottom to top in sequence.
Optionally, the step of forming the substrate and the initial convex layer comprises: providing an initial substrate, wherein a first mask layer is formed on part of the surface of the initial substrate; and etching a part of the initial substrate by taking the first mask layer as a mask to form the substrate and the initial convex layer positioned on the substrate, wherein the first mask layer is positioned on the top surface of the initial convex layer after the initial convex layer is formed.
Optionally, before forming the initial isolation structure, a top surface of the initial convex layer has a first mask layer; before etching back part of the initial convex layer, the top surface of the initial isolation structure is lower than that of the initial convex layer; the method for forming the semiconductor structure further comprises the following steps: before the initial convex layer is etched back, a second mask layer is formed on the surface of the initial isolation structure, and the second mask layer covers partial side walls of the initial convex layer and side walls of the first mask layer; before etching back the part of the initial convex layer, flattening the second mask layer and the first mask layer until the top surface of the initial convex layer is exposed; etching back part of the initial convex layer by taking the second mask layer as a mask; and removing the second mask layer after the first sacrificial layer, the first channel layer, the second sacrificial layer, and the second channel layer are formed.
Optionally, the method of forming the initial isolation structure includes: forming an isolation structure material layer on the substrate, wherein the isolation structure material layer covers the side wall of the initial convex layer; and after the isolation structure material layer is formed, etching back the isolation structure material layer to form the initial isolation structure.
Optionally, the method for forming the semiconductor structure further includes: after forming the second channel layer, etching a portion of the initial isolation structure to form an isolation structure covering sidewalls of the bump layer and exposing sidewalls of the first sacrificial layer, the first channel layer, the second sacrificial layer, and the second channel layer.
Optionally, the step of forming the first sacrificial layer, the first channel layer, the second sacrificial layer and the second channel layer comprises: forming the first sacrificial layer on the convex layer; forming the first channel layer on the first sacrificial layer; forming the second sacrificial layer on the first channel layer; and forming the second channel layer on the second sacrificial layer.
Optionally, the step of forming the first sacrificial layer on the convex layer includes: epitaxially growing a first sacrificial material layer on the top surface of the convex layer, the first sacrificial material layer also being located on a portion of the initial isolation structure; carrying out planarization treatment on the first sacrificial material layer until the first sacrificial material layer on part of the initial isolation structure is removed; and after the first sacrificial material layer is subjected to planarization treatment, etching back to remove a part of the first sacrificial material layer so as to form the first sacrificial layer.
Optionally, the step of forming the first channel layer on the first sacrificial layer includes: epitaxially growing the first channel material layer on the top surface of the first sacrificial layer, the first channel material layer also being located on a portion of the initial isolation structure; carrying out planarization treatment on the first channel material layer until the first channel material layer on part of the initial isolation structure is removed; and after the first channel material layer is subjected to planarization treatment, a part of the first channel material layer is removed through back etching to form the first channel layer.
Optionally, the step of forming the second sacrificial layer on the first channel layer comprises: epitaxially growing the second sacrificial material layer on a top surface of the first channel layer, the second sacrificial material layer also being on a portion of the initial isolation structure; carrying out planarization treatment on the second sacrificial material layer until the second sacrificial material layer on part of the initial isolation structure is removed; and after the second sacrificial material layer is subjected to planarization treatment, etching back to remove a part of the second sacrificial material layer so as to form the second sacrificial layer.
Optionally, the step of forming the second channel layer on the second sacrificial layer includes: epitaxially growing a second channel material layer on a top surface of the second sacrificial layer, the second channel material layer also being located on a portion of the initial isolation structure; carrying out planarization treatment on the second channel material layer until the second channel material layer positioned on part of the initial isolation structure is removed; and after the second channel material layer is subjected to planarization treatment, a part of the second channel material layer is removed through back etching to form the second channel layer.
Optionally, the second mask layer and the first mask layer are made of the same material.
Optionally, the second mask layer and the first mask layer are both made of silicon nitride.
Optionally, the first sacrificial layer and the second sacrificial layer are both made of silicon germanium.
Optionally, the thickness of the first sacrificial layer is 5 to 100 angstroms, and the thickness of the second sacrificial layer is 5 to 100 angstroms.
Optionally, the material of the initial isolation structure is silicon oxide.
Another aspect of the present application provides a semiconductor structure comprising: a substrate; a convex layer on the substrate; a first channel layer on and discrete from the raised layer, the first channel layer for constituting a channel of a first type of GAA transistor; a second channel layer on and separate from the first channel layer, the second channel layer for constituting a channel of a second type of GAA transistor, the first type and the second type being opposite.
Optionally, the first type GAA transistor is P-type and the second type GAA transistor is N-type; or the first type GAA transistor is of an N type, and the second type GAA transistor is of a P type.
Optionally, the first channel layer is made of silicon, the second channel layer is made of silicon, the first sacrificial layer is made of silicon germanium, and the second sacrificial layer is made of silicon germanium.
Optionally, the semiconductor structure further comprises: and the isolation structure is positioned on the substrate and covers the side wall of the convex layer.
Optionally, the material of the isolation structure is silicon oxide.
Another aspect of the present application provides a semiconductor structure comprising: a substrate; a convex layer on the substrate; a first channel layer on and discrete from the raised layer, the first channel layer for constituting a channel of a first type of GAA transistor; a second channel layer on and separate from the first channel layer, the second channel layer for constituting a channel of a second type of GAA transistor, the first type and the second type being opposite.
Optionally, the first type GAA transistor is P-type and the second type GAA transistor is N-type; or the first type GAA transistor is of an N type, and the second type GAA transistor is of a P type.
Optionally, the first channel layer is made of silicon, the second channel layer is made of silicon, the first sacrificial layer is made of silicon germanium, and the second sacrificial layer is made of silicon germanium.
Optionally, the material of the isolation structure material layer is silicon oxide.
Optionally, the semiconductor structure further comprises: and the isolation structure is positioned on the substrate and covers the convex layer.
The technical scheme of this application has following beneficial effect:
firstly, the process of etching the initial substrate to form the initial convex layer and the grooves on the two sides of the initial convex layer is an independent process, and other materials are not involved, so that the increase of the types of etching byproducts can not be caused, the adverse effect of the increase of the types of the etching byproducts on the groove forming process can be avoided, and the grooves with basically consistent depth can be finally obtained.
Secondly, the deposition or the back etching of the first sacrificial layer, the first channel layer, the second sacrificial layer or the second channel layer are independent processes, and other materials are not involved, so that the increase of the types of the etching byproducts is not caused, and the adverse effect of the increase of the types of the etching byproducts on the forming process of each layer can be avoided.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application.
FIG. 1 is a flow chart of a method of forming a semiconductor structure;
FIG. 2 is a schematic view of a semiconductor structure formed in accordance with the method of forming the semiconductor structure of FIG. 1;
FIG. 3 is a schematic view of a semiconductor structure formed under different etch process parameters according to the method of forming the semiconductor structure of FIG. 1;
FIG. 4 is a flow chart of a method of forming a semiconductor structure according to one embodiment of the present application;
fig. 5 to 21 are schematic views illustrating a semiconductor structure forming process according to an embodiment of the present disclosure;
fig. 22 is a perspective view of a semiconductor structure according to an embodiment of the present application;
fig. 23 to 28 are schematic views illustrating a process of forming a CFET from a semiconductor structure according to an embodiment of the present application.
Detailed Description
As mentioned in the background, the prior art methods of forming CFETs are in need of improvement.
Fig. 1 shows a flow chart of a method of forming a semiconductor structure, the method comprising: providing an initial substrate, wherein the initial substrate comprises a first channel film, a sacrificial film, a second channel film and a hard mask which are sequentially stacked from bottom to top; and etching the hard mask, the second channel film, the sacrificial film, the first channel film and part of the initial substrate to respectively form a hard mask layer, a second channel layer, a sacrificial layer, a first channel layer and a substrate convex layer.
The semiconductor structure shown in fig. 2 may be formed by the above method, and includes a substrate 1, a substrate bump layer 2 located above the substrate 1, a first channel layer 4 located above the substrate bump layer 2, a second channel layer 6 located above the first channel layer 4, and a hard mask layer 7 located above the second channel layer 6. As can be seen, the width of the first channel layer 4 is smaller than the width of the substrate bump layer 2 and the width of the second channel layer 6 because, during etching of the nanosheet stack, the etching rate of the first channel layer 4 composed of silicon germanium (SiGe) is typically greater than the etching rates of the substrate bump layer 2 and the second channel layer 6 composed of silicon (Si), which results in the first channel layer 4 being consumed faster during etching and thus becoming narrower than the second channel layer 6. In addition, since the substrate bump layer 2, the first channel layer 4 and the second channel layer 6 are etched in the same process, more etching byproducts (e.g., volatile polymers) are generated simultaneously during the etching process, which affects the uniformity of the etching process and thus causes the etched trenches to have different depths.
If milder etch process parameters are selected to reduce the effects of etch by-products, the method can form the semiconductor structure shown in fig. 3, as can be seen, the hard mask layer 7 on the top is excessively consumed due to the longer etching time, which leads to the problem of insufficient residual thickness.
In order to solve the above technical problem, an embodiment of the present application provides a method for forming a semiconductor structure, which includes the following steps with reference to fig. 4:
step S1: forming a substrate and an initial convex layer on the substrate;
step S2: forming an initial isolation structure on the substrate to cover the side wall of the initial convex layer;
step S3: after the initial isolation structure is formed, etching back part of the initial convex layer to form a groove in the initial isolation structure and enable the initial convex layer to form a convex layer positioned at the bottom of the groove;
step S4: and sequentially forming a first sacrificial layer, a first channel layer, a second sacrificial layer and a second channel layer in the groove from bottom to top.
The above steps and their sub-steps are explained in detail below with reference to fig. 5 to 22.
As shown in fig. 5, an initial substrate 10 is provided, and a first mask layer 130 is formed on a portion of the surface of the initial substrate 10.
The material of the initial substrate 10 may be a group IV semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or may be a group III-V semiconductor material, such as indium gallium arsenide (InGaAs), indium arsenide (InAs), indium antimonide (InSb), indium gallium antimonide (InGaSb). The material of the initial substrate 10 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. In this embodiment, the material of the initial substrate 10 is silicon.
The material of the first mask layer 130 may be silicon oxide, titanium nitride (TiN), silicon nitride, or the like. In the present embodiment, the first Mask layer 130 is a Hard Mask (Hard Mask) made of silicon nitride. The first mask layer 130 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. The patterning of the first mask layer 130 may be achieved by a photolithography process. For example, a photoresist may be spin-coated on the surface of the first mask layer 130, a trench pattern may be formed in the photoresist after the exposure and development process, the first mask layer 13 may be etched by a dry etching process or a wet etching process to form a mask pattern, and oxygen plasma may be introduced after the etching process to ash and remove the remaining photoresist.
As shown in fig. 6, a portion of the initial substrate 10 is etched using the first mask layer 130 as a mask to form the substrate 110 and the initial convex layer 120 on the substrate 110, wherein the first mask layer 130 is located on the top surface of the initial convex layer 120 after the initial convex layer 120 is formed.
The process of etching a portion of the initial substrate 10 may be a dry etch (e.g., plasma etch, atomic layer etch) or a wet etch.
As shown in fig. 7, an isolation structure material layer 145 is formed on the substrate 110, the isolation structure material layer 145 covering sidewalls of the initial convex layer 120 and sidewalls and a top of the first mask layer 130.
The material of the isolation structure material layer 145 may be an oxide, nitride, carbide, boride, or the like. For example, the material of the isolation structure material layer 145 may be silicon oxide, aluminum oxide, silicon nitride, boron nitride, silicon carbide, or the like. In the present embodiment, the material of the isolation structure material layer 145 is silicon oxide. The isolation structure material layer 145 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.
As shown in fig. 8, the isolation structure material layer 145 is processed by planarization such that the top surface of the isolation structure material layer 145 is flush with the top surface of the first mask layer 130.
The Planarization process may be Chemical Mechanical Polishing (CMP).
As shown in fig. 9, the isolation structure material layer 145 is etched back to form the initial isolation structures 140.
In some embodiments, the process of etching back the isolation structure material layer 145 also exposes a portion of the sidewalls of the initial bump layer 120. The initial isolation structure 140 may cover a portion of the sidewalls of the initial convex layer 120. In the back etching of the isolation structure material layer 145, the thickness of the isolation structure material layer 145 removed by the back etching may be 1.5 to 2.5 times the thickness of the first mask layer 130. The process of etching back the isolation structure material layer 145 may be dry etching (e.g., plasma etching, atomic layer etching) or wet etching.
As shown in fig. 10, a second mask layer 134 is formed on the surface of the initial isolation structure 140, and the second mask layer 134 covers a portion of the sidewalls of the initial convex layer 120 and the sidewalls and the top of the first mask layer 130.
The material of the second mask layer 134 may be silicon oxide, titanium nitride, silicon nitride, etc. In the present embodiment, the second Mask layer 134 is a Hard Mask (Hard Mask) made of silicon nitride (SiN). The second mask layer 134 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.
As shown in fig. 11, a portion of the second mask layer 134 and the first mask layer 130 are planarized until the top surface of the initial convex layer 120 is exposed.
At this time, the second mask layer 134 may cover only a portion of the sidewalls of the initial convex layer 120 and the sidewalls of the first mask layer 130. Specifically, the top surface of the second mask layer 134 remaining after the planarization is flush with the top surface of the initial convex layer 120. The planarization process may be chemical mechanical polishing.
As shown in fig. 12, a portion of the initial bump layer 120 is etched back using the second mask layer 134 as a mask to form a recess in the initial isolation structure 140, and the initial bump layer 120 forms a bump layer 122 at the bottom of the recess.
The top surface of the initial isolation structures 140 may be lower than the top surface of the initial bump layer 120 before etching back portions of the initial bump layer 120. The process of etching back the initial convex layer 120 may be dry etching or wet etching. The thickness of the portion of the initial bump layer 120 removed during the etch-back process is 2/3 to 3/4 the thickness of the initial substrate 10. In some embodiments, a chemical dry etch back may be applied to the initial bump layer 120 until the recess reaches a predetermined depth. In some embodiments, where the initial bump layer 120 is etched back and forth using a plasma etch process, the Pressure of the plasma etch, and thus the height of the bump layer 122, may be controlled by an Adaptive Pressure Controller (APC).
Next, the first sacrificial layer 152, the first channel layer 162, the second sacrificial layer 172, and the second channel layer 182 are sequentially formed in the groove from bottom to top. Specifically, this step may include: forming a first sacrificial layer 152 on the convex layer 122; forming a first channel layer 162 on the first sacrificial layer 152; forming a second sacrificial layer 172 on the first channel layer 162; and forming a second channel layer 182 on the second sacrificial layer 172.
As shown in fig. 13, a first sacrificial material layer 150 is formed on the top surface of the convex layer 122.
The first sacrificial material layer 150 may cover a portion of sidewalls of the initial isolation structure 140 and sidewalls of the second mask layer 134. The material of the first sacrificial material layer 150 may be silicon germanium (SiGe), gallium arsenide (gaas), or the like. In the embodiment, the material of the first sacrificial material layer 150 is silicon germanium, for example, the content of germanium in the first sacrificial material layer 150 may be 25% to 75%. The first sacrificial material layer 150 may be formed by epitaxial growth.
For example, forming the first sacrificial material layer 150 on the convex layer 122 may include: epitaxially growing a first sacrificial material layer 150 on the top surface of the convex layer 122, the first sacrificial material layer 150 also being located on a portion of the initial isolation structure 140 (or the second mask layer 134); the first sacrificial material layer 150 is planarized until the first sacrificial material layer 150 on a portion of the initial isolation structure 140 (or the second mask layer 134) is removed such that a top surface of the first sacrificial material layer 150 is flush with a top surface of the second mask layer 134.
As shown in fig. 14, the first sacrificial material layer 150 is etched back to form a first sacrificial layer 152.
During the back etching of the first sacrificial material layer 150, a portion of the sidewalls of the initial isolation structure 140 and the sidewalls of the second mask layer 134 are exposed. The first sacrificial layer 152 serves as a separation layer between the convex layer 122 and a first channel layer 162 formed in a subsequent process and is to be removed in the subsequent process. In some embodiments, the process of etching back the first sacrificial material layer 150 is a chemical dry etch back. In some embodiments, where the first sacrificial material layer 150 is etched back and forth using a plasma etch process, the pressure of the plasma etch, and thus the height of the first sacrificial layer 152, may be controlled by an adaptive pressure regulator.
As shown in fig. 15, a first channel material layer 160 is formed on the top surface of the first sacrificial layer 152.
The first channel material layer 160 may cover a portion of sidewalls of the initial isolation structure 140 and sidewalls of the second mask layer 134. The material of the first channel material layer 160 may be a group IV semiconductor material, such as silicon, germanium, silicon-on-insulator, germanium-on-insulator, etc., or may be a group III-V semiconductor material, such as indium gallium arsenide, indium antimonide, indium gallium antimonide. In the present embodiment, the material of the first channel material layer 160 is silicon. The first channel material layer 160 may be formed by epitaxial growth.
For example, forming the first channel material layer 160 on the first sacrificial layer 152 may include: epitaxially growing a first channel material layer 160 on the top surface of the first sacrificial layer 152, the first channel material layer 160 may also be located on a portion of the initial isolation structure 140 (or the second mask layer 134); the first channel material layer 160 is planarized until a portion of the first channel material layer 160 on the initial isolation structure 140 (or the second mask layer 134) is removed such that a top surface of the first channel material layer 160 is flush with a top surface of the second mask layer 134. The thickness of the first sacrificial layer 152 may be 5 to 100 angstroms.
As shown in fig. 16, the first channel material layer 160 is etched back to form a first channel layer 162.
During the etch back of the first channel material layer 160, a portion of the sidewalls of the initial isolation structure 140 and the sidewalls of the second mask layer 134 are exposed. In some embodiments, the process of etching back the first channel material layer 160 is a chemical dry etch back. In some embodiments, where the first channel material layer 160 is etched back and forth using a plasma etch process, the pressure of the plasma etch, and thus the height of the first channel layer 162, may be controlled by an adaptive pressure regulator. The first channel layer 162 may serve as a channel of an n-type FET or a p-type FET and be complementary to a channel type of the second channel layer 182.
As shown in fig. 17, a second sacrificial material layer 170 is formed on the top surface of the first channel layer 162.
The second sacrificial material layer 170 may cover a portion of sidewalls of the initial isolation structure 140 and sidewalls of the second mask layer 134. The material of the second sacrificial material layer 170 may be silicon germanium (SiGe), gallium arsenide (gaas), or the like. In the embodiment, the material of the second sacrificial material layer 170 is silicon germanium, for example, the content of germanium in the second sacrificial material layer 170 may be 25% to 75%. The second sacrificial material layer 170 may be formed by epitaxial growth.
For example, forming the second sacrificial material layer 170 on the first channel layer 162 may include: epitaxially growing a second sacrificial material layer 170 on the top surface of the first channel layer 162, the second sacrificial material layer 170 also being located on a portion of the initial isolation structure 140 (or the second mask layer 134); the second sacrificial material layer 170 is planarized until the second sacrificial material layer 170 on a portion of the initial isolation structure 140 (or the second mask layer 134) is removed such that a top surface of the second sacrificial material layer 170 is flush with a top surface of the second mask layer 134.
As shown in fig. 18, the second sacrificial material layer 170 is etched back to form a second sacrificial layer 172.
During the etch back of the second sacrificial material layer 170, a portion of the sidewalls of the initial isolation structure 140 and the sidewalls of the second mask layer 134 are exposed. The second sacrificial layer 172 serves as a separation layer between the first channel layer 162 and a second channel layer 182 formed in a subsequent process and is to be removed in the subsequent process. In some embodiments, the process of etching back the second sacrificial material layer 170 is a chemical dry etch back. In some embodiments, where the second sacrificial material layer 170 is etched back and forth using a plasma etch process, the pressure of the plasma etch, and thus the height of the second sacrificial layer 172, may be controlled by an adaptive pressure regulator. The thickness of the second sacrificial layer 172 may be 5 to 100 angstroms.
As shown in fig. 19, a second channel material layer 180 is formed on the top surface of the second sacrificial layer 172.
The second channel material layer 180 may cover a portion of sidewalls of the initial isolation structure 140 and sidewalls of the second mask layer 134. The material of the second channel material layer 180 may be a group IV semiconductor material, such as silicon, germanium, silicon-on-insulator, germanium-on-insulator, etc., or may be a group III-V semiconductor material, such as indium gallium arsenide, indium antimonide, indium gallium antimonide. In the present embodiment, the material of the second channel material layer 180 is silicon. The second channel material layer 180 may be formed by epitaxial growth.
For example, forming the second channel material layer 180 on the second sacrificial layer 172 may include: epitaxially growing a second channel material layer 180 on the top surface of the second sacrificial layer 172, the second channel material layer 180 may also be located on a portion of the initial isolation structure 140 (or the second mask layer 134); the second channel material layer 180 is planarized until a portion of the second channel material layer 180 on the initial isolation structure 140 (or the second mask layer 134) is removed such that a top surface of the second channel material layer 180 is flush with a top surface of the second mask layer 134.
As shown in fig. 20, the second channel material layer 180 is etched back to form a second channel layer 182.
During the etch back of the second channel material layer 180, portions of the sidewalls of the initial isolation structure 140 and the sidewalls of the second mask layer 134 are exposed. In some embodiments, the process of etching back the second channel material layer 180 is a chemical dry etch back. In some embodiments, where the second channel material layer 180 is etched back and forth using a plasma etch process, the pressure of the plasma etch, and thus the height of the second channel layer 182, may be controlled by an adaptive pressure regulator. The first channel layer 162 may be used to constitute a channel of a first type of GAA transistor and the second channel layer 182 may be used to constitute a channel of a second type of GAA transistor, the first type and the second type being opposite.
As shown in fig. 21, the second mask layer 134 is removed and a portion of the initial isolation structure 140 is removed to form an isolation structure 142.
The second mask layer 134 may be removed by various suitable physical or chemical means. For example, the second mask layer 134 may be removed by a planarization process, such as CMP, or other etching process. A portion of the initial isolation structure 140 may be removed by a dry etch or a wet etch process. The isolation structure 142 covers sidewalls of the bump layer 122 and exposes sidewalls of the first sacrificial layer 152, the first channel layer 162, the second sacrificial layer 172, and the second channel layer 182.
In the technical scheme of the application, the etching of the first sacrificial layer 152, the first channel layer 162, the second sacrificial layer 172 and the second channel layer 182 is performed independently, so that a process flow for etching multiple layers of materials simultaneously does not exist, the condition that the final widths of the layers are different due to different etching ratios when multiple material layers are etched simultaneously is avoided, and adverse effects such as different depths of trenches and excessive consumption of mask layers caused by the simultaneous generation of multiple etching byproducts are also avoided.
Fig. 22 is a perspective view of a semiconductor structure according to an embodiment of the present application.
A process flow from the semiconductor structure shown in fig. 22 to a CFET will be described with reference to fig. 23 to 28.
As shown in fig. 23, a dummy gate structure 400 is formed, the dummy gate structure 400 covering a portion of the top of the isolation structure 142, a portion of the sidewall of the first sacrificial layer 152, a portion of the sidewall of the first channel layer 162, a portion of the sidewall of the second sacrificial layer 172, and a portion of the sidewall and a portion of the top of the second channel layer 182.
After the dummy gate structure 400 is formed, a first opening (not shown) may be formed at one side of the dummy gate structure 400, the first opening penetrating the second channel layer 182, the second sacrificial layer 172, the first channel layer 162, and the first sacrificial layer 152, and a second opening (not shown) may be formed at the other side of the dummy gate structure 400, the second opening penetrating the second channel layer 182, the second sacrificial layer 172, the first channel layer 162, and the first sacrificial layer 152. A first source (not shown), a first isolation layer (not shown), and a first drain (not shown) are sequentially formed in the first opening from bottom to top, and a second source (not shown), a second isolation layer (not shown), and a second drain (not shown) are sequentially formed in the second opening from bottom to top.
As shown in fig. 24, an interlayer dielectric layer 300 is formed, where the interlayer dielectric layer 300 covers a portion of the top of the isolation structure 142, a portion of the sidewall of the first sacrificial layer 152, a portion of the sidewall of the second sacrificial layer 172, a portion of the sidewall of the first channel layer 162, a portion of the sidewall and a portion of the top of the second channel layer 182, the sidewall of the first source electrode, the sidewall of the first isolation layer, the sidewall and the top of the second source electrode, the sidewall of the second drain electrode, the sidewall of the second isolation layer, and the sidewall and the top of the second drain electrode.
As shown in fig. 25, the dummy gate structure 400 is removed to form the third opening 310.
As shown in fig. 26, the first sacrificial layer 152 and the second sacrificial layer 172 located within the third opening 310 are removed.
As shown in fig. 27, a gate structure 410 is formed within the third opening 310, the gate structure 410 surrounding the first channel layer 162 and the second channel layer 182.
Fig. 28 shows the internal structure of fig. 27 (the interlayer dielectric layer 300 is removed), and it is to be noted that, in fig. 28, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are not shown.
Correspondingly, the embodiment of the application also provides a semiconductor structure. The semiconductor structure may include: to the substrate 110; a convex layer 122 on the substrate 110; a first channel layer 162 on the convex layer 122 and separated from the convex layer 122, the first channel layer 162 being used to constitute a channel of the first type GAA transistor; and a second channel layer 182 on the first channel layer 162 and separated from the first channel layer 162, the second channel layer 182 being used to constitute a channel of a second type GAA transistor, the first type and the second type being opposite.
In some embodiments, the first type GAA transistors are P-type and the second type GAA transistors are N-type; or the first type GAA transistor is of an N type, and the second type GAA transistor is of a P type.
In some embodiments, the material of the first channel layer 162 is silicon, the material of the second channel layer 182 is silicon, the material of the first sacrificial layer 152 is silicon germanium, and the material of the second sacrificial layer 172 is silicon germanium.
In some embodiments, the semiconductor structure further comprises an isolation structure located on the substrate 110 and covering the convex layer 122. In some embodiments, the material of the isolation structure 142 is silicon oxide.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this application and are within the spirit and scope of the exemplary embodiments of the application.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
forming a substrate and an initial convex layer on the substrate;
forming an initial isolation structure on the substrate to cover the side wall of the initial convex layer;
after the initial isolation structure is formed, etching back part of the initial convex layer to form a groove in the initial isolation structure and enable the initial convex layer to form a convex layer positioned at the bottom of the groove; and
and sequentially forming a first sacrificial layer, a first channel layer, a second sacrificial layer and a second channel layer in the groove from bottom to top.
2. The method of forming a semiconductor structure of claim 1, wherein the steps of forming the substrate and the initial convex layer comprise:
providing an initial substrate, wherein a first mask layer is formed on part of the surface of the initial substrate; and
and etching part of the initial substrate by taking the first mask layer as a mask to form the substrate and the initial convex layer positioned on the substrate, wherein the first mask layer is positioned on the top surface of the initial convex layer after the initial convex layer is formed.
3. The method of claim 1, wherein a top surface of said initial convex layer has a first mask layer prior to forming said initial isolation structure; before etching back part of the initial convex layer, the top surface of the initial isolation structure is lower than that of the initial convex layer;
the method for forming the semiconductor structure further comprises the following steps:
before the initial convex layer is etched back, a second mask layer is formed on the surface of the initial isolation structure, and the second mask layer covers partial side walls of the initial convex layer and side walls of the first mask layer;
before etching back the part of the initial convex layer, flattening the second mask layer and the first mask layer until the top surface of the initial convex layer is exposed;
etching back part of the initial convex layer by taking the second mask layer as a mask; and
removing the second mask layer after forming the first sacrificial layer, the first channel layer, the second sacrificial layer, and the second channel layer.
4. The method of forming a semiconductor structure of claim 1, wherein the method of forming the initial isolation structure comprises:
forming an isolation structure material layer on the substrate, wherein the isolation structure material layer covers the side wall of the initial convex layer; and
after the isolation structure material layer is formed, etching back the isolation structure material layer to form the initial isolation structure.
5. The method of forming a semiconductor structure of claim 1, further comprising:
after forming the second channel layer, etching a portion of the initial isolation structure to form an isolation structure covering sidewalls of the bump layer and exposing sidewalls of the first sacrificial layer, the first channel layer, the second sacrificial layer, and the second channel layer.
6. The method of forming a semiconductor structure of claim 1, wherein the steps of forming the first sacrificial layer, the first channel layer, the second sacrificial layer, and the second channel layer comprise:
forming the first sacrificial layer on the convex layer;
forming the first channel layer on the first sacrificial layer;
forming the second sacrificial layer on the first channel layer; and
forming the second channel layer on the second sacrificial layer.
7. The method of forming a semiconductor structure of claim 6, wherein the step of forming the first sacrificial layer on the convex layer comprises:
epitaxially growing a first sacrificial material layer on a top surface of the convex layer 122, the first sacrificial material layer also being located on a portion of the initial isolation structure;
carrying out planarization treatment on the first sacrificial material layer until the first sacrificial material layer on part of the initial isolation structure is removed; and
and after the first sacrificial material layer is subjected to planarization treatment, etching back to remove a part of the first sacrificial material layer so as to form the first sacrificial layer.
8. The method of forming a semiconductor structure of claim 6, wherein the step of forming the first channel layer on the first sacrificial layer comprises:
epitaxially growing the first channel material layer on the top surface of the first sacrificial layer, the first channel material layer also being located on a portion of the initial isolation structure;
carrying out planarization treatment on the first channel material layer until the first channel material layer on part of the initial isolation structure is removed; and
and after the first channel material layer is subjected to planarization treatment, etching back to remove a part of the first channel material layer so as to form the first channel layer.
9. The method of forming a semiconductor structure of claim 6, wherein the step of forming the second sacrificial layer on the first channel layer comprises:
epitaxially growing the second sacrificial material layer on a top surface of the first channel layer, the second sacrificial material layer also being on a portion of the initial isolation structure;
carrying out planarization treatment on the second sacrificial material layer until the second sacrificial material layer on part of the initial isolation structure is removed; and
and after the second sacrificial material layer is subjected to planarization treatment, etching back to remove a part of the second sacrificial material layer so as to form the second sacrificial layer.
10. The method of forming a semiconductor structure of claim 6, wherein the step of forming the second channel layer on the second sacrificial layer comprises:
epitaxially growing a second channel material layer on a top surface of the second sacrificial layer, the second channel material layer also being located on a portion of the initial isolation structure;
carrying out planarization treatment on the second channel material layer until the second channel material layer on part of the initial isolation structure is removed; and
and after the second channel material layer is subjected to planarization treatment, etching back to remove a part of the second channel material layer so as to form the second channel layer.
11. The method of forming a semiconductor structure of claim 3, wherein the second mask layer and the first mask layer are comprised of a same material.
12. The method of claim 3, wherein the second mask layer and the first mask layer are both made of silicon nitride.
13. The method of forming a semiconductor structure of claim 1, wherein the first sacrificial layer and the second sacrificial layer are both silicon germanium.
14. The semiconductor structure of claim 1, wherein the first sacrificial layer has a thickness of 5 to 100 angstroms and the second sacrificial layer has a thickness of 5 to 100 angstroms.
15. The method of claim 1, wherein the initial isolation structure is formed of silicon oxide.
16. A semiconductor structure, comprising:
a substrate;
a convex layer on the substrate;
a first channel layer on and discrete from the raised layer, the first channel layer for constituting a channel of a first type of GAA transistor;
a second channel layer on and separate from the first channel layer, the second channel layer for constituting a channel of a second type of GAA transistor, the first type and the second type being opposite.
17. The semiconductor structure of claim 16, wherein the first type GAA transistor is P-type and the second type GAA transistor is N-type; or the first type GAA transistor is of an N type, and the second type GAA transistor is of a P type.
18. The semiconductor structure of claim 16, wherein the material of the first channel layer is silicon, the material of the second channel layer is silicon, the material of the first sacrificial layer is silicon germanium, and the material of the second sacrificial layer is silicon germanium.
19. The semiconductor structure of claim 16, further comprising: and the isolation structure is positioned on the substrate and covers the side wall of the convex layer.
20. The semiconductor structure of claim 19, wherein a material of the isolation structure is silicon oxide.
CN202010292058.3A 2020-04-14 2020-04-14 Method for forming semiconductor structure Pending CN113539966A (en)

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CN101719501A (en) * 2009-12-01 2010-06-02 中国科学院上海微系统与信息技术研究所 Hybrid orientation inversion mode all-around-gate CMOS field effect transistor
CN103238208A (en) * 2010-12-01 2013-08-07 英特尔公司 Silicon and silicon germanium nanowire structures
CN107004631A (en) * 2014-12-24 2017-08-01 英特尔公司 INGAAS EPI structures and wet etching process for realizing III V GAA in ART grooves
US20200098859A1 (en) * 2018-09-25 2020-03-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for making superimposed transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101719501A (en) * 2009-12-01 2010-06-02 中国科学院上海微系统与信息技术研究所 Hybrid orientation inversion mode all-around-gate CMOS field effect transistor
CN103238208A (en) * 2010-12-01 2013-08-07 英特尔公司 Silicon and silicon germanium nanowire structures
CN107004631A (en) * 2014-12-24 2017-08-01 英特尔公司 INGAAS EPI structures and wet etching process for realizing III V GAA in ART grooves
US20200098859A1 (en) * 2018-09-25 2020-03-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for making superimposed transistors

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