CN113539963A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN113539963A
CN113539963A CN202110652211.3A CN202110652211A CN113539963A CN 113539963 A CN113539963 A CN 113539963A CN 202110652211 A CN202110652211 A CN 202110652211A CN 113539963 A CN113539963 A CN 113539963A
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China
Prior art keywords
dielectric layer
sacrificial gate
layer
exposed
over
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Pending
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CN202110652211.3A
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Chinese (zh)
Inventor
魏宇晨
巫丰印
谢子逸
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113539963A publication Critical patent/CN113539963A/en
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    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer and the first dielectric layer are planarized and recessed with an upper portion of the sacrificial gate structure exposed and a lower portion of the sacrificial gate structure embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth dielectric layer and the third dielectric layer are planarized and the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.

Description

Method for manufacturing semiconductor device
Technical Field
Embodiments of the present application relate to a method of manufacturing a semiconductor device.
Background
As the semiconductor industry moves into nanotechnology process nodes for higher device densities, higher performance, and lower costs, challenges presented by manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate Field Effect Transistors (FETs), including fin-type FETs (finfets) and full-gate-all-around (GAA) FETs. In a FinFET, the gate electrode is adjacent to three sides of the channel region with a gate dielectric layer in between. The gate electrode of a FinFET comprises one or more layers of metal material formed by gate replacement techniques.
Disclosure of Invention
Some embodiments of the present application provide a method of manufacturing a semiconductor device, including: forming a sacrificial gate structure over a substrate, the sacrificial gate structure comprising a sacrificial gate electrode; forming a first dielectric layer over the sacrificial gate structure; forming a second dielectric layer over the first dielectric layer; planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer such that an upper portion of the sacrificial gate structure is exposed and a lower portion of the sacrificial gate structure is embedded in the first dielectric layer; forming a third dielectric layer over the exposed sacrificial gate structure and over the first dielectric layer; forming a fourth dielectric layer over the third dielectric layer; planarizing the fourth dielectric layer and the third dielectric layer such that the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer; and removing the sacrificial gate electrode.
Further embodiments of the present application provide a method of manufacturing a semiconductor device, including: forming sacrificial gate structures over a substrate, wherein each of the sacrificial gate structures includes a sacrificial gate electrode and an upper portion of each of the sacrificial gate structures is exposed while a lower portion of each of the sacrificial gate structures is embedded in a first dielectric layer; forming a second dielectric layer over the exposed sacrificial gate structure and over the first dielectric layer; forming a third dielectric layer over the second dielectric layer; planarizing the third dielectric layer and the second dielectric layer such that the sacrificial gate electrode is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer; and removing the sacrificial gate electrode from each of the sacrificial gate structures, thereby forming a gate spacer, wherein a recess amount at a roughness pattern region is 1nm to 5nm, wherein a distance between adjacent sacrificial gate structures in the roughness pattern region is 50nm or more.
Still further embodiments of the present application provide a method of manufacturing a semiconductor device, including: forming underlying structures over a substrate, wherein an upper portion of each of the underlying structures is exposed and a lower portion of each of the underlying structures is embedded in a first dielectric layer; forming a second dielectric layer over the exposed underlying structure and over the first dielectric layer; forming a third dielectric layer over the second dielectric layer; and planarizing the third dielectric layer and the second dielectric layer such that the underlying structure is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer, wherein planarizing the third dielectric layer and the second dielectric layer comprises: a first Chemical Mechanical Polishing (CMP) process for etching the third dielectric layer; a second chemical mechanical polishing process for etching the second dielectric layer, ending when a portion of the underlying structure is exposed; and a third chemical mechanical polishing process for recessing the second dielectric layer and the underlying structure.
Drawings
The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 illustrates one of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 illustrates one of the stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 3 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 4 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 5 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 6 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 7 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 8 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 9 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 10 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 11 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 12 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 13 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 14 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 15 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 16 illustrates one of the stages of a sequential process for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
Fig. 17A, 17B, 17C, and 17D illustrate various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the invention.
Fig. 18A, 18B, 18C, 18D and 18E illustrate various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the invention.
Fig. 19A, 19B, 19C and 19D illustrate one of the stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 20A, 20B and 20C illustrate one of the stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 21A, 21B and 21C illustrate one of the stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 22A, 22B and 22C illustrate one of the stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 23A, 23B and 23C illustrate various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the invention.
Fig. 24A, 24B and 24C illustrate various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired characteristics of the device. Further, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various components may be arbitrarily drawn in different scales for simplicity and clarity.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Further, the term "made of …" may mean "including" or "consisting of …".
In the gate replacement technique, a sacrificial gate structure (e.g., made of polysilicon) including a sacrificial gate electrode is first formed over a channel region and then replaced with a metal gate structure. In gate replacement techniques, various planarization operations, such as chemical mechanical polishing processes, are employed to planarize dielectric, polysilicon and/or metal layers. Furthermore, in some FinFET devices, after a gate replacement process to form a metal gate structure, an upper portion of the metal gate structure is recessed and a capping insulating layer is formed over the recessed gate structure to ensure isolation between the metal gate electrode and adjacent conductive contacts. In the present invention, a method of suppressing the dishing problem in the CMP operation and to improve the isolation characteristics of the capping insulating layer is provided.
Fig. 1-16 illustrate a sequential process for fabricating a FET device according to an embodiment of the present invention. It should be understood that for other embodiments of the method, additional operations may be provided before, during, and after the processes shown in fig. 1-16, and some of the operations described below may be replaced or eliminated. The order of operations/processes may be interchanged.
As shown in fig. 1, impurity ions (dopant) 12 are implanted into a silicon substrate 10 to form a well region. Ion implantation is performed to prevent punch-through effects.
In one embodiment, the substrate 10 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 10 may comprise a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In this embodiment, the substrate 10 is made of Si.
The substrate 10 may include one or more buffer layers (not shown) in its surface area. The buffer layer may be used to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layer may increase from 30 atomic% of the germanium of the bottom-most buffer layer to 70 atomic% of the germanium of the top-most buffer layer.
The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). Dopant 12 is Boron (BF), such as for an n-type Fin FET2) And phosphorus for p-type Fin FETs.
In fig. 2, a mask layer 15 is formed over a substrate 10. In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. In some embodiments, the first mask layer 15A is made of silicon nitride, and the second mask layer 15B is made of silicon oxide. In other embodiments, the first mask layer 15A is made of silicon oxide, and the second mask layer 15B is made of silicon nitride (SiN). The first and second mask layers are formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or other suitable processes including low pressure CVD (lpcvd) and plasma enhanced CVD (pecvd). The mask layer 15 is patterned into a mask pattern by using a patterning operation including photolithography and etching.
Next, as shown in fig. 3, the substrate 10 is patterned into a fin structure 20 extending in the X direction by using the patterned mask layer 15. In fig. 3, two fin structures 20 are arranged in the Y direction. However, the number of fin structures is not limited to two, and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of fin structure 20 to improve pattern fidelity in the patterning operation.
The fin structure 20 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes including a double patterning process or a multiple patterning process. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns having, for example, pitches smaller than those obtainable using a single, direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and then the remaining spacers may be used to pattern the fin structure.
After forming the fin structure, a layer of insulating material including one or more layers of insulating material is formed over the substrate such that the fin structure is fully embedded in the insulating layer. The insulating material for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. The annealing operation may be performed after the insulating layer is formed. A planarization operation, such as a Chemical Mechanical Polishing (CMP) method and/or an etch back method, is then performed, thereby exposing the upper surface of the fin structure 20 from the insulating material layer 30, as shown in fig. 4.
In some embodiments, one or more pad layers 22 are formed over the structure of fig. 3, as shown in fig. 4, prior to forming the layer of insulating material 30. The liner layer 22 comprises one or more of silicon nitride, SiON, SiCN, SiOCN, and silicon oxide.
Then, as shown in fig. 5, the insulating material layer 30 is recessed to form the isolation insulating layer 30 such that an upper portion of the fin structure 20 is exposed. With this operation, the fin structures 20 are electrically isolated from each other by an isolation insulation layer 30, also referred to as Shallow Trench Isolation (STI). The lower portion 11 of the fin structure is embedded in an isolation insulating layer 30.
After the isolation insulating layer 30 is formed, a sacrificial gate dielectric layer 42 is formed, as shown in fig. 6. The sacrificial gate dielectric layer 42 comprises one or more layers of insulating material, such as a silicon oxide based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 42 is in the range of about 1nm to about 5 nm.
Fig. 7 shows the structure after forming a sacrificial gate structure 40 over the exposed fin structure 20. The sacrificial gate structure includes a sacrificial gate electrode 44 and a sacrificial gate dielectric layer 42. A sacrificial gate structure 40 is formed over the portion of the fin structure that will become the channel region. The sacrificial gate structure 40 is formed by first blanket depositing a sacrificial gate dielectric layer 42 over the fin structure. A sacrificial gate electrode layer is then blanket deposited over the sacrificial gate dielectric layer and over the fin structures such that the fin structures are fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon, such as polysilicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. The mask layer includes a pad SiN layer 46 and a silicon oxide mask layer 48.
Next, a patterning operation is performed on the mask layer and the sacrificial gate electrode layer is patterned into a sacrificial gate structure 40, as shown in fig. 7. The patterning operation of the sacrificial gate structure 40 will be explained in more detail below.
In some embodiments, the sacrificial gate structure 40 includes a sacrificial gate dielectric layer 42, a sacrificial gate electrode layer 44 (e.g., polysilicon), a pad SiN layer 46, and a silicon oxide mask layer 48. By patterning the sacrificial gate structure 40, an upper portion of the fin structure 20 is partially exposed on opposing sides of the sacrificial gate structure 40, thereby defining source/drain (S/D) regions, as shown in fig. 7. In the present invention, the source and the drain are used interchangeably, and their structures are substantially the same. In fig. 7, one sacrificial gate structure is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X-direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.
After forming the sacrificial gate structure 40, a blanket layer 45 of insulating material for the sidewall spacers 45 is conformally formed by using CVD or other suitable method, as shown in fig. 8. Blanket layer 45 is deposited in a conformal manner such that it is formed to have substantially equal thickness on vertical surfaces, such as sidewalls, horizontal surfaces, and tops of the sacrificial gate structures. In some embodiments, blanket layer 45 is deposited to a thickness in the range of about 2nm to about 10 nm. In one embodiment, the insulating material of blanket layer 45 is a silicon nitride based material such as SiN, SiON, SiOCN, or SiCN and combinations thereof.
Furthermore, as shown in fig. 9, sidewall spacers 45 are formed on opposite sidewalls of the sacrificial gate structure, and subsequently, the fin structure of the S/D region is recessed downward below the upper surface of the isolation insulating layer 30. After forming the blanket layer 45, anisotropic etching is performed on the blanket layer 45 using, for example, Reactive Ion Etching (RIE). During the anisotropic etch process, most of the insulating material is removed from the horizontal surfaces, leaving a dielectric spacer layer on the vertical surfaces, such as the sidewalls of the sacrificial gate structure and the sidewalls of the exposed fin structure. The mask layer 48 may be exposed from the sidewall spacers. In some embodiments, an isotropic etch may then be performed to remove the insulating material from the upper portions of the S/D regions of the exposed fin structure 20.
Subsequently, the fin structure of the S/D region is recessed downward below the upper surface of the isolation insulating layer 30 by using dry etching and/or wet etching. As shown in fig. 9, the sidewall spacers 45 formed on the S/D regions of the exposed fin structure (fin sidewalls) partially remain. However, in other embodiments, the sidewall spacers 45 formed on the S/D regions of the exposed fin structure are completely removed. In the case of a GAA FET, the internal spacers are formed after recessing the S/D regions.
Subsequently, as shown in fig. 10, a source/drain (S/D) epitaxial layer 50 is formed. The S/D epitaxial layer 50 includes one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or Si, SiGe, Ge, GeSn and SiGeSn for p-channel FETs. The S/D layer 50 is formed by an epitaxial growth method using CVD, ALD, or Molecular Beam Epitaxy (MBE).
As shown in fig. 10, the S/D epitaxial layers are grown separately from the recessed fin structures. In some embodiments, the grown epitaxial layers merge over the isolation insulating layer and form voids 52.
Subsequently, an insulating liner layer 60 is formed as an etch stop layer, and then an interlayer dielectric (ILD) layer 65 is formed, as shown in fig. 11. The insulating liner layer 60 is made of a silicon nitride-based material, such as SiN, and serves as a contact etch stop layer in a subsequent etching operation. Materials for ILD layer 65 include compounds containing Si, O, C, and/or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for ILD layer 65. After the ILD layer 65 is formed, a planarization operation, such as CMP, is performed, exposing the top of the sacrificial gate electrode layer 44, as shown in fig. 11.
Next, as shown in fig. 12, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed, exposing the fin structure in the gate spacers 49. ILD layer 65 protects S/D structure 50 during removal of the sacrificial gate structure. The sacrificial gate structure may be removed using a plasma dry etch and/or a wet etch. When sacrificial gate electrode layer 44 is polysilicon and ILD layer 65 is silicon oxide, a wet etchant such as TMAH solution may be used to selectively remove sacrificial gate electrode layer 54. Thereafter, the sacrificial gate dielectric layer 42 is removed using a plasma dry etch and/or a wet etch.
After removing the sacrificial gate structure, a gate dielectric layer 82 is formed around the exposed fin structure 20, and a gate electrode layer 88 is formed on the gate dielectric layer 82, as shown in fig. 13.
In some embodiments, the gate dielectric layer 82 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and/or combinations thereof. Examples of high-k dielectric materials include HfO2、HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titania, hafnia-alumina (HfO)2-Al2O3) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interfacial layer formed between the channel layer and the dielectric material.
The gate dielectric layer 82 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 82 is formed using a highly conformal deposition process, such as ALD, to ensure that a gate dielectric layer with a uniform thickness is formed over the channel region. In some embodiments, the thickness of gate dielectric layer 82 is in the range of about 1nm to about 6 nm.
A gate electrode layer 88 is formed on the gate dielectric layer 82. Gate electrode 88 comprises one or more layers of conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof.
The gate electrode layer 88 may be formed by CVD, ALD, plating, or other suitable methods. A gate electrode layer is also deposited over the upper surface of ILD layer 65. The gate dielectric layer and gate electrode layer formed over ILD layer 65 are then planarized using, for example, CMP, until the top surface of ILD layer 65 is exposed.
After the planarization operation, the gate electrode layer 88 is recessed and a gate insulating cover layer 90 is formed over the recessed gate electrode 88, as shown in fig. 13. In some embodiments, the gate capping insulating layer 90 comprises one or more layers of a silicon nitride based material, such as SiN. The gate capping insulating layer 90 may be formed by depositing an insulating material and then a planarization operation.
In some embodiments of the present invention, one or more work function adjusting layers (not shown) are interposed between the gate dielectric layer 82 and the gate electrode 88. The work function adjusting layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC or a multilayer of two or more of these materials. For an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi is used as a work function adjusting layer, and for a p-channel FET, one or more of WN, WCN, W, Ru, Co, TiN, or TiSiN is used as a work function adjusting layer. The work function adjusting layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the work function adjusting layer may be formed separately for an n-channel FET and a p-channel FET, which may use different metal layers.
Subsequently, a contact hole 110 is formed in the ILD layer 65 by using dry etching, as shown in fig. 14. In some embodiments, an upper portion of the S/D epitaxial layer 50 is etched.
A silicide layer 120 is formed over the S/D epitaxial layer 50 as shown in fig. 15. The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. Then, a conductive material 130 is formed in the contact hole, as shown in fig. 16. The conductive material 130 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN.
It should be appreciated that the FinFET goes through further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.
Fig. 17A through 18E illustrate various views of the detailed sequential process of fig. 11 through 12, according to an embodiment of the present invention. It should be understood that for other embodiments of the method, additional operations may be provided before, during, and after the processes shown in fig. 17A-18E, and some of the operations described below may be replaced or eliminated. The order of operations/processes may be interchanged. Materials, processes, methods, dimensions, and/or configurations explained using the above embodiments may be applied to the following embodiments, and detailed descriptions thereof may be omitted.
After forming one or more sacrificial gate structures corresponding to fig. 10, a first dielectric layer 62 is formed to completely cover the sacrificial gate structures, and a second dielectric layer 64 made of a different material from the first dielectric layer 62 is further formed over the first dielectric layer 62, as shown in fig. 17A. In some embodiments, as shown in FIG. 17A, the sacrificial gate structure includes a fine pattern corresponding to a short channel FET (e.g., gate length Lg ≦ 20nm) and a coarse or larger pattern corresponding to a long channel FET (e.g., 50nm ≦ Lg ≦ 500 nm). Further, in some embodiments, the spacing between adjacent sacrificial gate structures varies between the same width as the fine pattern and about 2-5 times the width of the fine pattern, between 50nm and about 500 nm.
In some embodiments, the first dielectric layer 62 is made of a silicon oxide-based material, such as silicon oxide, SiON, and SiOC. In some embodiments, the second dielectric layer 64 is made of a silicon nitride-based material, such as silicon nitride, SiON, and SiCN. In some embodiments, the thickness of the second dielectric layer 64 is less than the thickness of the first dielectric layer 62. The first dielectric layer and the second dielectric layer are formed by LPCVD, plasma CVD, ALD, or any other suitable film forming method. In some embodiments, the second dielectric layer is not formed.
Then, as shown in fig. 17B, one or more planarization operations are performed on the first dielectric layer and the second dielectric layer to expose the sacrificial gate electrode 44 (polysilicon layer) of the sacrificial gate structure. In some embodiments, the planarization operation comprises a CMP operation. During the planarization operation, hard mask layers 46 and 48 are also removed.
In some embodiments, the planarization operation includes a first CMP process for etching primarily the second dielectric layer 64 and a second CMP process for subsequently etching the first dielectric layer 62, ending when the polysilicon layer of the sacrificial gate electrode is exposed.
Next, as shown in fig. 17C, the remaining first dielectric layer 62 is recessed to expose an upper portion of the sacrificial gate structure by one or more etching (e.g., plasma dry etching) operations. In some embodiments, after the planarization operation, the amount of recess D11 is about 10% to about 30% of the original depth D10 of the first dielectric layer 62, which is also measured from the top of the sacrificial gate structure. In some embodiments, D10 is in the range of about 100nm to about 200 nm. In some embodiments, D11 is in the range of about 10nm to about 60nm, and in other embodiments in the range of about 20nm to about 35 nm.
Subsequently, as shown in fig. 17D, a third dielectric layer 66 is formed to completely cover the sacrificial gate structure, and a fourth dielectric layer 68 made of a different material from the third dielectric layer 66 is further formed over the third dielectric layer 66.
In some embodiments, the third dielectric layer 66 is made of a silicon nitride-based material, such as silicon nitride, SiON, and SiCN. In some embodiments, the silicon nitride layer is doped with some impurities (diffused silicon nitride film). In some embodiments, the fourth dielectric layer 68 is made of a silicon oxide-based material, such as silicon oxide, SiON, TEOS, and SiOC. The third dielectric layer and the fourth dielectric layer are formed by LPCVD, plasma CVD, ALD, flowable CVD, or any other suitable film formation method.
In some embodiments, the deposition temperature is in the range of about 400 ℃ to about 600 ℃.
In some embodiments, the thickness of the third dielectric layer 66 is less than the thickness of the fourth dielectric layer 68.
In some embodiments, the thickness of the third dielectric layer 66 is in the range of about 50nm to about 100 nm. In some embodiments, the thickness of the third dielectric layer 66 is 2-3 times the depth of the depth D11. When the thickness is less than the range, the flatness of the dielectric layer after a subsequent planarization operation (CMP) may be insufficient, and when the thickness is greater than the range, some patterns of lower pattern density may suffer from dishing problems, and deposition and/or polishing time may increase, which increases manufacturing costs. In some embodiments, the thickness of the fourth dielectric layer 68 is in a range from about 100nm to about 200nm to improve planarity after a subsequent planarization (CMP) process.
Then, as shown in fig. 18A to 18C, a planarization operation is performed on the first dielectric layer and the second dielectric layer to expose the sacrificial gate electrode 44 of the sacrificial gate structure. In some embodiments, the planarization operation includes a first CMP process, a second CMP process, and a third CMP process, which are sequentially performed in this order. In the first to third CMP operations, different slurries and/or CMP pads are used.
In the first CMP operation, the fourth dielectric layer 68 is mainly etched. The first CMP operation is stopped at the surface of the third dielectric layer 66 by employing an endpoint detection technique. In some embodiments, the downward force of the CMP head is about greater than for all areasThe range of 0.1 up to about 2psi is relatively low to detect endpoint and stops on the third dielectric layer 66 to inhibit dishing problems. When the lower pressure is higher than this range, a dishing problem may occur in the oxide-rich region. In some embodiments, the slurry used in the first CMP operation includes a slurry containing CeO2The abrasive of (a), which etches silicon oxide at a high etch rate (e.g., 30-160nm/min) and does not substantially etch silicon nitride.
In some embodiments, an additional overpolish (overetch) is performed for about 10-30 seconds after the endpoint is detected. As shown in fig. 18A, in some embodiments, the remaining portion of the fourth dielectric layer remains due to the topography of the upper surface of the third dielectric layer 66.
The second CMP operation etches the third dielectric layer 66 and stops on the sacrificial gate electrode layer 44 (polysilicon layer), primarily by employing an endpoint detection technique. In some embodiments, the downward force of the CMP head is relatively low in the range of about greater than zero up to about 3 psi. In some embodiments, an additional overpolish is performed for about 5-15 seconds (or about 3-9% of the main etch time) after endpoint detection. When the overpolish time is too short, the third dielectric layer 66 may remain on the sacrificial gate electrode 44, and when the overpolish time is too long, a dishing problem at a large interval portion may occur (see fig. 18D). In some embodiments, in the second CMP operation, the sacrificial gate electrode layer 44 is lightly etched in an amount of 0.5nm to about 2.5 nm.
In some embodiments, the third CMP operation etches the third dielectric layer 66 and the sacrificial gate electrode layer 44. The third CMP operation is controlled by time. In some embodiments, the etch time of the third CMP operation is in a range from about 5 seconds to about 15 seconds. In some embodiments, in the second CMP operation, sacrificial gate electrode layer 44 is etched in an amount of 0.5nm to about 5 nm. In some embodiments, after the third CMP process, the remaining third dielectric layer 66 is in the range of about 15nm to about 30 nm. The structure of fig. 18C corresponds to the structure of fig. 11, and ILD layer 65 comprises first dielectric layer 62 and the remaining third dielectric layer 66. In some embodiments, the slurry used in the third CMP has a relatively high silicon nitride etch rate (e.g., 20-50nm/min) and a relatively low polysilicon etch rate. In some embodiments, the thickness D12 of the remaining third dielectric layer is about 10% to about 30%, in some embodiments about 90nm to about 180nm, of the height D13 of the sacrificial gate structure from the upper surface of the isolation insulating layer. In some embodiments, D12 is in the range of about 9nm to about 54nm, and in other embodiments, in the range of about 20nm to about 35 nm.
In some embodiments, dishing may be observed in large spacing portions or rough pattern portions between sacrificial gate structures (the distance between adjacent sacrificial gate structures is about 50nm or more (e.g., up to about 500nm)), as shown in fig. 18D. In some embodiments, the recess amount D20 measured from the top of the adjacent sacrificial gate structure is in a range of about 1nm to about 5 nm. In some embodiments, the difference between the maximum thickness (observed at, e.g., dense patterns) and the minimum thickness (observed at, e.g., rough patterns) of the remaining third dielectric layer 66 is in the range of about 2nm to about 10 nm.
Has high or medium hardness (e.g., hardness) in the first to third CMP processes>50 (shore D)) for high planarization efficiency requirements. When the hardness is less than about 50, polishing may not yield good planarization efficiency, dishing may occur in a low density pattern region, and the third dielectric layer 66 on the first dielectric layer 62 may be removed due to the dishing effect and does not protect the dielectric layer 62 in a subsequent process. In addition, in the first to third CMP processes, since the CMP process mainly etches silicon nitride, the post-CMP cleaning process includes a pre-cleaning process (e.g., platen polishing), an ultrasonic (megasonic) wafer cleaning process, a brush conditioning process, and an IPA (isopropyl alcohol) cleaning process. In some embodiments, the brush conditioning process includes a first step and a second step. In some embodiments, the first step includes a polishing operation using an acid solution with one or more chelating agents to capture metal ions during polishing, and the second step includes the use of a base solution (e.g., NH)4OH) to remove excess organic material.
After the CMP operation, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed, similar to fig. 12, to form gate spacers 49, as shown in fig. 18E.
The above planarization operation of fig. 17A to 18C may be applied to the planarization operation of other underlying structures, such as fin structures, metal gate electrodes, and contact and wiring structures.
Fig. 19A-22C illustrate various views of the detailed sequential process of fig. 12-13, in accordance with an embodiment of the present invention. It should be understood that for other embodiments of the method, additional operations may be provided before, during, and after the processes shown in fig. 19A-22C, and some of the operations described below may be replaced or eliminated. The order of operations/processes may be interchanged. Materials, processes, methods, dimensions, and/or configurations explained using the above embodiments may be applied to the following embodiments, and detailed descriptions thereof may be omitted.
Fig. 19A-19D show various views after removal of the sacrificial gate structure (sacrificial gate electrode 44 and sacrificial gate dielectric layer 42) to form gate spacers 49, as described with reference to fig. 12. Fig. 19A is a sectional view (plan view or projection view) along X1-X1 of fig. 19D, fig. 19B is a sectional view along Y1-Y1 of fig. 19D, and fig. 19C is a sectional view along Y2-Y2 of fig. 19D. In some embodiments, insulating liner layer 60, which serves as an etch stop layer, is formed prior to forming ILD layer 65. In some embodiments, the insulating liner layer 60 comprises silicon nitride.
In some embodiments, the upper portion of the gate sidewall spacers 45 are recessed, as shown in fig. 19B and 19C. In some embodiments, the gate sidewall spacers 45 are recessed during removal of the sacrificial gate dielectric layer, and in other embodiments, one or more dry and/or wet etching operations are performed to recess the gate sidewall spacers 45. In some embodiments, after recessing gate sidewall spacers 45, the uppermost surface is made of only silicon nitride-based material (e.g., silicon nitride) (layers 60 and 66).
Fig. 20A, 20B and 20C are enlarged views of the gate spacing after the formation of the metal gate structure. FIG. 20A corresponds to a short channel FET (e.g., 4nm ≦ Lg ≦ 10nm) including a gate electrode of a Static Random Access Memory (SRAM) cell, FIG. 20B corresponds to an intermediate channel FET (e.g., 12nm ≦ Lg ≦ 20nm) including a gate electrode of a logic circuit, and FIG. 20C corresponds to a long channel FET (50nm ≦ Lg ≦ 500 nm).
As shown in fig. 20A-20C, an interfacial layer 81 is formed on the channel region of the fin structure 20, and a gate dielectric layer 82 is formed over the interfacial layer and the inner walls of the gate sidewall spacers 45. In some embodiments, a gate dielectric layer 82 is formed over the upper surface of the etch stop layer 60 and the additional dielectric layer 66. In some embodiments, the gate dielectric layer 82 is formed by an ALD process to conformally form a layer over the high aspect ratio structures. In some embodiments, the aspect ratio (height/bottom diameter or area) of the gate spacers 49 is in the range of about 7 to about 25.
Then, a barrier layer 83 is formed over the gate dielectric layer 82. In some embodiments, barrier layer 83 comprises one or more layers of Ta, TaN, Ti, TiN, or TiSiN. In some embodiments, the thickness of the barrier layer is in the range of about 1nm to about 3 nm. In some embodiments, barrier layer 83 is not formed. In some embodiments, the thickness at the bottom of barrier layer 83 is thicker than the thickness at the sides. In some embodiments, the thickness at the bottom of barrier layer 83 is about 0.5 to three times the thickness at the sides.
In addition, one or more first work function adjusting material (WFM) layers are formed over the barrier layer 83. In some embodiments, first WFM layer 84 is a p-type WFM material such as WN, WCN, W, Ru, Co, TiN, or TiSiN. In some embodiments, the thickness of the first WFM layer is in the range of about 0.5nm to about 10nm, and in other embodiments in the range of about 1nm to about 2 nm. In some embodiments, the thickness at the bottom of the first WFM layer 84 is about 0.8 to twice the thickness at the sides. When the first WFM layer is made of TiN, the TiN layer is made of TiCl4And NH3Is formed. In some embodiments, the TiN layer includes Cl as an impurity. In some embodiments, the Ti concentration in the TiN layer is in a range of about 10 atomic% to about 80 atomic%. When the Ti concentration is too small, the resistance of the TiN layer increases, and when the Ti concentration is too high, Ti diffusion may cause various problems (e.g., punch-through).
In addition, in the second placeOne or more second WFM layers 85 are formed over a WFM layer 84. In some embodiments, the second WFM layer 85 is an n-type WFM material, such as TiAl, tisai, TiAlC, TaAl, or TaAlC. In some embodiments, the thickness of the second WFM layer is in the range of about 0.5nm to about 6nm, and in other embodiments in the range of about 2nm to about 5 nm. In some embodiments, the thickness at the bottom of the second WFM layer 85 is the same as the thickness at the sides or three times the thickness at the sides. After the WFM layer is formed, a body metal layer 86 is formed over the WFM layer. In some embodiments, a glue layer (not shown) is formed over the WFM layer prior to forming the body metal layer. In some embodiments, the glue layer comprises one or more of Ta, WCN, TaN, Ti, TiN, or TiSiN. The body metal layer 86 includes W, Ta, Sn, Nb, Ru, Co, or Mo. In certain embodiments, W is used. In some embodiments, the bulk metal layer 86 is formed by using a metal halide (chloride) gas (e.g., WCl)5、TaCl5、SnCl4、NbCl5Or MoCl4) The ALD process of (a). In some embodiments, the bulk metal layer 86 comprises a fluorine-free metal, for example, from WCl as a source gas5Fluorine-free W is formed. In some embodiments, in an n-type FET, the first WFM layer (p-type material layer) is not formed.
In some embodiments, as shown in fig. 20A, the second WFM layer 85 completely fills the gate space, and no body metal layer (e.g., W layer) is formed in the gate space. Furthermore, in some embodiments, the conductive layer is conformally formed in the gate spacers and thus does not completely fill the gate spacers of the long channel FET, as shown in fig. 20B. In this case, one or more insulating layers 89 are formed to fill the remaining space of the gate space, as shown in fig. 20C. The insulating layer 89 is formed by one or more deposition and CMP operations. In some embodiments, insulating layer 89 comprises silicon nitride.
Then, as shown in fig. 21A to 21C, the upper portion of the conductive layer formed in the gate spacer is recessed by one or more etching operations. In some embodiments, in the etching operation, the upper portions of sidewall spacers 45 and/or the upper portions of gate dielectric layer 82 are also etched. In some embodiments, the top of the WFM layer is lower than the top of the gate dielectric layer 82. In other embodiments, the top of the body metal layer 86 is higher than the top of either or both of the WFM layers. In the long channel FET, the insulating layer 89 is not substantially etched, as shown in fig. 21C.
In addition, as shown in fig. 22A to 22C, a gate capping insulating layer 90 is formed over the recessed conductive layer and the recessed gate dielectric layer 82. In some embodiments, the gate capping insulating layer 90 comprises silicon nitride, SiON, and/or SiOCN or any other suitable material. In the long channel FET as shown in fig. 22C, a gate cover insulating layer 90 fills the space between the gate sidewall spacer 45 and the insulating layer 89. In some embodiments, the conductive layers 83-86 of the gate electrode and the gate dielectric layer 82 have a U-shaped cross-section.
Fig. 23A to 23C illustrate respective views of the detailed sequential process of fig. 21A to 21C to 22A to 22C for forming the gate capping insulating layer 90 according to an embodiment of the present invention. It should be understood that for other embodiments of the method, additional operations may be provided before, during, and after the processes shown in fig. 23A-23C, and some of the operations described below may be replaced or eliminated. The order of operations/processes may be interchanged. Materials, processes, methods, dimensions, and/or configurations explained using the above embodiments may be applied to the following embodiments, and detailed descriptions thereof may be omitted.
After forming the recesses, as shown in fig. 21A-21C, one or more insulating layers 90L for a gate capping insulating layer are formed in the recesses and over ILD layers 62 and 66, as shown in fig. 23A. In some embodiments, the metal gate structure includes a short channel gate electrode corresponding to fig. 22A, a middle channel gate electrode corresponding to fig. 22B, and a long channel gate electrode corresponding to fig. 22C. Furthermore, in some embodiments, fin end caps 92 and 94 are formed over edge portions of the fin structure (not shown in fig. 23A-23C).
In some embodiments, insulating layer 90L comprises silicon nitride, SiON, and/or SiOCN or any other suitable material formed by LPCVD, plasma CVD, ALD, or any other suitable film forming method.
Then, as shown in fig. 23B and 23C, one or more planarization operations such as a CMP process are performed to planarize the insulating layer 90L, thereby forming the gate cover insulating layer 90. In some embodiments, the third dielectric layer 66 remaining on the first dielectric layer 62 is also removed during the planarization operation. In some embodiments, a residue of the third dielectric layer 66' remains on the first dielectric layer 62. In some embodiments, the thickness of the remaining third dielectric layer 66' is about 0.2nm to about 0.5 nm.
Fig. 24A-24C illustrate various views of the detailed sequential process of fig. 14-16 for forming source/drain contacts (and gate contacts) according to an embodiment of the present invention. It should be understood that for other embodiments of the method, additional operations may be provided before, during, and after the processes shown in fig. 24A-24C, and some of the operations described below may be replaced or eliminated. The order of operations/processes may be interchanged. Materials, processes, methods, dimensions, and/or configurations explained using the above embodiments may be applied to the following embodiments, and detailed descriptions thereof may be omitted.
After forming the gate cap insulating layer 90, a second ILD layer 100 is formed over the first ILD layer 65(62) and the metal gate structure with the gate cap insulating layer, as shown in fig. 24A. The second ILD layer 100 comprises silicon oxide, SiOC, SiOCN, or any other suitable dielectric material.
Source/drain contact openings 110 and gate contact openings 115 are then formed using one or more photolithography and etching operations, as shown in fig. 24B. In some embodiments, a portion of the source/drain epitaxial layer 50 and a portion of the metal gate electrode are also etched.
Next, as shown in fig. 24C, one or more conductive layers are formed in the openings 110 and 115, and a planarization operation is performed to form source/drain contacts 130 and gate contacts 135.
As shown in fig. 24B and 24C, the gate capping insulating layer 90 may electrically isolate the gate electrode from the source/drain contacts 130 even if the source/drain opening locations are not perfectly aligned with the underlying structure.
The various embodiments or examples described herein provide several advantages over the prior art. In the embodiment of the present invention, since the planarization operation used in the gate replacement process includes a plurality of film formation processes and a plurality of CMP operations, the dishing problem can be effectively suppressed.
It is to be understood that not all advantages need be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments may provide different advantages.
According to one aspect of the invention, in a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer and the first dielectric layer are planarized and the second dielectric layer and the first dielectric layer are recessed such that an upper portion of the sacrificial gate structure is exposed and a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth dielectric layer and the third dielectric layer are planarized such that the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed. In one or more of the above and below embodiments, the first dielectric layer comprises a silicon oxide-based material and the second dielectric layer comprises a different silicon nitride-based material than the first dielectric layer. In one or more of the above and below embodiments, the third dielectric layer comprises a silicon nitride-based material, and the fourth dielectric layer comprises a silicon oxide-based material different from the third dielectric layer. In one or more of the above and below embodiments, planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer includes: a first chemical mechanical polishing process (CMP) for etching the second dielectric layer; a second CMP process for etching the first dielectric layer, ending when the sacrificial gate electrode is exposed; and a third etching process for recessing the first dielectric layer. In one or more of the above and below embodiments, planarizing the fourth and third dielectric layers includes: a first Chemical Mechanical Polishing (CMP) process for etching the fourth dielectric layer; a second CMP process for etching the third dielectric layer, ending when the sacrificial gate electrode is exposed; and a third CMP process for recessing the third dielectric layer and the sacrificial gate electrode. In one or more of the above and following embodiments, the first CMP process includes a first endpoint detection and a first overpolish after detecting the first endpoint, the second CMP process includes a second endpoint detection and a second overpolish after detecting the second endpoint, and the third CMP process is time controlled without using the endpoint detection. In one or more of the above and below embodiments, the second overpolishing is performed for 5-15 seconds.
According to another embodiment of the present invention, in a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. Each of the sacrificial gate structures includes a sacrificial gate electrode, and an upper portion of each of the sacrificial gate structures is exposed while a lower portion of each of the sacrificial gate structures is embedded in the first dielectric layer. A second dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A third dielectric layer is formed over the second dielectric layer. The third dielectric layer and the second dielectric layer are planarized such that the sacrificial gate electrode is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed from each of the sacrificial gate structures, thereby forming a gate spacer. The amount of dishing at the roughness pattern region is 1nm to 5nm, wherein a distance between adjacent sacrificial gate structures in the roughness pattern region is 50nm or more. In one or more of the above and below embodiments, the second dielectric layer comprises a silicon nitride-based material, and the third dielectric layer comprises a silicon oxide-based material different from the second dielectric layer. In one or more of the above and below embodiments, planarizing the third and second dielectric layers includes: a first Chemical Mechanical Polishing (CMP) process for etching the third dielectric layer; a second CMP process for etching the second dielectric layer, ending when the sacrificial gate electrode is exposed; and a third CMP process for recessing the second dielectric layer and the sacrificial gate electrode. In one or more of the above and below embodiments, the first CMP process includes an end point checkAnd a first overpolish after detecting the endpoint, the second CMP process includes endpoint detection and a second overpolish after detecting the endpoint, and the third CMP process is time controlled without using endpoint detection. In one or more of the above and below embodiments, the second overpolishing is performed for 5-15 seconds. In one or more of the above and below embodiments, the second CMP process includes setting a down force of the CMP head to be greater than zero and up to 3 psi. In one or more of the above and below embodiments, the first CMP process includes using a CMP slurry including CeO2The polishing agent of (1). In one or more of the above and below embodiments, the second CMP process also etches the sacrificial gate electrode. In one or more of the above and below embodiments, further, a gate dielectric layer is formed in each of the gate spacers, a conductive layer is formed on the gate dielectric layer, the gate dielectric layer and the conductive layer are recessed to form recessed gate electrodes, and a gate capping insulating layer is formed on each of the recessed gate electrodes. In one or more of the above and following embodiments, in forming the gate capping insulating layer, a fourth dielectric layer is formed on each of the recessed gate electrodes and over the remaining third dielectric layer, and a planarization operation is performed to remove the fourth dielectric layer and a portion of the remaining third dielectric layer to expose the recessed first dielectric layer.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. An upper portion of each of the underlying structures is exposed, and a lower portion of each of the underlying structures is embedded in the first dielectric layer. A second dielectric layer is formed over the exposed underlying structure and over the first dielectric layer. A third dielectric layer is formed over the second dielectric layer and the third dielectric layer and the second dielectric layer are planarized such that underlying structures are exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer. Planarizing the third dielectric layer and the second dielectric layer includes: a first Chemical Mechanical Polishing (CMP) process for etching the third dielectric layer; a second CMP process for etching the second dielectric layer, ending when a portion of the underlying structure is exposed; and a third CMP process for recessing the second dielectric layer and underlying structures. In one or more of the above and following embodiments, the first CMP process includes a first endpoint detection and a first overpolish after detecting the first endpoint, the second CMP process includes a second endpoint detection and a second overpolish after detecting the second endpoint, and the third CMP process is time controlled without using the endpoint detection. In one or more of the above and below embodiments, the second overpolishing is performed for 5-15 seconds. In one or more of the above and below embodiments, the second dielectric layer comprises silicon nitride and the third dielectric layer comprises silicon oxide. In one or more of the above and below embodiments, the first dielectric layer includes silicon oxide.
The foregoing has outlined features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
forming a sacrificial gate structure over a substrate, the sacrificial gate structure comprising a sacrificial gate electrode;
forming a first dielectric layer over the sacrificial gate structure;
forming a second dielectric layer over the first dielectric layer;
planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer such that an upper portion of the sacrificial gate structure is exposed and a lower portion of the sacrificial gate structure is embedded in the first dielectric layer;
forming a third dielectric layer over the exposed sacrificial gate structure and over the first dielectric layer;
forming a fourth dielectric layer over the third dielectric layer;
planarizing the fourth dielectric layer and the third dielectric layer such that the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer; and
the sacrificial gate electrode is removed.
2. The method of claim 1, wherein the first dielectric layer comprises a silicon oxide-based material and the second dielectric layer comprises a different silicon nitride-based material than the first dielectric layer.
3. The method of claim 1, wherein the third dielectric layer comprises a silicon nitride-based material and the fourth dielectric layer comprises a different silicon oxide-based material than the third dielectric layer.
4. The method of claim 1, wherein planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer comprises:
a first Chemical Mechanical Polishing (CMP) process for etching the second dielectric layer;
a second chemical mechanical polishing process for etching the first dielectric layer, ending when the sacrificial gate electrode is exposed; and
a third etch process to recess the first dielectric layer.
5. The method of claim 1, wherein planarizing the fourth and third dielectric layers comprises:
a first Chemical Mechanical Polishing (CMP) process for etching the fourth dielectric layer;
a second chemical mechanical polishing process for etching the third dielectric layer, ending when the sacrificial gate electrode is exposed; and
a third chemical mechanical polishing process to recess the third dielectric layer and the sacrificial gate electrode.
6. The method of claim 5, wherein:
the first chemical mechanical polishing process includes a first endpoint detection and a first overpolish after detecting the first endpoint,
the second chemical mechanical polishing process includes a second endpoint detection and a second overpolish after detecting the second endpoint, and
the third chemical mechanical polishing process is time controlled without using endpoint detection.
7. The method of claim 6, wherein the second overpolishing is performed for 5-15 seconds.
8. A method of manufacturing a semiconductor device, comprising:
forming sacrificial gate structures over a substrate, wherein each of the sacrificial gate structures includes a sacrificial gate electrode and an upper portion of each of the sacrificial gate structures is exposed while a lower portion of each of the sacrificial gate structures is embedded in a first dielectric layer;
forming a second dielectric layer over the exposed sacrificial gate structure and over the first dielectric layer;
forming a third dielectric layer over the second dielectric layer;
planarizing the third dielectric layer and the second dielectric layer such that the sacrificial gate electrode is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer; and
removing the sacrificial gate electrode from each of the sacrificial gate structures, thereby forming a gate spacer,
wherein a recess amount at a roughness pattern region where a distance between adjacent sacrificial gate structures is 50nm or more is 1nm to 5 nm.
9. The method of claim 8, wherein the second dielectric layer comprises a silicon nitride-based material and the third dielectric layer comprises a different silicon oxide-based material than the second dielectric layer.
10. A method of manufacturing a semiconductor device, comprising:
forming underlying structures over a substrate, wherein an upper portion of each of the underlying structures is exposed and a lower portion of each of the underlying structures is embedded in a first dielectric layer;
forming a second dielectric layer over the exposed underlying structure and over the first dielectric layer;
forming a third dielectric layer over the second dielectric layer; and
planarizing the third dielectric layer and the second dielectric layer such that the underlying structure is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer,
wherein planarizing the third dielectric layer and the second dielectric layer comprises:
a first Chemical Mechanical Polishing (CMP) process for etching the third dielectric layer;
a second chemical mechanical polishing process for etching the second dielectric layer, ending when a portion of the underlying structure is exposed; and
a third chemical mechanical polishing process to recess the second dielectric layer and the underlying structure.
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