CN113539130B

CN113539130B - Display module assembly and display device

Info

Publication number: CN113539130B
Application number: CN202110814567.2A
Authority: CN
Inventors: 刘长瑜
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2021-07-19
Filing date: 2021-07-19
Publication date: 2023-04-11
Anticipated expiration: 2041-07-19
Also published as: WO2023000830A1; CN113539130A

Abstract

The embodiment of the application relates to a display module assembly and display device, and the display module assembly includes: the pixel circuit area is provided with a pixel circuit array; the grid driving area is provided with a grid driving circuit, the grid driving circuit is electrically connected with the pixel circuit array, and the grid driving circuit is used for generating a light-emitting control signal and outputting the light-emitting control signal to the pixel circuit array; the light emitting device area is provided with a light emitting device array, the light emitting device array is connected with the pixel circuit array, and the pixel circuit array drives the light emitting device array to emit light under the control of the light emitting control signal; the projection of the light emitting device area on the virtual plane along the third direction covers the projection of the pixel circuit area on the virtual plane along the third direction, the projection of the light emitting device area on the virtual plane along the third direction is at least partially overlapped with the projection of the grid drive area on the virtual plane along the third direction, the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction.

Description

Display module and display device

Technical Field

The embodiment of the application relates to the technical field of display, in particular to a display module and display equipment.

Background

With the continuous development of science and technology, people have higher and higher requirements on the appearance state of display equipment, comprehensive screens are popularized in the market, the frame of the display screen is reduced, and the screen occupation ratio is improved. However, the current bezel width still cannot meet the demand of people for narrow bezel display devices.

Disclosure of Invention

The embodiment of the application provides a display module assembly and display equipment, and the frame width of the display module assembly can be optimized.

A display module, comprising:

the pixel circuit area is provided with a pixel circuit array;

the grid driving area is provided with a grid driving circuit, the grid driving circuit is electrically connected with the pixel circuit array, and the grid driving circuit is used for generating a light-emitting control signal and outputting the light-emitting control signal to the pixel circuit array;

the light emitting device area is provided with a light emitting device array, the light emitting device array is connected with the pixel circuit array, and the pixel circuit array drives the light emitting device array to emit light under the control of a light emitting control signal;

the projection of the light emitting device region on a virtual plane along a third direction covers the projection of the pixel circuit region on the virtual plane along the third direction, the projection of the light emitting device region on the virtual plane along the third direction is at least partially overlapped with the projection of the gate driving region on the virtual plane along the third direction, the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction.

A display device, comprising: the display module is provided.

In the embodiment of the present application, the light emitting device region is provided with the light emitting device array, and the plane where the light emitting device array is located can be understood as a display surface, the display surface is perpendicular to the third direction, and the non-light emitting gate driving region and the light emitting device region can be partially overlapped in the third direction by the arrangement manner that the light emitting device region covers not only the pixel circuit region in the third direction but also at least part of the gate driving region is overlapped, so that the area of the gate driving region which is not overlapped with the light emitting device region in the third direction is relatively small, that is, the area occupied by the gate driving region which is not overlapped with the light emitting device region in the third direction in the plane parallel to the display surface is relatively small, and thus a display module with a narrow frame can be realized.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic position diagram of a pixel circuit region, a gate driving region and a light emitting device region in a display module according to an embodiment;

FIG. 2 is a schematic structural diagram of a display module according to an embodiment;

FIG. 3 is a schematic diagram of a pixel circuit array according to an embodiment;

fig. 4 is a schematic structural view of a light emitting device array according to an embodiment;

FIG. 5 is a schematic structural diagram of a display module without a first isolation structure;

FIG. 6 is a second schematic diagram illustrating a pixel circuit array according to an embodiment;

FIG. 7 is a second schematic structural diagram of a display module according to an embodiment;

FIG. 8 is a schematic diagram of a first repeating unit and a corresponding light emitting device of an embodiment;

FIG. 9 is a circuit diagram of a first pixel sub-circuit according to one embodiment;

FIG. 10 is a third schematic structural diagram of a display module according to an embodiment;

FIG. 11 is a schematic diagram of a top view of the locations of a first gate sub-circuit and a second gate sub-circuit according to an embodiment;

FIG. 12 is a schematic diagram of a cross-sectional position of a first gate sub-circuit and a second gate sub-circuit according to an embodiment;

FIG. 13 is a schematic cross-sectional diagram of a drive circuit of an LTPS structure according to an embodiment;

FIG. 14 is a schematic cross-sectional diagram of a driving circuit of an LTPO structure according to an embodiment;

FIG. 15 is a second circuit diagram of the first pixel sub-circuit according to one embodiment;

FIG. 16 is a fourth schematic view illustrating a structure of a display module according to an embodiment;

fig. 17 is a third schematic diagram illustrating a configuration of a pixel circuit array according to an embodiment;

FIG. 18 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment of FIG. 17;

FIG. 19 is a fourth schematic diagram illustrating a pixel circuit array according to an embodiment;

FIG. 20 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment of FIG. 19;

FIG. 21 is a fifth exemplary embodiment of a pixel array;

FIG. 22 is a schematic diagram illustrating a display module formed based on the pixel circuit array of the embodiment in FIG. 21;

FIG. 23 is a schematic diagram illustrating the positions of a light emitting device and a gate driving circuit in a display module according to an embodiment;

FIG. 24 is a partial schematic view of the connection of the light emitting device of the embodiment of FIG. 23 to a first pixel sub-circuit;

FIG. 25 is a schematic cross-sectional view illustrating a display module according to an embodiment;

FIG. 26 is a schematic top view of the position of a fan-out wire set according to an embodiment;

fig. 27 is a schematic positional view of a light emitting device array of an embodiment.

Element number description:

pixel circuit array: 100, respectively; a first sub-array: 110; the first pixel circuit: 111; a first gate electrode: 1101; a first source electrode: 1102; a first drain electrode: 1103; a source contact structure: 1104; a drain contact structure: 1105; anode: 1107; a second active layer: 1108; second gate insulating layer: 1109; a second gate: 1110; a light shielding layer: 1111; substrate layer: 1112; a first buffer layer: 1113; first gate insulating layer: 1114; interlayer insulating layer: 1115; a planarization layer: 1116; a first isolation structure: 101, a first electrode and a second electrode; the second pixel circuit: 112, a first electrode; a first repeating unit: 113; a second sub-array: 120 of a solvent; a third sub-array: 130, 130; the third pixel circuit: 131; a fourth sub-array: 140 of a solvent; the fourth pixel circuit: 141, a solvent; an anode reset unit: 1511; a gate reset unit: 1512; a data writing unit: 1513; a threshold compensation unit: 1514; a light emission control unit: 1515; an array of light emitting devices: 200; light-emitting repeating unit: 210; repeating the subunit: 2101; virtual quadrangle: 2102; a light emitting device: 201; a gate drive circuit: 300, respectively; a first drive unit: 310; a first gate sub-circuit: 311; a second gate sub-circuit: 312; a second drive unit: 320, a first step of mixing; gate line: 400, respectively; and (3) fanning out the wiring group: 500, a step of; virtual plane: 600.

Detailed Description

To facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application belong. The terminology used herein in the description of the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the embodiments of the present application, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only used for convenience in describing the embodiments of the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the embodiments of the present application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first direction may be referred to as a second direction, and similarly, a second direction may be referred to as a first direction, without departing from the scope of the present application. The first direction and the second direction are both directions, but they are not the same direction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. In the description of the present application, "a plurality" means at least one, e.g., one, two, etc., unless explicitly specified otherwise.

Fig. 1 is a schematic position diagram of a pixel circuit region a, a gate driving region B, and a light emitting device region C in a display module according to an embodiment of the present disclosure. The display device may be a smartphone, a tablet, a gaming device, an Augmented Reality (AR) device, a notebook, a desktop computing device, a wearable device, or the like. For convenience of understanding, the display device is exemplified as a mobile phone in the following. Referring to fig. 1, the display module includes a pixel circuit region a, a gate driving region B, and a light emitting device region C. The pixel circuit area a is provided with a pixel circuit array 100. The gate driving region B is provided with a gate driving circuit 300, the gate driving circuit 300 is electrically connected to the pixel circuit array 100, and the gate driving circuit 300 is configured to generate a light emitting control signal and output the light emitting control signal to the pixel circuit array 100. The light emitting device region C is provided with a light emitting device array 200, the light emitting device array 200 is connected to the pixel circuit array 100, and the pixel circuit array 100 drives the light emitting device array 200 to emit light under the control of a light emitting control signal.

The projection of the light emitting device region C on a virtual plane along a third direction covers the projection of the pixel circuit region a on the virtual plane along the third direction, the projection of the light emitting device region C on the virtual plane along the third direction is at least partially overlapped with the projection of the gate driving region B on the virtual plane along the third direction, the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction. It should be noted that the virtual plane 600 is not a feature actually existing in the display module, but is a reference plane introduced for convenience of describing features of the display module.

In this embodiment, the light emitting device region C is provided with a light emitting device array, and a plane where the light emitting device array is located can be understood as a display surface, the display surface is perpendicular to the third direction, and the non-light emitting gate driving region B and the light emitting device region C partially overlap in the third direction by the arrangement manner that the light emitting device region C not only covers the pixel circuit region a in the third direction but also overlaps at least part of the gate driving region B, so that the area of the gate driving region B that is not overlapped with the light emitting device region C in the third direction is relatively small, that is, the area occupied by the gate driving region B that is not overlapped with the light emitting device region C in the third direction in a plane parallel to the display surface is relatively small, and thus a display module with a narrow frame can be realized.

With continued reference to fig. 1, in one embodiment, the pixel circuit area a and the gate driving area B are disposed adjacent to each other in a first direction, and the first direction is perpendicular to the third direction. Based on the above manner of adjacent arrangement in the first direction, it can be understood that the pixel circuit area a and the gate driving area B are arranged on the same layer, so that the gate driving area B and the pixel circuit area a can be arranged closely, thereby saving space in the display module.

Fig. 2 is a schematic structural diagram of a display module according to an embodiment, and referring to fig. 2, the display module of the embodiment includes a pixel circuit array 100 and a light emitting device array 200. Specifically, fig. 3 is a schematic structural diagram of the pixel circuit array 100 according to an embodiment, and fig. 4 is a schematic structural diagram of the light emitting device array 200 according to an embodiment, and the pixel circuit array 100 and the light emitting device array 200 are stacked in a thickness direction to form a display module.

Referring to fig. 3, the pixel circuit array 100 includes a first sub-array 110, the first sub-array 110 includes a plurality of first pixel circuits 111 and a plurality of first isolation structures 101, and the first isolation structures 101 are located between two first pixel circuits 111 adjacent in a first direction. The first isolation structure 101 is partially disposed between two adjacent first pixel circuits 111 in the first direction, and the remaining portion is not disposed between two adjacent first pixel circuits 111 in the first direction, and may be specifically disposed as needed. It is to be understood that although in the embodiment of fig. 3, one first isolation structure 101 is provided every other first pixel circuit 111 in the first direction, i.e. the first isolation structures 101 are uniformly arranged in the first array 110, the first isolation structures 101 may also be non-uniformly arranged in the first array 110. For example, one first isolation structure 101 may be disposed every four first pixel circuits 111 in one region, and one first isolation structure 101 may be disposed every five first pixel circuits 111 in another region, which is not limited in this embodiment.

Referring to fig. 2 to 4 in combination, the light emitting device array 200 includes a plurality of light emitting devices, and the plurality of light emitting devices are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence. Specifically, the circular structure in the lower portion of each first pixel sub-circuit in fig. 3 is a node for connecting the first pixel sub-circuit to the light emitting device 201, and correspondingly, the circular structure in each light emitting device 201 in fig. 4 is an anode for connecting the first pixel sub-circuit. It is understood that the circular configuration in the embodiment of fig. 3 and 4 is only for illustrative purposes, and is not intended to limit the scope of the present application, and the position can be adjusted according to the design of the circuit trace.

With continued reference to fig. 4, in one embodiment, the light emitting device array 200 is divided into a plurality of light emitting repeating units 210, the plurality of light emitting repeating units 210 respectively correspond to the plurality of first pixel circuits 111 in a one-to-one manner, and each of the light emitting repeating units 210 respectively includes a plurality of light emitting devices 201. The light-emitting repeating unit 210 includes a plurality of repeating subunits 2101, and the light-emitting repeating unit 210 includes 4n red light-emitting devices, 8n green light-emitting devices, and 4n blue light-emitting devices, where n is an integer greater than or equal to 1. Wherein, two adjacent pixels can share red emitting device or blue emitting device to improve display module's resolution ratio, and restrain display module's various limit problem, and then promote display quality. It can be understood that the present embodiment does not specifically limit the arrangement manner among the red light emitting device, the green light emitting device, and the blue light emitting device, and all of the technical solutions that can improve the resolution of the display module described above belong to the protection scope of the present embodiment.

In one embodiment, with continued reference to fig. 4, each of the repeating subunits 2101 includes one of the red light-emitting devices, two of the green light-emitting devices, and one of the blue light-emitting devices separated from each other, wherein one of the green light-emitting devices and one of the red light-emitting devices in the repeating subunit 2101 each have a center located at two first vertices of a virtual quadrilateral 2102, which are located on a diagonal of the virtual quadrilateral 2102. Another one of the green light-emitting devices and one of the blue light-emitting devices in the repeated sub-unit 2101 respectively have centers located at two second vertices of a virtual quadrangle 2102, the two second vertices being located on the other diagonal of the virtual quadrangle 2102.

It should be noted that each Light Emitting device in the present embodiment may be, but is not limited to, an Organic Light-Emitting diode (OLED), a Quantum Dot Light Emitting diode (QLED), a Micro Light Emitting diode (Micro LED), and the like. In the embodiments of the present application, the light emitting device is exemplified as an organic light emitting diode. The light emitting devices can be organic light emitting diodes with different colors, such as red OLEDs, green OLEDs, blue OLEDs and the like, the driving circuit of each light emitting device can be the same, but the light emitting layer materials of the light emitting devices with different colors are different, so that the display with different colors is realized, and the display equipment realizes full-color display.

For example, if the display module needs to realize richer colors or a larger color gamut, a larger number of light emitting devices, for example, light emitting devices with four different colors, may be provided. In this embodiment, the display module includes three light emitting devices of different colors, which may be red (R), green (G), and blue (B), respectively. It is to be understood that the above quantities are for illustrative purposes only and are not intended to limit the scope of the present embodiments.

Fig. 5 is a schematic structural diagram of a display module without a first isolation structure, and referring to fig. 5, driving traces corresponding to two green light emitting devices are respectively shown in bold in the upper left corner and the lower right corner of fig. 5. Here, the light emitting device on the left side in fig. 5 may be understood as a light emitting device near the center of the display module, and the light emitting device on the right side in fig. 5 may be understood as a light emitting device near the frame of the display module. Obviously, the length difference between the two circuit traces is large, and the difference in performance of the light emitting device, such as response speed or light emitting brightness, can be caused, so that the display module has uneven display in the first direction. Furthermore, it is more critical that in fig. 5, the length variation of the drive traces is gradual, i.e. the closer to the bezel, the longer the length of the drive traces. Thus, there is no area in fig. 5 where the length of one drive trace is arranged in the same manner.

Referring to fig. 2, two first pixel sub-circuits filled in a grid shape are shown, and each first pixel sub-circuit is connected to a corresponding blue light emitting device through a driving wire. Referring to fig. 5, two pixel sub-circuits filled in a grid shape are also shown, each pixel sub-circuit is connected to a corresponding blue light emitting device through a driving wire, and the positional relationship of the two connected blue light emitting devices corresponds to the positional relationship of the two blue light emitting devices shown in the embodiment of fig. 2.

As can be seen by referring to the connection relationship of the driving traces in fig. 2 and fig. 5 in combination, the lengths of the driving traces connected between the two first pixel sub-circuits filled in a grid shape and the corresponding blue light emitting devices shown in fig. 2 are the same, while the lengths of the driving traces connected between the two first pixel sub-circuits filled in a grid shape and the corresponding blue light emitting devices shown in fig. 5 are different, specifically, the driving trace connected to the first pixel sub-circuit on the right side is longer than the driving trace connected to the first pixel sub-circuit on the left side. As described above, the length of the driving trace affects the response speed or the light emitting brightness of the light emitting device, so for the two first pixel sub-circuits in the embodiment of fig. 2, since the lengths of the driving traces connected to each other are the same, the response speed or the light emitting brightness of the two corresponding connected blue light emitting devices are very similar, that is, the uniformity of the display is better. However, for the two first pixel sub-circuits in fig. 5, because the lengths of the connected driving traces are different, there may be a certain difference in performance, such as response speed or light emitting brightness, of the two correspondingly connected blue light emitting devices, that is, the display uniformity is not as good as that in the embodiment of fig. 2.

It is understood that only a portion of the structure of the display module is shown in fig. 5, and the above difference becomes more obvious as the size of the display module and the number of pixels increase. For example, it is assumed that the size of the pixel circuit array 100 in the first direction is 99.5% of the size of the light emitting device array 200 in the first direction, that is, a width of 0.5% is reserved for setting other peripheral circuits. Then, the light emitting device located at the center of the light emitting device array 200 is the shortest distance from its corresponding driving circuit, and the length of the driving trace is understood to be equal to about 0cm. For the light emitting device located at the outermost side of the light emitting device array 200, the corresponding driving circuit is located at the outermost side of the pixel circuit array 100, and due to the inherent difference in size between the pixel circuit array 100 and the light emitting device array 200, the length of the driving trace of the light emitting device is approximately equal to 0.5% of the size of the light emitting device array 200 in the first direction, and if the size of the display module in the first direction is 6cm, the length of the driving trace is approximately equal to 0.3mm. Therefore, if the first isolation structure is not arranged, the uniformity of the routing length needs to be greatly sacrificed when the display device with the narrow frame is realized.

In this embodiment, by adding the first isolation structure, and the relative positions of the plurality of first isolation structures and the plurality of first pixel circuits, the length relationship of the driving wiring can be effectively adjusted, that is, the lengths of the driving wirings corresponding to the plurality of light emitting devices with the same color are close, so that the excessive length difference between the driving wirings corresponding to the light emitting devices with the same color is avoided, the response speed or the luminance of the light emitting devices is further influenced, and the display uniformity of the display module is improved.

As shown in fig. 2, a first isolation structure 101 is disposed between every two adjacent first pixel circuits 111, so that the first pixel circuits 111 are more uniformly arranged. Meanwhile, the length of the driving traces in each first pixel circuit 111 can be set in the same manner, so that the uniformity of the length of the driving traces is further improved. In other embodiments, the first isolation structure may be only disposed between a part of two adjacent first pixel circuits, and the first isolation structure is not disposed between the remaining part of two adjacent first pixel circuits, which is not limited in this embodiment.

Fig. 6 is a second schematic structural diagram of the pixel circuit array 100 according to the embodiment, and fig. 7 is a schematic structural diagram of a display module obtained based on the pixel circuit array 100 according to the embodiment of fig. 6 and the light emitting device array 200 according to the embodiment of fig. 3. Referring to fig. 3 and fig. 6 in combination, in the present embodiment, the first isolation structure may be the second pixel circuit 112, that is, the first sub-array 110 includes a plurality of first pixel circuits 111 and a plurality of second pixel circuits 112, of which two first pixel circuits 111 and one second pixel circuit 112 are shown in the embodiment of fig. 6. One second pixel circuit 112 is arranged between any two adjacent first pixel circuits 111 in a first direction, and the first direction is perpendicular to the thickness direction of the display module, that is, the first pixel circuits 111 and the second pixel circuits 112 are arranged at intervals in the first direction. For example, the first direction may be a width direction of the display module.

Alternatively, the plurality of first pixel sub-circuits in each first pixel circuit 111 may be arranged in an array, for example, in an array of 4 rows × 4 columns as shown in the embodiment of fig. 6. It should be noted that the number and arrangement of the first pixel sub-circuits of the first pixel circuit 111 in fig. 6 are only used for exemplary illustration, and are not used to limit the protection scope of the present embodiment. The first isolation sub-structure may be a second pixel sub-circuit, and a plurality of the second pixel sub-circuits are not connected to the light emitting device, that is, the second pixel circuit 112 may include a plurality of second pixel sub-circuits. The plurality of second pixel sub-circuits may be arranged along the second direction, or may be arranged in an array. Further, the size of the first pixel sub-circuit may be the same as the size of the second pixel sub-circuit, and the structure of the second pixel sub-circuit may be the same as the structure of the first pixel sub-circuit, so as to reduce the design difficulty of the pixel circuit array 100, and also reduce the difference influence of various optical effects on the size structure in the exposure preparation process, thereby improving the preparation yield of the pixel circuit array 100.

The second pixel sub-circuit may be understood as a dummy pixel sub-circuit (dummy pixel), i.e. as shown in fig. 7, the second pixel sub-circuit is not connected to the light emitting device, but is only used to optimize the size and arrangement of the pixel circuit array. Specifically, in the present embodiment, the size of the light emitting device array 200 in the first direction is larger than the size of the pixel circuit array 100 in the first direction. By relatively reducing the size of the pixel circuit array 100 in the first direction, a larger space can be provided for arranging other peripheral circuits, that is, the other peripheral circuits and the pixel circuit array 100 are arranged in the same layer, and the light emitting device array 200 is partially arranged on the other peripheral circuits, so that the width of the left frame and the right frame of the display module is narrowed by moving the positions of the other peripheral circuits on the basis of not reducing the light emitting area of the display module. Meanwhile, after each first pixel sub-circuit is reduced, the first pixel sub-circuit still needs to be made to correspond to the position of the corresponding light-emitting device, so as to avoid that the response speed or the light-emitting brightness of the light-emitting device is affected by too long driving wiring between the first pixel sub-circuit and the corresponding light-emitting device. Therefore, the second pixel sub-circuit can fill the gap between the first pixel sub-circuits caused by the reduction of the size, so that the purpose of corresponding positions is realized, the arrangement uniformity of the first pixel sub-circuits is improved, and the display uniformity of the display module is improved. Meanwhile, by arranging a second pixel sub-circuit (dummy pixel) which is the same as the first pixel sub-circuit, the structure, size and distance of each pixel sub-circuit in the pixel circuit array 100 can be ensured to be consistent, and the problem of screen Mura caused by inconsistent circuit wiring density is avoided. Moreover, the consistent structure of the pixel sub-circuits is also beneficial to the stability of the process, the electrical consistency of the thin film transistors is ensured, and the uniformity of display is ensured.

Wherein the first pixel circuit 111 may be aligned with the second pixel circuit 112 in the second direction. Specifically, the first pixel circuit 111 may have a first side edge and a third side edge extending in the second direction, the first side edge may also be understood as a left edge, and the third side edge may also be understood as a right edge. The first pixel circuit 111 may also have a second side edge extending in the first direction, which may also be understood as an upper edge, and a fourth side edge, which may also be understood as a lower edge. One side edge of the second pixel circuit 112 is aligned with the second side edge of the first pixel circuit 111 in the second direction, thereby simplifying the design of the pixel circuit array 100.

Fig. 8 is a schematic structural diagram of a first repeating unit 113 and a corresponding light emitting device according to an embodiment, and referring to fig. 8, in one embodiment, a first repeating unit 113 is defined by one of the first pixel circuits 111 and one of the second pixel circuits 112 adjacent to each other. In addition, in the present embodiment, the first pixel circuit 111 on the left side and the second pixel circuit 112 on the right side are divided to form the first repeating unit 113, for example, but in other embodiments, the first pixel circuit 111 on the right side and the second pixel circuit 112 on the left side may be divided, for example.

Referring to fig. 4 and 8 in combination, the difference between the size of the light-emitting repeating unit 210 in the first direction and the size of the first repeating unit 113 in the first direction is within a third preset range, that is, it can be understood that the size of the light-emitting repeating unit 210 in the first direction is similar to the size of the first repeating unit 113 in the first direction. The third preset range may be, for example, 0um to 5um. In this embodiment, by setting the size relationship between the light-emitting repeating unit 210 and the first repeating unit 113, the correspondence between the positions of the light-emitting repeating unit 210 and the first repeating unit 113 can be achieved, so that a shorter driving trace is provided to improve the stability and reliability of the driving current.

Fig. 9 is one of circuit diagrams of a first pixel sub-circuit of an embodiment, and referring to fig. 9, in the present embodiment, the first pixel sub-circuit includes a driving transistor T1, an anode reset unit 1511, a gate reset unit 1512, a data write unit 1513, a threshold compensation unit 1514, and a light emission control unit 1515.

Specifically, the driving transistor T1 is used to generate a driving current. The gate of the driving transistor T1 is connected to the gate resetting unit 1512, the first pole of the driving transistor T1 is used for receiving the Data signal Data, and the second pole of the driving transistor T1 can output the driving current correspondingly. The current value of the driving current is determined by the Data signal Data and directly influences the light-emitting brightness of the light-emitting device.

The control terminal of the anode reset unit 1511 is configured to receive the second Scan signal Scan (n), the input terminal of the anode reset unit 1511 is configured to receive the reset voltage signal Vinit, and the output terminal of the anode reset unit 1511 is connected to the anode of the light emitting device.

The anode reset unit 1511 is configured to receive a reset voltage Vinit through the input terminal after the gate of the driving transistor T1 is reset, and pull down the anode of the light emitting device connected thereto to the reset voltage Vinit, so as to reset the anode of the light emitting device. Here, the reset voltage Vinit may be understood as an anode initial charging voltage of the light emitting device. By resetting the anode of the light-emitting device, the flow of the driving current of the light-emitting device, which is used for driving the light-emitting device, to the anode of the light-emitting device can be changed so as to drive the light-emitting device to emit light, and meanwhile, the driving current cannot be influenced, so that the reliability of the light-emitting brightness of the light-emitting device is ensured.

The control terminal of the gate reset unit 1512 is connected to the gate control terminal, and is configured to receive a first Scan signal Scan (n-1); the input end of the gate reset unit 1512 is connected to the second reset end, and is configured to receive a reset voltage Vinit; the output terminal of the gate reset unit 1512 is connected to the gate of the driving transistor T1. Specifically, the gate reset unit 1512 may pull down the gate voltage of the driving transistor T1 to the reset voltage Vinit according to the first Scan signal Scan (n-1) received by the control terminal, so as to reset the gate of the driving transistor T1.

The data writing unit 1513 includes a data writing transistor T2, a gate of the data writing transistor T2 is connected to the second scanning signal line Scan (n), a first pole of the data writing transistor T2 is connected to the data signal line, a second pole of the data writing transistor T2 is connected to the first pole of the driving transistor T1, and the data writing transistor T2 is configured to control on/off of a signal transmission path between the second scanning signal line and the first pole of the driving transistor T1 according to the second scanning signal Scan (n). Specifically, taking the Data writing transistor T2 as a P-type transistor as an example, when the second Scan signal Scan (n) is at a low level, the Data writing transistor T2 is turned on and transmits the Data signal Data to the first pole of the driving transistor T1; when the second Scan signal Scan (n) is at a low level, the data writing transistor T2 is turned off. It is understood that the data writing unit 1513 is not limited to the data writing transistor T2 of the present embodiment, and may be other circuit structures capable of controlling a signal according to an enable and implementing a signal transmission function.

The threshold compensation unit 1514 is respectively connected to the gate and the second pole of the driving transistor T1, and is configured to control the connection and disconnection of a signal transmission path between the gate and the second pole of the driving transistor T1 according to a second Scan signal Scan (n). Specifically, by providing the threshold compensation unit 1514, the threshold voltage of the driving transistor T1 can be compensated, thereby preventing the threshold voltage of the driving transistor T1 from affecting the luminance of the light emitting device.

The threshold compensation unit 1514 includes a threshold compensation transistor T3 and a storage capacitor C1. The storage capacitor C1 is connected to the second power voltage terminal VDD and the gate of the driving transistor T1, respectively. The gate of the threshold compensation transistor T3 is connected to the first scan signal line, the first pole of the threshold compensation transistor T3 is connected to the second pole of the driving transistor T1, and the second pole of the threshold compensation transistor T3 is connected to the gate of the driving transistor T1. The threshold compensation transistor T3 is used to control the on/off of the signal transmission path between the gate and the second pole of the driving transistor T1 according to the second Scan signal Scan (n). Specifically, taking the threshold compensation transistor T3 as a P-type transistor as an example, when the second Scan signal Scan (n) is at a low level, threshold compensation is performed and the storage capacitor C1 is charged, so that the compensation result is stored in the storage capacitor C1.

Alternatively, the threshold compensation transistor T3 may be a double gate transistor. In this embodiment, the threshold compensation transistor T3 of the double-gate transistor structure is adopted, so that the reliability of threshold compensation can be effectively improved, thereby improving the display quality of the display device. It is understood that other transistors in the first pixel sub-circuit may also be double-gate transistors to further improve the display quality.

The light emission control unit 1515 includes a first control transistor T5 and a second control transistor T6. The gate of the first control transistor T5 is configured to receive a light emission control signal, the first pole of the first control transistor T5 is connected to the second power voltage terminal, the second pole of the first control transistor T5 is connected to the first pole of the driving transistor T1, and the first control transistor T5 is configured to control on/off of a signal transmission path between the second power voltage terminal and the first pole of the driving transistor T1 according to the light emission control signal EM. The gate of the second control transistor T6 is configured to receive the emission control signal EM, the first pole of the second control transistor T6 is connected to the second pole of the driving transistor T1, the anode of the second pole of the second control transistor T6 is connected to the light emitting device, and the second control transistor T6 is configured to control on/off of a signal transmission path between the second pole of the driving transistor T1 and the anode of the light emitting device according to the emission control signal EM. Illustratively, taking the first and second control transistors T5 and T6 as P-type transistors as an example, when the emission control signal EM is at a low level, the first and second control transistors T5 and T6 are turned on, the voltage of the first pole of the driving transistor T1 is pulled up to the second power voltage VDD, the difference in gate-to-source voltages of the first driving transistor T1 is varied to generate a driving current and output the driving current to the light emitting device, thereby controlling the light emitting device to emit light.

Note that the transistors in this embodiment are not limited to the P-type transistors in the foregoing embodiments, and may be N-type transistors or the like. The types of the transistors are different, and the corresponding driving modes can be adjusted adaptively. In addition, the first pixel sub-circuit of the present embodiment is not limited to the 7T1C first pixel sub-circuit in the foregoing embodiments, that is, the first pixel sub-circuit may have other numbers of transistors, so that a lightweight display device is implemented by a smaller number of transistors, or a more flexible display function is implemented by a larger number of transistors, for example, other types of driving circuits such as 3T1C, 6T1C, and 6T2C may be used.

Fig. 10 is a third schematic structural diagram of the display module according to the embodiment, and in order to simplify the drawing, the driving traces between the light emitting devices and the first pixel sub-circuits are not shown in fig. 10. Referring to fig. 10, the gate driving circuit 300 is respectively connected to each of the first pixel sub-circuits, and the gate driving circuit 300 is configured to drive the light emitting device corresponding to each of the first pixel sub-circuits to emit light. The Gate driving circuit 300 may be a Gate On Array (GOA) circuit, and in this embodiment, the size of the frame may be further reduced by disposing the Gate driving circuit 300 on the Array substrate.

With continued reference to fig. 10, in one embodiment, the gate driving circuit 300 includes a first driving unit 310 and a second driving unit 320. The first driving unit 310 is connected to the first pixel sub-circuit, and the first driving unit 310 is configured to generate a Scan control signal, where the Scan control signal is used to control the first pixel sub-circuit to perform gate reset, anode reset, and data write, respectively, that is, the Scan control signal includes a first Scan signal Scan (n-1) and a second Scan signal Scan (n). The second driving unit 320 is connected to the first pixel sub-circuit, and the second driving unit 320 is configured to generate a light-emitting control signal EM, where the light-emitting control signal EM is used to control on/off of an output path of a driving current, and the output path is a path between the first pixel sub-circuit and the corresponding light-emitting device.

Fig. 11 is a schematic top view illustrating positions of the first gate sub-circuit 311 and the second gate sub-circuit 312 according to an embodiment, referring to fig. 11, in this embodiment, the first direction is parallel to a row direction of the display module, and the display panel includes a display area AA and a non-display area NAA disposed around the display area AA. The display module further includes a plurality of gate lines 400 disposed in the pixel circuit region, each of the gate lines 400 is respectively connected to a plurality of first pixel sub-circuits (each of the plurality of rectangular structures arranged in an array in the figure may be understood as a first pixel sub-circuit) in the pixel circuit array 100, and the first driving unit 310 includes a first gate sub-circuit 311 and a second gate sub-circuit 312 disposed in the non-display region NAA. The first gate sub-circuit 311 is disposed on one side of the pixel circuit array 100 in the first direction, and the second gate sub-circuit 312 is disposed on the other side of the pixel circuit array 100 in the first direction. Two ends of each gate line 400 are respectively connected to the first gate sub-circuit 311 and the second gate sub-circuit 312. In the present embodiment, each gate line 400 receives the same signal from both ends, i.e., the driving manner of single-row and dual-drive is adopted, so that the voltage difference between any two points on the gate line 400 can be within the sixth preset range. Wherein, the sixth preset range may be, for example, 0mV to 0.02mV. It can be understood that as the resolution of the display module is increased, the number of loads required to be driven by each gate line 400 is increased. Therefore, if the gate line 400 is too long and the gate driving circuit 300 is disposed only at one end, the voltage at the other end is low, and even the driving transistor cannot be turned on effectively, thereby affecting the display quality of the display module. In this embodiment, the reliability of the voltage on the gate line 400 can be effectively improved by the above arrangement, so as to improve the uniformity of the display module.

Fig. 12 is a schematic cross-sectional position diagram of the first gate sub-circuit 311 and the second gate sub-circuit 312 according to an embodiment, and referring to fig. 12, in an embodiment, a projection of the first gate sub-circuit 311 on a virtual plane 600 along a third direction and a projection of the light emitting device array 200 on the virtual plane 600 along the third direction have a first overlapping area, and the virtual plane 600 is a plane perpendicular to the third direction. A projection of the second gate sub-circuit 312 onto the virtual plane 600 along the third direction has a second overlapping area with a projection of the light emitting device array 200 onto the virtual plane 600 along the third direction. Wherein the first overlapping area is equal to the second overlapping area. In this embodiment, the first gate sub-circuit 311 and the second gate sub-circuit 312 which are symmetrically arranged are adopted, so that the symmetry of the frame of the display module can be effectively improved, and the width of the frame on one side can be prevented from being too large.

In one embodiment, each of the first and second pixel sub-circuits includes a plurality of thin film transistors, and each of the thin film transistors in the first and second pixel sub-circuits is a Low Temperature Poly-silicon (LTPS) transistor. Specifically, fig. 13 is a schematic cross-sectional view of a driving circuit of an LTPS structure according to an embodiment, in which all thin film transistors are LTPS transistors, and a cross-sectional direction of fig. 13 is perpendicular to a display surface of a display module.

Referring to fig. 13, in the present embodiment, the base plate may include Polyimide (PI) substrates 1112 and first buffer layers 1113 alternately arranged in sequence, and in the embodiment shown in fig. 13, the base plate includes two Polyimide (PI) substrates 1112 and two first buffer layers 1113 alternately arranged in sequence. It is understood that the substrate may also include a greater number of Polyimide (PI) substrates 1112 and first buffer layers 1113. A first gate insulating layer 1114, an interlayer insulating layer 1115, and a planarization layer 1116 are also disposed on the substrate. In fig. 13, two of the above-described first pixel sub-circuits are also shown in the first gate insulating layer 1114, the interlayer insulating layer 1115, and the planarization layer 1116.

Specifically, the display module further includes a plurality of driving traces L, the plurality of first pixel sub-circuits are respectively connected to the plurality of light emitting devices in a one-to-one correspondence manner through the plurality of driving traces L, and each of the first pixel sub-circuits is respectively configured to output a driving signal to an anode 1107 of the connected light emitting device. For convenience of illustration, in the embodiments of the present application, the trace connected between the output terminal of the driving circuit and the anode 1107 of the light emitting device is defined as a driving trace L. The driving trace L may be a transparent metal line, such as an Indium Tin Oxide (ITO) metal line, an Aluminum Zinc Oxide (AZO) metal line, or the like.

The first pixel sub-circuit 110a includes a first gate 1101, a first source 1102, a first drain 1103, a source contact 1104 and a corresponding drain contact 1105, and the anode 1107 layer in the first light emitting device is electrically connected to the first source 1102 through the driving trace L. The first pixel sub-circuit 110b may also include a first gate 1101, a first source 1102, a first drain 1103, a source contact 1104 and a drain contact 1105, and the anode 1107 layer in the second light emitting device is also electrically connected to the corresponding first source 1102 through the driving trace L. Referring to fig. 13, since the positions of the light emitting devices 201 in the same first repeating unit 113 are different, and the positions of the first pixel sub-circuits corresponding to the light emitting devices 201 are also different, the driving traces L with different lengths need to be arranged to achieve accurate connection.

In one embodiment, the LTPS structure based driving circuit, with continued reference to fig. 8, the first repeating unit 113 may include a plurality of the first pixel sub-circuits arranged in a 4n row by 4n column array, and a plurality of the second pixel sub-circuits arranged in a 4n row by 1 column array, where n is a positive integer. In the embodiment of fig. 8, n =1, i.e., the first repeating unit 113 includes a plurality of the first pixel sub-circuits arranged in a 4 x 4 column array, and a plurality of the second pixel sub-circuits arranged in a 4 x 1 column array. Referring to fig. 8, if the number of the first pixel sub-circuits in the first repeating unit 113 is too large, the distance between the first pixel sub-circuit close to the second pixel circuit 112 and the corresponding light emitting device is too long, which results in that the length of a part of the driving wires L is too long, and further affects the display quality of the display module. Therefore, the arrangement of the present embodiment can reduce the difference in driving performance between different light emitting devices on the basis of arranging a larger number of first pixel sub-circuits having actual driving functions.

In one embodiment, the second pixel sub-circuit includes a plurality of thin film transistors, and at least one of the thin film transistors is a Low Temperature Polycrystalline Oxide (LTPO) transistor. For example, the Transistor T3 and the Transistor T4 which affect the leakage in fig. 9 may be replaced with a Thin Film Transistor (TFT), which has a better leakage suppression performance. That is, the transistor T3 and the transistor T4 in fig. 9 are replaced with LTPS structures, and other transistors are still maintained as LTPS structures, and the connection structure of the circuit is maintained, so that the purpose of controlling leakage current is achieved. Specifically, fig. 14 is a schematic cross-sectional view of an exemplary LTPO structure driving circuit, in which at least one thin film transistor is a LTPO transistor driving circuit, and a cross-sectional direction of fig. 14 is perpendicular to a display surface of a display module.

Referring to fig. 14, in the present embodiment, the substrate, the first source electrode 1102, the first drain electrode 1103 and the first gate electrode 1101 are disposed in the same manner as in the embodiment of fig. 13, and are not repeated herein. The light shielding layer 1111 and the first grid 1101 are arranged on the same layer, a second buffer layer 1113 is arranged between the interlayer insulating layer 1115 and the second active layer 1108, the drain contact structure 1105 is overlapped on a step structure of the second active layer 1108, the second active layer 1108 is provided with a second source 1102 and a second drain 1103, the shape of the second grid insulating layer 1109 is the same as that of the second grid 1110, the second active layer 1108, the second grid insulating layer 1109 and the second grid 1110 are sequentially overlapped, the second interlayer dielectric layer covers partial areas of the upper surfaces of the second grid insulating layer 1109, the second grid 1110 and the second active layer 1108, and an area which is not covered by the second interlayer dielectric layer in the upper surface of the second active layer 1108 is a step surface of the step structure overlapped with the first source 1102 and the first drain 1103 to be formed. In this embodiment, by using a driving circuit of an LTPO structure, the anode 1107 of the light emitting element can be initialized in the data holding stage, thereby improving the problems of screen flicker, smear, and the like at the time of low-frequency driving.

In one embodiment, the second pixel sub-circuits include emission control lines (not shown in fig. 14) for transmitting emission control signals EM, and two of the second pixel sub-circuits adjacently disposed in the first direction are symmetrically disposed about a virtual symmetrical plane (shown by a dotted line 1117 in fig. 14) which is a plane perpendicular to the first direction, and share the same emission control line. As can be seen from a comparison between fig. 13 and fig. 14, the film structure of the driving circuit of the LTPO structure is relatively complex. Therefore, by using the method of sharing the light-emitting control lines (i.e. sharing the thickened signal lines) shown in fig. 15, the total number of the light-emitting control lines can be reduced, thereby simplifying the wiring complexity of the display module and providing a display module with a smaller volume. It can be understood that the circuit structure shown in the embodiment of fig. 15 includes two first pixel sub-circuits, but the structure of each first pixel sub-circuit is the same as that in the embodiment of fig. 9, and the description thereof is omitted here.

Fig. 16 is a fourth schematic structural view of a display module according to an embodiment, and referring to fig. 16, the first repeating unit 113 includes a plurality of the first pixel sub-circuits arranged in an array of 4n rows × 8n columns, and the second pixel circuit 112 includes a plurality of the second pixel sub-circuits arranged in an array of 4n rows × 2m columns, where m and n are positive integers. As shown in fig. 16, m may be 1, n may be 1. In the present embodiment, two adjacent second pixel sub-circuits are symmetrically disposed about a virtual symmetry plane (as shown by the dotted line 1117 in fig. 14). It is understood that the number of rows of sub-pixel circuits in the first repeating unit 113 needs to be even to achieve the above symmetrical arrangement, so as to be compatible with the LTPO process.

It will be appreciated that in some embodiments, the first pixel sub-circuit may also employ a drive circuit of LTPS structure and the second pixel sub-circuit employs a drive circuit of LTPO structure to form a pixel circuit array. The specific structure of each driving circuit can refer to the foregoing embodiments, and details are not repeated here.

In one embodiment, a length difference between the driving traces connected to the plurality of first pixel sub-circuits located at corresponding positions in each of the first pixel circuits is within a fifth preset range. It is understood that, in order to achieve better display quality, the lengths of the driving traces connected to the first pixel sub-circuits at corresponding positions should be equal. That is, the fifth preset range should be 0um from a design point of view. However, since there is a certain process error in the manufacturing process, the fifth preset range may be allowed to be slightly increased, for example, 0um to 1um. For example, two first pixel sub-circuits in a dashed-line box in fig. 10 may be understood as the first pixel sub-circuits of the corresponding positions. If the light emitting devices at the corresponding positions are not lighted simultaneously, the display color may be non-uniform. Therefore, the light emitting devices at the corresponding positions need to be lit at the same timing to achieve the desired color and brightness of the display together. It is emphasized that the same time is not limited to the exact same time, and if the difference between the lighting times of the two light emitting devices at the corresponding positions is smaller than a preset threshold, the lighting at the same time can be understood, and the preset threshold can be 0.01ms, for example. The lighting time refers to the time when the light-emitting devices reach stable target brightness, and the display driving chip determines the target brightness of each light-emitting device according to the picture required to be displayed.

Fig. 17 is a third schematic structural diagram of the pixel circuit array 100 according to an embodiment, and referring to fig. 17, in one embodiment, the pixel circuit array 100 further includes a second sub-array 120. A second sub-array 120 is disposed adjacent to the first sub-array 110 in the first direction, and the second sub-array 120 includes a plurality of the first pixel circuits 111. Fig. 18 is a schematic structural diagram of a display module formed based on the pixel circuit array 100 of the embodiment of fig. 17, and referring to fig. 18, in this embodiment, by disposing the second sub-array 120 not including the second pixel sub-circuit in the area near the edge of the display module, a larger number of light emitting devices can be disposed correspondingly, so as to increase the overlapping area between the light emitting device array 200 and other peripheral circuits (e.g., the gate driving circuit 300). The overlap area refers to an overlap area in the third direction, i.e., an overlap area between a projection of the light emitting device array 200 on a virtual plane perpendicular to the third direction and a projection of other peripheral circuits on the virtual plane perpendicular to the third direction.

It can be understood that, when a user uses the display device, the requirement on the display uniformity of the middle area is greater than the requirement on the edge area, and therefore, the first sub-array 110 structure is adopted in the middle area and the second sub-array 120 structure is adopted in the edge area in the present embodiment, which can not only achieve the purpose of narrowing the display frame to a greater extent, but also reduce the influence on the user experience. Illustratively, when one layer of ITO traces is used, the left and right borders can strive for a space of 200um to 400um, so as to provide a display module with a narrower border. It should be noted that although the second sub-array 120 in the embodiment of fig. 17 only shows 8 columns of the first pixel sub-circuits, the second sub-array 120 may actually arrange more columns of the first pixel sub-circuits as needed to further optimize the narrow-bezel performance.

With continued reference to fig. 17 and 18, in one embodiment, one side edge of the second sub-array 120 is aligned with the first side edge of the first sub-array 110 in a second direction, which is perpendicular to the first direction and perpendicular to the thickness direction of the display module. It is understood that the definition of each side edge of the first sub-array 110 in this embodiment is the same as that of the first pixel circuit in the previous embodiment, and the description thereof is omitted here. In this embodiment, by the above method, the design difficulty of the pixel driving circuit can be reduced without affecting the display function.

Referring to fig. 19, in one embodiment, the pixel circuit array 100 further includes a third sub-array 130, wherein the third sub-array 130 can be understood to be relatively close to the center of the display module, while the first sub-array 110 is relatively close to the frame of the display module. Fig. 20 is a schematic structural diagram of a display module formed based on the pixel circuit array 100 in the embodiment of fig. 19, and referring to fig. 19 and 20, in this embodiment, the third sub-array 130 is disposed adjacent to the first sub-array 110 in the second direction, which is perpendicular to the first direction and perpendicular to the thickness direction of the display module. The third sub-array 130 includes a plurality of the first repeating units 113 and a plurality of second isolation structures located between two of the first repeating units 113 adjacent in the second direction. By adding the second isolation structure and the relative positions of the plurality of second isolation structures and the plurality of first repeating units 113, the length relationship of the driving wires can be effectively adjusted, that is, the lengths of the driving wires corresponding to the plurality of light emitting devices with the same color are similar, so that the problem that the length difference between the driving wires corresponding to the light emitting devices with the same color is too large, the response speed or the luminance of the light emitting devices is influenced, and the display uniformity of the display module is improved.

The second isolation structure may be a third pixel circuit 131, wherein the third pixel circuit 131 includes a plurality of third pixel sub-circuits, and the third pixel sub-circuits may have the same structure as the first pixel sub-circuits, and are not electrically connected to the light emitting devices. Through setting up the third pixel sub circuit the same with first pixel sub circuit, can guarantee that the structure and the size of each inside pixel sub circuit of pixel circuit array 100 are unanimous, avoid because the inconsistent problem of the screen Mura that arouses of circuit line density. Moreover, the dimensional structure of the pixel sub-circuits is consistent, which is beneficial to the stability of the process, ensures the electrical property consistency of the thin film transistors and ensures the uniformity of display. Still further, a plurality of the third pixel sub-circuits in the same third pixel circuit 131 may be arranged in the first direction.

Optionally, a second isolation structure is disposed between any two adjacent first repeating units 113 in the second direction. That is, one third pixel circuit 131 is provided between any two adjacent first repeating units 113 in the second direction. Wherein a size of the light emitting device array 200 in the second direction is larger than a size of the pixel circuit array 100 in the second direction. Through the arrangement mode, the first pixel sub-circuit and the third pixel sub-circuit can be arranged more regularly in the second direction, the distance among the pixel sub-circuits in the pixel circuit array 100 can be ensured to be consistent, and therefore the problem of screen mura of the display module caused by inconsistent circuit wiring density is further improved.

In one embodiment, one side edge of the third sub-array 130 is aligned with a second side edge of the first sub-array 110 in a first direction, the second side edge connects the first side edges, and a plurality of the third pixel sub-circuits in the third pixel circuit 131 are arranged in the first direction. The difference between the sum of the sizes of the first repeating unit 113 and the third pixel circuit 131 in the second direction and the size of the light emitting repeating unit in the second direction is within a fourth preset range. The fourth preset range may be, for example, 0um to 10um. Through the setting mode, the correspondence between the light-emitting device and the corresponding first pixel sub-circuit can be effectively improved, so that the driving wiring is prevented from being too long, and the display uniformity is improved.

Fig. 21 is a fifth structural schematic diagram of the pixel circuit array according to an embodiment, and referring to fig. 21, in the embodiment, the pixel circuit array 100 further includes a fourth sub-array 140. A fourth sub-array 140 is disposed adjacent to the third sub-array 130 in the first direction, and is disposed adjacent to the second sub-array 120 in the second direction, the fourth sub-array 140 includes a plurality of the first pixel circuits 111 and a plurality of third isolation structures 141, the third isolation structures include a plurality of the second isolation sub-structures, and the third isolation structures are located between two adjacent first pixel circuits in the second direction. Further, one third isolation structure is disposed between any two adjacent first pixel circuits 111 in the second direction in the fourth sub-array 140.

With continued reference to fig. 21, the third isolation structure may be a fourth pixel circuit 141, i.e., the fourth sub-array 140 may include a plurality of the first pixel circuits 111 and a plurality of fourth pixel circuits 141. The fourth pixel circuit 141 includes a plurality of the third pixel sub-circuits. Wherein a plurality of the third pixel sub-circuits in the fourth pixel circuit 141 may be arranged in the first direction.

Further, one fourth pixel circuit 141 is disposed in the fourth sub-array 140 between any two adjacent first pixel circuits 111 in the second direction, so as to improve the arrangement uniformity of the pixel sub-circuits. A third side edge of the fourth sub-array 140 is aligned in the second direction with the first side edge of the first sub-array 110 and a fourth side edge of the fourth sub-array 140 is aligned in the first direction with the second side edge of the first sub-array 110, the third side edge connecting the fourth side edges. Fig. 22 is a schematic structural diagram of a display module formed based on the pixel circuit array 100 of the embodiment of fig. 21, and referring to fig. 22, in this embodiment, by providing the fourth sub-array 140, a greater number of light emitting devices can be provided compared to the third sub-array 130, so as to increase the overlapping area of the light emitting device array 200 and other peripheral circuits (e.g., gate driving circuits) in the third direction.

Further, fig. 23 is a schematic diagram of positions of a light emitting device and a gate driving circuit in a display module according to an embodiment, fig. 24 is a partial schematic diagram of a connection relationship between the light emitting device and a first pixel sub-circuit in the embodiment of fig. 23, and referring to fig. 23 and fig. 24 in combination, in this embodiment, by providing a plurality of third pixel sub-circuits arranged along a first direction and a plurality of second pixel sub-circuits arranged along a second direction, spatial sharing of peripheral circuits such as the light emitting device and the gate driving circuit in the third direction can be achieved, so that an occupied area of the peripheral circuits in a plane parallel to a display surface can be reduced, and a display device with a narrow frame can be provided.

Fig. 25 is a schematic cross-sectional view of a display module according to an embodiment, in which a cross-sectional plane of the embodiment is parallel to the second direction and parallel to the third direction, and referring to fig. 25, in one embodiment, the display module further includes a fan-out region D, and the fan-out region D is provided with a fan-out wiring group 500. The fanout line group 500 and the pixel circuit array 100 are adjacently arranged in the second direction, and the projection of the fanout line group 500 on the virtual plane 600 along the third direction coincides with the projection of the light emitting device array 200 on the virtual plane 600 along the third direction, the third direction is the thickness direction of the display module, and the virtual plane 600 is a plane perpendicular to the third direction. Fig. 26 is a schematic top view illustrating positions of fan-out wiring groups according to an embodiment, and referring to fig. 26, in this embodiment, the display panel further includes a display driving unit located in the non-display area NAA, and the display driving unit is connected to the pixel circuit array 100 through the fan-out wiring area. The Display driving unit may be a Display Driver IC (DDIC). In this embodiment, the light emitting device array 200 and the fan-out routing group 500 are partially overlapped in the third direction, and when a layer of ITO is used for routing, a space of 200um to 400um can be obtained at the upper and lower frames, so as to provide a display module with a narrower frame.

Further, in one embodiment, a projection of the light emitting device array 200 in a third direction on a virtual plane completely covers a projection of the pixel circuit array 100 in the third direction on the virtual plane, the third direction is a thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction. Fig. 27 is a schematic positional diagram of the light emitting device array 200 according to an embodiment, referring to fig. 27, based on the above arrangement, the light emitting device array 200 is partially overlapped with the first gate sub-circuit 311 and the second gate sub-circuit 312 in the first direction, and partially overlapped with the fan-out routing group 500, so as to maximize a display area, and further provide a display module with a narrowest frame.

The present application also provides a display device, including: the display module is provided. In this embodiment, based on above-mentioned display module assembly, can narrow display device's frame to optimize display device's demonstration homogeneity, thereby improve display device's comprehensive display performance.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the patent of the embodiment of the application shall be subject to the appended claims.

Claims

1. A display module, comprising:

the pixel circuit area is provided with a pixel circuit array, the pixel circuit array comprises a first sub-array, the first sub-array comprises a plurality of first pixel circuits and a plurality of first isolation structures, the first isolation structures are positioned between two adjacent first pixel circuits in a first direction, the first direction is vertical to the thickness direction of the display module, and the first pixel circuits comprise a plurality of first pixel sub-circuits;

a light emitting device region, provided with a light emitting device array, connected to the pixel circuit array, the pixel circuit array driving the light emitting device array to emit light under the control of a light emission control signal, the light emitting device array including a plurality of light emitting devices correspondingly connected to the first pixel sub-circuits, the size of the light emitting device array in the first direction being larger than the size of the pixel circuit array in the first direction;

2. The display module as claimed in claim 1, wherein the pixel circuit region and the gate driving region are disposed adjacent to each other in the first direction.

3. The display module according to claim 1, wherein one first isolation structure is disposed between any two adjacent first pixel circuits in the first direction.

4. The display module of claim 1, wherein the first isolation structure is a second pixel circuit, the second pixel circuit comprises a plurality of second pixel sub-circuits, the second pixel sub-circuits have the same structure as the first pixel sub-circuits, and the second pixel sub-circuits are not electrically connected to the light emitting devices.

5. The display module according to claim 4, wherein the plurality of second pixel sub-circuits in the same second pixel circuit are arranged along a second direction, the second direction being perpendicular to the first direction and perpendicular to a thickness direction of the display module.

6. The display module of claim 1, wherein the pixel circuit array further comprises:

a second sub-array disposed adjacent to the first sub-array in the first direction, the second sub-array including a plurality of the first pixel circuits.

7. The display module of claim 6, wherein the gate driving circuit comprises:

the first driving unit is connected with the first pixel sub-circuit and used for generating scanning control signals, and the scanning control signals are used for controlling the first pixel sub-circuit to respectively perform grid electrode resetting, anode resetting and data writing;

and the second driving unit is connected with the first pixel sub-circuit and used for generating a light-emitting control signal, the light-emitting control signal is used for controlling the on-off of an output path of the driving current, and the output path is a path between the first pixel sub-circuit and the corresponding light-emitting device.

8. The display module of claim 7, further comprising a plurality of gate lines, each gate line being connected to a respective one of the plurality of first pixel sub-circuits, the first driving unit comprising:

the first grid sub-circuit is arranged on one side of the pixel circuit array in the first direction;

the second grid sub-circuit is arranged on the other side of the pixel circuit array in the first direction;

each gate line is respectively connected with the first gate sub-circuit and the second gate sub-circuit.

9. The display module according to claim 8, wherein a projection of the first gate sub-circuit on a virtual plane along the third direction has a first overlapping area with a projection of the light emitting device array on a virtual plane along the third direction;

a projection of the second gate sub-circuit on the virtual plane along the third direction has a second overlapping area with a projection of the light emitting device array on the virtual plane along the third direction;

wherein the first overlapping area is equal to the second overlapping area.

10. The display module of claim 1, wherein the pixel circuit array further comprises:

a third sub-array, disposed adjacent to the first sub-array in a second direction, the second direction being perpendicular to the first direction and perpendicular to the thickness direction of the display module, and defining a first repeating unit formed by one adjacent first pixel circuit and one adjacent first isolation structure, where the third sub-array includes a plurality of the first repeating units and a plurality of second isolation structures, and the second isolation structures are located between two adjacent first repeating units in the second direction;

wherein a size of the light emitting device array in the second direction is larger than a size of the pixel circuit array in the second direction.

11. The display module of claim 10, wherein one of the second isolation structures is disposed between any two adjacent first repeating units in the second direction in the third sub-array.

12. The display module of claim 10, wherein the second isolation structure is a third pixel circuit, the third pixel circuit comprises a plurality of third pixel sub-circuits, the third pixel sub-circuits have the same structure as the first pixel sub-circuits, and the third pixel sub-circuits are not electrically connected to the light emitting devices.

13. The display module of claim 12, wherein a plurality of the third pixel sub-circuits in the same third pixel circuit are arranged along the first direction.

14. The display module of claim 10, wherein the pixel circuit array further comprises:

and a fourth sub-array disposed adjacent to the third sub-array in the first direction, the fourth sub-array including a plurality of the first pixel circuits and a plurality of third isolation structures, each of the third isolation structures being located between two of the first pixel circuits adjacent in the second direction.

15. The display module of claim 14, wherein one of the third isolation structures is disposed between any two adjacent first pixel circuits in the second direction in the fourth sub-array.

16. The display module of claim 14, wherein the third isolation structure comprises a plurality of third pixel sub-circuits, the third pixel sub-circuits have the same structure as the first pixel sub-circuits, and the third pixel sub-circuits are not electrically connected to the light emitting devices.

17. The display module of claim 10, further comprising:

the pixel circuit array is connected with the grid driving circuit, the fan-out area is provided with a fan-out line group, the fan-out line group is connected with at least one of the pixel circuit array and the grid driving circuit, and the projection of the fan-out line group on a virtual plane along the third direction is overlapped with the projection part of the light-emitting device array on the virtual plane along the third direction.

18. The display module as claimed in claim 17, wherein the fan-out region and the pixel circuit region are disposed adjacent to each other in a second direction, the second direction being perpendicular to the first direction and perpendicular to the third direction.

19. The display module according to claim 10, wherein the light emitting device array is divided into a plurality of light emitting repeating units, the plurality of light emitting repeating units respectively correspond to the plurality of first pixel circuits one by one, and each of the light emitting repeating units respectively comprises a plurality of light emitting devices;

wherein a difference between a size of the light emitting repeating unit in the first direction and a size of the first repeating unit in the first direction is within a third preset range.

20. The display module according to claim 19, wherein the third predetermined range is 0um to 5um.

21. The display module of claim 19, wherein the difference between the sum of the dimensions of the first repeating unit and the second isolating structure in the second direction and the dimension of the light-emitting repeating unit in the second direction is within a fourth predetermined range.

22. The display module according to claim 21, wherein the fourth predetermined range is 0um to 10um.

23. The display module according to claim 4, wherein the first pixel sub-circuit comprises an emission control line for receiving an emission control signal, the first pixel sub-circuit comprises a plurality of thin film transistors, at least one of the plurality of thin film transistors is a low temperature poly-oxide transistor, two first pixel sub-circuits adjacently disposed in the first direction are symmetrically disposed about a virtual symmetry plane, and share the same emission control line, and the virtual symmetry plane is a plane perpendicular to the first direction.

24. The display module of claim 23, wherein a first pixel circuit and a second pixel circuit adjacent to each other are defined to form a first repeating unit, the second pixel sub-circuit comprises a plurality of thin film transistors, at least one of the thin film transistors in the second pixel sub-circuit is a low temperature poly-crystalline oxide transistor, the first repeating unit comprises a plurality of the first pixel sub-circuits arranged in a 4n row by 8n column array, the second pixel circuit comprises a plurality of the second pixel sub-circuits arranged in a 4n row by 2m column array, wherein m and n are positive integers, a row direction is parallel to the first direction, and a column direction is perpendicular to the first direction and perpendicular to a thickness direction of the display module.

25. The display module of claim 4, wherein a first repeating unit is defined by one of the first pixel circuits and one of the first isolation structures, the first pixel sub-circuit and the second pixel sub-circuit respectively include a plurality of thin film transistors, and each of the thin film transistors in the first pixel sub-circuit and the second pixel sub-circuit is a low temperature poly-crystal transistor, the first repeating unit includes a plurality of the first pixel sub-circuits arranged in a 4n row x 4n column array, and the second pixel circuit includes a plurality of the second pixel sub-circuits arranged in a 4n row x 1 column array, where n is a positive integer, a row direction is parallel to the first direction, and a column direction is perpendicular to the first direction and perpendicular to a thickness direction of the display module.

26. The display module according to claim 1, further comprising a plurality of driving traces, wherein the plurality of first pixel sub-circuits are respectively connected to the plurality of light emitting devices in a one-to-one correspondence manner via the plurality of driving traces, and each of the first pixel sub-circuits is respectively configured to output a driving signal to an anode of the connected light emitting device.

27. The display module according to claim 26, wherein a difference in length between the driving traces connected to the plurality of first pixel sub-circuits located at corresponding positions in each of the first pixel circuits is within a fifth predetermined range.

28. A display device, comprising: a display module according to any one of claims 1 to 27.