CN113535509A - Memory bank abnormity detection method and device and BMC - Google Patents
Memory bank abnormity detection method and device and BMC Download PDFInfo
- Publication number
- CN113535509A CN113535509A CN202110651172.5A CN202110651172A CN113535509A CN 113535509 A CN113535509 A CN 113535509A CN 202110651172 A CN202110651172 A CN 202110651172A CN 113535509 A CN113535509 A CN 113535509A
- Authority
- CN
- China
- Prior art keywords
- memory bank
- bmc
- bios
- information
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000005856 abnormality Effects 0.000 claims description 23
- 238000004590 computer program Methods 0.000 claims description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 13
- 238000004883 computer application Methods 0.000 abstract description 2
- 230000000007 visual effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The application is applicable to the technical field of computer application, and provides a memory bank abnormity detection method and device and a BMC. The method comprises the following steps: the BIOS acquires memory information; the BIOS sends the memory bank information to the BMC through serial port redirection; and the BMC analyzes the memory bank information to obtain the memory bank abnormity detection result. The memory bank information acquired by the BIOS is sent to the BMC through the BIOS serial port redirection, and the BMC analyzes the memory bank information to obtain the abnormal condition of the memory bank. The method solves the problem that the Feiteng platform cannot obtain the memory bank information through the CPU because no ME exists, and is safe, reliable, convenient and visual.
Description
Technical Field
The application belongs to the technical field of computer application, and particularly relates to a memory bank anomaly detection method and device and a BMC.
Background
The Feiteng platform is a general name of a platform applying series products such as a domestic Feiteng server CPU, a domestic Feiteng desktop CPU, a domestic Feiteng embedded CPU and the like. The Feiteng CPU product has the characteristics of complete pedigree, high performance, perfect ecology, high degree of autonomy and the like, and provides a core computing power support for various types of equipment from a terminal to a cloud.
The popularization of high-density data centers, the change of IT architectures and the improvement of computing power requirements by cloud computing promote the continuous expansion of the server market. The stability of the server and the quick and accurate positioning of the server fault are always pursued by the server.
For a platform without an ME (Management Engine), such as a flight platform, the relevant information of the memory bank cannot be acquired through the CPU, so that the failure of the memory bank is unknown, and the memory bank with a specific problem cannot be located.
Disclosure of Invention
The embodiment of the application provides a memory bank abnormity detection method and device and a BMC (baseboard management controller), which can solve the problem that a Feiteng platform cannot acquire a memory bank fault.
In a first aspect, an embodiment of the present application provides a method for detecting an abnormality of a memory bank, including:
the BIOS acquires memory information;
the BIOS redirects the memory bank information to the BMC through a serial port;
and the BMC analyzes the memory bank information to obtain a memory bank abnormity detection result.
Wherein, the BIOS sends the memory information to BMC through serial port redirection, including:
redirecting the debugging port of the BIOS to the serial port of the BMC, wherein the BMC is connected with the BIOS through a CPLD;
and the BIOS sends the memory bank information from the debugging port to the serial port of the BMC through the CPLD.
Illustratively, the BMC analyzes the memory bank information to obtain a memory bank abnormality detection result, including:
the BMC analyzes the memory bank information to obtain the identification and the state of each memory bank;
and the BMC determines the memory bank with the abnormality according to the state and obtains the identifier of the memory bank with the abnormality.
Further, after the BMC analyzes the memory bank information and obtains a memory bank abnormality detection result, the method further includes:
the BMC sends out an error prompt instruction;
the error prompt instruction comprises the identifier of the memory bank with the exception and is used for indicating a prompt module corresponding to the memory bank with the exception to execute prompt operation.
In a second aspect, an embodiment of the present application provides a memory bank exception detection method, which is executed by a BMC, and includes:
receiving memory bank information from a BIOS, wherein the memory bank information is sent by redirecting the BIOS to the BMC through a serial port;
and analyzing the memory bank information to obtain a memory bank abnormity detection result.
The BMC analyzes the memory bank information to obtain a memory bank abnormity detection result, and the method comprises the following steps:
analyzing the memory bank information to obtain the identification and the state of each memory bank;
determining the memory bank with the abnormality according to the state, and obtaining the identifier of the memory bank with the abnormality;
after analyzing the memory bank information and obtaining the memory bank abnormity detection result, the method further comprises the following steps:
sending an error prompt instruction;
the error prompt instruction comprises the identifier of the memory bank with the exception and is used for indicating a prompt module corresponding to the memory bank with the exception to execute prompt operation.
In a third aspect, an embodiment of the present application provides a BMC, which includes a memory, a processor, and a computer program stored in the memory, and when the computer program is executed by the processor, the memory bank exception detection method according to the second aspect may be implemented.
In a fourth aspect, an embodiment of the present application provides a memory bank anomaly detection apparatus, including: BIOS and BMC;
the BIOS is used for acquiring the memory bank information and sending the memory bank information to the BMC through serial port redirection;
the BMC is used for analyzing the memory bank information to obtain a memory bank abnormity detection result.
Further, the memory bank abnormality detection apparatus further includes: a CPLD;
the CPLD connects the output port of the BIOS with the input port of the BMC, so that the BIOS sends the acquired memory bank information out of the debugging port of the BIOS and to the serial port of the BMC through the CPLD.
Further, the memory bank abnormality detection apparatus further includes: a plurality of prompting lamps and IO expansion chips;
the input port of the IO expansion chip is connected with the output port of the BMC, the output ports of the IO expansion chip are respectively connected with a plurality of prompt lamps, one prompt lamp is correspondingly arranged on each memory bank, and the IO expansion chip is used for expanding the output port of the BMC so that the prompt lamps can be turned on or turned off according to an error prompt instruction sent by the BMC.
The IO expansion chip is an I2C-GPIO chip.
It is understood that the beneficial effects of the second to fourth aspects can be seen from the description of the first aspect, and are not described herein again.
Compared with the prior art, the embodiment of the application has the advantages that: and sending the memory bank information acquired by the BIOS to the BMC through the BIOS serial port redirection, and analyzing the memory bank information by the BMC to obtain the abnormal condition of the memory bank. The method solves the problem that the Feiteng platform cannot obtain the memory bank information through the CPU because no ME exists, and is safe, reliable, convenient and visual.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a memory bank exception detection method according to an embodiment of the present application;
fig. 2 is a schematic flow diagram of a BMC end of a memory bank exception detection method according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a BMC provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a memory bank anomaly detection device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The memory bank anomaly detection method provided by the embodiment of the application can be applied to computer equipment, is suitable for computer equipment which cannot acquire memory bank information because of no ME, and is particularly suitable for computer equipment configured with a Feiteng platform. The embodiment of the present application does not set any limit to the specific type of the computer device.
Fig. 1 is a flowchart of a memory bank exception detection method according to an embodiment of the present application. By way of example and not limitation, as shown in fig. 1, the memory bank abnormality detection method of this embodiment includes the following steps:
s101: the BIOS acquires the memory bank information.
When the server is started, the BIOS (Basic Input Output System) detects hardware, and prints related information when a memory bank is detected, thereby acquiring corresponding memory information. The memory bank information includes the identification and status of each memory bank.
S102: the BIOS sends the memory bank information to the BMC through serial port redirection.
Specifically, the debug port of the BIOS is redirected to a serial port of a BMC (Baseboard Management Controller), and the BMC is connected to the BIOS through a CPLD. The data transmission path of the BIOS is redirected to the BMC, and a basis is provided for the BIOS to transmit the memory bank information to the BMC.
The BIOS sends the memory information from the debugging port to the serial port of the BMC through the CPLD.
S103: and the BMC analyzes the memory bank information to obtain the memory bank abnormity detection result.
Specifically, the BMC analyzes the memory bank information to obtain the identifier and the state of each memory bank.
And the BMC determines the memory bank with the abnormality according to the state and obtains the identifier of the memory bank with the abnormality. The abnormal memory bank and the corresponding identification are quickly identified through the state, and the position of the abnormal memory bank can be quickly and accurately positioned in the starting process.
In this embodiment, the BIOS serial port is redirected to the BMC serial port, so that the memory bank information is transmitted to the BMC, and then the BMC can analyze the memory bank information to obtain the memory bank abnormality detection result, thereby quickly and accurately positioning the position of the abnormal memory bank and obtaining a reliable abnormality detection result through the memory bank information.
In another embodiment, after the BMC analyzes the memory bank information and obtains the abnormal condition of the memory bank, the method further includes:
and the BMC sends out an error prompt instruction.
The error prompt instruction comprises an identifier of the memory bank with the exception, and is used for indicating a prompt module corresponding to the memory bank with the exception to execute prompt operation. The prompt module can safely, conveniently and visually display the position of the abnormal memory bank, and the abnormal memory bank can be quickly found.
Optionally, the prompt module is an LED lamp, and the prompt operation is to turn on the normally turned-off LED lamp or turn off the normally turned-on LED lamp.
In this embodiment, firmware development is performed on BMC based on OpenBMC. Correspondingly, fig. 2 is a schematic view of a BMC end flow of the memory bank exception detection method according to an embodiment of the present application. By way of example and not limitation, as shown in fig. 2, the following steps are performed at the BMC:
s201: memory bank information from the BIOS is received.
The memory bank information is sent by the BIOS through the serial port to the BMC through redirection.
S202: and analyzing the memory bank information to obtain the identification and the state of each memory bank.
S203: and determining the memory bank with the abnormality according to the state, and obtaining the identifier of the memory bank with the abnormality.
S204: and sending an error prompt instruction according to the identification of the memory bank with the exception.
The error prompt instruction comprises an identifier of the memory bank with the exception, and is used for indicating a prompt module corresponding to the memory bank with the exception to execute prompt operation.
Fig. 3 is a schematic structural diagram of a BMC according to an embodiment of the present disclosure, which is provided as an example and not a limitation. As shown in fig. 3, the BMC comprises a memory, a processor and a computer program stored in the memory, wherein the steps of the above-described method embodiments can be implemented when the computer program is executed by the processor.
Those skilled in the art will appreciate that FIG. 3 is merely an example of a BMC, and is not intended to be limiting of a BMC, and may include more or fewer components than shown, or some components in combination, or different components.
The processor referred to is typically an ARM processor or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like.
The memory is an internal storage unit of the BMC, and is used for storing an operating system, an application program, a BootLoader (BootLoader), data, other programs, and the like, for example, a program code of the computer program. The memory may also be used to temporarily store data that has been output or is to be output.
Fig. 4 is a schematic structural diagram of a memory bank anomaly detection device according to an embodiment of the present application. As shown in fig. 4, the apparatus includes: BIOS and BMC.
The BIOS is used for obtaining the memory bank information and sending the memory bank information to the BMC through serial port redirection. And the mutual information between the BIOS and the BMC is realized through serial port redirection.
Optionally, the debug serial port of the BIOS is redirected to the dev/ttyS1 port of the BMC. After obtaining the memory information, the BIOS transmits the memory information to a dev/ttyS1 port of the BMC through the debug serial port.
The BMC is used for analyzing the memory bank information to obtain a memory bank abnormity detection result.
Further, the device also comprises a CPLD.
The CPLD connects the output port of the BIOS with the input port of the BMC, so that the BIOS sends the acquired memory bank information out of the debugging port of the BIOS and to the serial port of the BMC through the CPLD. Information can be quickly transmitted between the BIOS and the BMC through the CPLD connection.
In addition, the device also comprises a plurality of prompting lamps and an IO expansion chip.
The input port of the IO expansion chip is connected with the output port of the BMC, the output ports of the IO expansion chip are respectively connected with the prompt lamps, each memory bank is correspondingly provided with one prompt lamp, and the IO expansion chip is used for expanding the output port of the BMC so that the prompt lamps can be turned on or turned off according to an error prompt instruction sent by the BMC.
Specifically, the prompt lamp can be arranged beside each memory bank, so that a user can check the detection result conveniently.
Optionally, the IO expansion chip is an I2C to GPIO chip. The prompting lamp is connected with the BMC through the I2C-GPIO port, when the BMC obtains an abnormal memory bank detection result, an error prompting instruction is sent through the I2C-GPIO chip, so that the prompting lamp corresponding to the abnormal memory bank is controlled according to the error prompting instruction, the prompting mode can be that the normally-off prompting lamp is turned on or the normally-on prompting lamp is turned off, the abnormal memory bank is safely and accurately positioned, the position of the abnormal memory bank can be conveniently and visually displayed, and the abnormal memory bank can be quickly found.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A memory bank anomaly detection method is characterized by comprising the following steps:
the BIOS acquires memory information;
the BIOS redirects the memory bank information to the BMC through a serial port;
and the BMC analyzes the memory bank information to obtain a memory bank abnormity detection result.
2. The memory bank exception detection method of claim 1, wherein the BIOS sending the memory bank information to the BMC via serial redirection, comprises:
redirecting the debugging port of the BIOS to the serial port of the BMC, wherein the BMC is connected with the BIOS through a CPLD;
and the BIOS sends the memory bank information from the debugging port to the serial port of the BMC through the CPLD.
3. The method as claimed in claim 1, wherein the BMC analyzes the bank information to obtain a bank anomaly detection result, which includes:
the BMC analyzes the memory bank information to obtain the identification and the state of each memory bank;
and the BMC determines the memory bank with the abnormality according to the state and obtains the identifier of the memory bank with the abnormality.
4. The method as claimed in claim 3, wherein after the BMC analyzes the bank information to obtain the bank anomaly detection result, the method further comprises:
the BMC sends out an error prompt instruction;
the error prompt instruction comprises the identifier of the memory bank with the exception and is used for indicating a prompt module corresponding to the memory bank with the exception to execute prompt operation.
5. A memory bank abnormity detection method is executed by a BMC and is characterized by comprising the following steps:
receiving memory bank information from a BIOS, wherein the memory bank information is sent by redirecting the BIOS to the BMC through a serial port;
and analyzing the memory bank information to obtain a memory bank abnormity detection result.
6. The method as claimed in claim 5, wherein the step of analyzing the memory bank information by the BMC to obtain a memory bank anomaly detection result comprises:
analyzing the memory bank information to obtain the identification and the state of each memory bank;
determining the memory bank with the abnormality according to the state, and obtaining the identifier of the memory bank with the abnormality;
after analyzing the memory bank information and obtaining the memory bank abnormity detection result, the method further comprises the following steps:
sending an error prompt instruction;
the error prompt instruction comprises the identifier of the memory bank with the exception and is used for indicating a prompt module corresponding to the memory bank with the exception to execute prompt operation.
7. A BMC comprising a memory, a processor and a computer program stored in the memory, wherein the computer program when executed by the processor implements the memory bank exception detection method of claim 5 or 6.
8. An apparatus for detecting memory bank abnormality, comprising: BIOS and BMC;
the BIOS is used for acquiring the memory bank information and sending the memory bank information to the BMC through serial port redirection;
the BMC is used for analyzing the memory bank information to obtain a memory bank abnormity detection result.
9. The memory bank abnormality detection apparatus according to claim 8, further comprising: a CPLD;
the CPLD connects the output port of the BIOS with the input port of the BMC, so that the BIOS sends the acquired memory bank information out of the debugging port of the BIOS and to the serial port of the BMC through the CPLD.
10. The memory bank abnormality detection apparatus according to claim 8, further comprising: a plurality of prompting lamps and IO expansion chips;
the input port of the IO expansion chip is connected with the output port of the BMC, the output ports of the IO expansion chip are respectively connected with a plurality of prompt lamps, one prompt lamp is correspondingly arranged on each memory bank, and the IO expansion chip is used for expanding the output port of the BMC so that the prompt lamps can be turned on or turned off according to an error prompt instruction sent by the BMC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110651172.5A CN113535509A (en) | 2021-06-10 | 2021-06-10 | Memory bank abnormity detection method and device and BMC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110651172.5A CN113535509A (en) | 2021-06-10 | 2021-06-10 | Memory bank abnormity detection method and device and BMC |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113535509A true CN113535509A (en) | 2021-10-22 |
Family
ID=78124823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110651172.5A Pending CN113535509A (en) | 2021-06-10 | 2021-06-10 | Memory bank abnormity detection method and device and BMC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113535509A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114816822A (en) * | 2022-05-07 | 2022-07-29 | 宝德计算机系统股份有限公司 | Server management method, device and system based on memory fault |
| WO2024082844A1 (en) * | 2022-10-18 | 2024-04-25 | 超聚变数字技术有限公司 | Fault detection apparatus and detection method for random access memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102799506A (en) * | 2012-06-29 | 2012-11-28 | 浪潮电子信息产业股份有限公司 | Method for positioning fault memory |
| CN103514068A (en) * | 2012-06-28 | 2014-01-15 | 北京百度网讯科技有限公司 | Method for automatically locating internal storage faults |
| WO2015039598A1 (en) * | 2013-09-17 | 2015-03-26 | 华为技术有限公司 | Fault locating method and device |
| WO2016106965A1 (en) * | 2014-12-31 | 2016-07-07 | 中兴通讯股份有限公司 | Server self-healing method and device |
| CN106055438A (en) * | 2016-05-27 | 2016-10-26 | 深圳市国鑫恒宇科技有限公司 | Method and system for rapidly locating anomaly of memory banks on mainboard |
| CN107992399A (en) * | 2017-12-12 | 2018-05-04 | 郑州云海信息技术有限公司 | A kind of memory bar condition detection method, apparatus and system |
-
2021
- 2021-06-10 CN CN202110651172.5A patent/CN113535509A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103514068A (en) * | 2012-06-28 | 2014-01-15 | 北京百度网讯科技有限公司 | Method for automatically locating internal storage faults |
| CN102799506A (en) * | 2012-06-29 | 2012-11-28 | 浪潮电子信息产业股份有限公司 | Method for positioning fault memory |
| WO2015039598A1 (en) * | 2013-09-17 | 2015-03-26 | 华为技术有限公司 | Fault locating method and device |
| WO2016106965A1 (en) * | 2014-12-31 | 2016-07-07 | 中兴通讯股份有限公司 | Server self-healing method and device |
| CN105808394A (en) * | 2014-12-31 | 2016-07-27 | 中兴通讯股份有限公司 | Server self-healing method and device |
| CN106055438A (en) * | 2016-05-27 | 2016-10-26 | 深圳市国鑫恒宇科技有限公司 | Method and system for rapidly locating anomaly of memory banks on mainboard |
| CN107992399A (en) * | 2017-12-12 | 2018-05-04 | 郑州云海信息技术有限公司 | A kind of memory bar condition detection method, apparatus and system |
Non-Patent Citations (1)
| Title |
|---|
| 熊兴中;: "SDRAM内存条控制器的设计与实现", 四川理工学院学报(自然科学版), no. 06, 30 December 2006 (2006-12-30) * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114816822A (en) * | 2022-05-07 | 2022-07-29 | 宝德计算机系统股份有限公司 | Server management method, device and system based on memory fault |
| WO2024082844A1 (en) * | 2022-10-18 | 2024-04-25 | 超聚变数字技术有限公司 | Fault detection apparatus and detection method for random access memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20240012706A1 (en) | Method, system and apparatus for fault positioning in starting process of server | |
| US20170031694A1 (en) | System and method for remote system configuration managment | |
| CN113535509A (en) | Memory bank abnormity detection method and device and BMC | |
| CN106055438A (en) | Method and system for rapidly locating anomaly of memory banks on mainboard | |
| US20110125941A1 (en) | Method and integrated circuit for providing enclosure management services utilizing multiple interfaces and protocols | |
| US20140129821A1 (en) | Test system and method for computer | |
| CN104021060A (en) | BMC serial port debugging system and method | |
| US10691562B2 (en) | Management node failover for high reliability systems | |
| CN111966390A (en) | Project construction method, system, terminal device and storage medium | |
| US7552371B2 (en) | Method and system for automatically diagnosing disability of computer peripheral devices | |
| US20150186317A1 (en) | Method and apparatus for detecting the initiator/target orientation of a smart bridge | |
| US8661293B2 (en) | Test architecture based on intelligent test sequence | |
| US8495353B2 (en) | Method and circuit for resetting register | |
| US11403243B2 (en) | Mainboard of a server and method of populating DIMM slots of a mainboard | |
| CN109710479B (en) | Processing method, first device and second device | |
| US20110010584A1 (en) | Diagnosis of and Response to Failure at Reset in a Data Processing System | |
| CN104182290A (en) | Debugging device and debugging method | |
| CN114924998B (en) | Memory information reading device and method, computing device motherboard, device and medium | |
| CN115712559A (en) | Method and device for testing hardware management software and electronic equipment | |
| CN115129378A (en) | Intelligent network card starting method and device capable of being actively adjusted, storage medium and equipment | |
| US10802901B2 (en) | Obtaining state information of threads of a device | |
| US11593121B1 (en) | Remotely disabling execution of firmware components | |
| CN113590203A (en) | Failure processing method and system for substrate management controller, storage medium and single chip microcomputer | |
| CN117971741B (en) | Interconnection link control method and device, storage medium and electronic equipment | |
| CN111198812B (en) | Application fault detection method, application fault detection device and terminal equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |