CN113517333A - MOSFET device with super junction structure and preparation method thereof - Google Patents
MOSFET device with super junction structure and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a MOSFET device with a super junction structure and a preparation method thereof, wherein the device comprises: the semiconductor layer comprises an N + + substrate region, an N type buffer layer and an N type epitaxial layer from bottom to top; a plurality of P type body regions which are horizontally arranged at intervals and are positioned on the upper surface of the N type epitaxial layer in the semiconductor layer; the N + injection regions are positioned on two sides of the upper surface of the P-type body region; the P + contact area is positioned in the center of the upper surface of the P-type body area; the grid is positioned on the upper surfaces of the two adjacent P-type body regions and is separated from the P-type body regions through a grid insulating film; a source electrode covering the gate electrode and spaced apart from the gate electrode by an interlayer insulating film; the drain electrode is positioned on the lower surface of the N + + substrate region in the semiconductor layer; and a trap energy level region formed by charged particles is also arranged in the semiconductor layer and is positioned at the lower part of the N-type epitaxial layer close to the N-type buffer layer. The MOSFET device provided by the invention has better soft recovery performance and higher switching speed.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a MOSFET device with a super junction structure and a preparation method thereof.
Background
Power semiconductor devices, also known as power electronic devices, are used in almost all electronic manufacturing industries, such as the computer field, the consumer electronics field, and the industrial control field. With the continuous improvement of the requirements of electronic products and energy efficiency, the performance requirements of power devices are higher and higher. The performance of the power device determines the technical level of the power system application, and meanwhile, the application puts higher requirements on the power device, and the development of a novel power device is promoted.
Conventional IGBTs (Insulated Gate Bipolar transistors) are widely used in power devices due to their superior properties such as high breakdown voltage and low turn-on voltage. However, since the IGBT has a collector junction, when the emitter is connected to a positive potential and the collector is connected to a negative potential, that is, reverse biased, the current cannot pass directly. Therefore, when the IGBT goes from conduction to forward blocking, a large surge voltage occurs to cause reverse breakdown. A parallel freewheeling diode is typically used to solve the above problem. However, the freewheeling diode limits the switching speed of the IGBT, and in recent years, in order to further increase the switching element speed, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device having a super junction structure is used instead of the IGBT.
However, the reverse recovery current of the existing MOSFET device changes rapidly and has poor softness, which causes the disadvantages of oscillation, electromagnetic interference, etc., and affects the switching speed and performance of the device.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a MOSFET device having a super junction structure and a method for manufacturing the same. The technical problem to be solved by the invention is realized by the following technical scheme:
a MOSFET device having a super junction structure, comprising:
the semiconductor layer comprises an N + + substrate region, an N type buffer layer and an N type epitaxial layer from bottom to top;
a plurality of P type body regions which are horizontally arranged at intervals and are positioned on the upper surface of the N type epitaxial layer in the semiconductor layer;
the N + injection regions are positioned on two sides of the upper surface of the P-type body region;
a P + contact region located at the center of the upper surface of the P-type body region;
a gate electrode located on the upper surfaces of two adjacent P-type body regions and separated from the P-type body regions by a gate insulating film;
a source electrode covering the gate electrode and spaced apart from the gate electrode by an interlayer insulating film;
the drain electrode is positioned on the lower surface of the N + + substrate region in the semiconductor layer;
and a trap energy level region formed by charged particles is also arranged in the semiconductor layer and is positioned at the position, close to the N-type buffer layer, of the lower part of the N-type epitaxial layer.
In one embodiment of the present invention, the N-type buffer layer includes an N + first buffer layer having a thickness of 9 μm to 15 μm and a doping concentration of 1 × 1016cm-3～3×1016cm-3。
In one embodiment of the present invention, the N-type buffer layer further includes an N-second buffer layer on the N + first buffer layer; wherein the thickness of the N-second buffer layer is 5-20 μm, and the doping concentration is 1 × 1015cm-3～3×1015cm-3。
In one embodiment of the invention, the charged particles comprise a substanceA seed, deuterium,3He + + and4He++。
in an embodiment of the invention, a plurality of first columnar layers are arranged below each P-type body region, the first columnar layers are connected with the P-type body regions and extend to the upper surface of the trap level region in the direction of the lower surface of the semiconductor layer, and a plurality of second columnar layers are formed on the N-type epitaxial layer.
In one embodiment of the present invention, the first cylindrical layer has a width of 2 μm to 6 μm and an impurity concentration of 3 × 1015cm-3～8×1015cm-3(ii) a The width of the second cylindrical layer is 2-10 μm, and the impurity concentration is 1 × 1015cm-3～3×1015cm-3。
In one embodiment of the present invention, the first cylindrical layer has a stripe-like structure.
In one embodiment of the present invention, the first cylindrical layer comprises an upper pillar and a lower pillar; the upper column is connected with the P-type body region, and the lower column is located below the upper column and is spaced from the upper column to form a spacing region.
In an embodiment of the present invention, the semiconductor device further includes a plurality of P-collector regions, wherein the P-collector regions are selectively disposed in the N + + substrate region and are spaced right below the P-type body regions.
Another embodiment of the present invention also provides a method for manufacturing a MOSFET device having a super junction structure, including the steps of:
epitaxially growing an N-type buffer layer on the N + + substrate;
epitaxially growing an N-type epitaxial layer on the N-type buffer layer for multiple times, and selectively injecting P-type impurities after each growth so as to form a semiconductor layer with a plurality of first cylindrical layers and second cylindrical layers;
performing P-type impurity implantation on the upper surface of the N-type epitaxy to form a P-type body region, and performing N-type impurity implantation and over-P-type impurity implantation on the P-type body region respectively to form an N + implantation region and a P + contact region;
preparing a grid electrode in an N + injection region above two adjacent P type body regions, and preparing a source electrode on the whole surface of the sample;
irradiating the back surface of the N + + substrate with charged ions to form a trap level region in the semiconductor layer;
selectively injecting P-type impurities into the lower surface of the N + + substrate to form a P-collector region;
and forming a drain electrode on the lower surface of the N + + substrate to finish the preparation of the device.
The invention has the beneficial effects that:
1. according to the MOSFET device with the super junction structure, the buffer layer is additionally arranged in the semiconductor layer to form a carrier storage pool in reverse recovery operation, so that the reduction rate of reverse recovery current of the device is reduced, and the soft recovery performance of the device is improved; meanwhile, a trap energy level is formed on the rear surface of the semiconductor layer, a large number of recombination centers exist in the trap energy level, and the service life of a current carrier is shortened through capturing and recombination, so that reverse recovery time and reverse recovery current are shortened, and the switching speed of a device is increased;
2. according to the invention, the plurality of P-type collectors are arranged on the substrate, so that the drain electrode is connected with the N + + contact region and the P-type collector region, the device has the characteristics of the MOSFET and the IGBT, and the performance of the device is greatly improved; meanwhile, the P-type collector region is arranged on the rear surface of the highly-doped N + first buffer layer and under the combined action of the P-type collector region and the buffer layer, the recovery efficiency of current carriers is greatly improved, and the soft recovery performance and the high-speed switching speed are further improved in reverse recovery operation.
3. The PIN diode is formed by separating the cylindrical layers, and the soft recovery degree can be adjusted by changing the number of the PIN diodes; meanwhile, the soft recovery effect is improved due to the increase of the number of PIN diodes;
4. the MOSFET device with the super junction structure provided by the invention has a thinner drift region, so that most of forward current flows to the drain collector region through the shortest conduction path, and the thinning of the drift region can reduce the on-resistance, thereby reducing the on-state loss.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic diagram of a MOSFET device having a super junction structure according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a MOSFET device having a super junction structure according to an embodiment of the present invention;
fig. 3a to 3i are schematic diagrams of a manufacturing process of a MOSFET device with a super junction structure according to an embodiment of the present invention;
description of reference numerals:
a 1-N + + substrate region; 2-N + first buffer; 3-N-second buffer; 4-trap level region; 5-N type epitaxial layer; a 6-P type body region; a 7-N + implant region; an 8-P + contact region; 9-a gate insulating film; 10-an interlayer insulating film; 11-a gate; 12-a source electrode; 13-a drain electrode; 14-one base unit; 15-a conductive channel; a 16-P type column middle separation region; 17-a second cylindrical zone; 18-column loading; 19-lower column; 20-a built-in diode; a 21-P collector region; 22-P type cylindrical layer.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. In the specification and drawings, in a layer or region with "N" or "P", electrons or holes represent majority carriers. In addition, the symbols "+" and "-" attached after N or P indicate that the impurity concentration is higher or lower than that of the layer to which no symbol is added. In the following description of the embodiments and the drawings thereof, the same components are denoted by the same reference numerals, and the description thereof will not be repeated. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention. Further, in the drawings described in the embodiments, the proportion and the size proportion are different from the actual ones for easy viewing or understanding.
Example one
Referring to fig. 1, fig. 1 is a schematic diagram of a MOSFET device with a super junction structure according to an embodiment of the present invention, which includes:
the semiconductor layer comprises an N + + substrate region 1, an N type buffer layer and an N type epitaxial layer 5 from bottom to top;
a plurality of P type body regions 6 which are horizontally arranged at intervals and are positioned on the upper surface of the N type epitaxial layer 5 in the semiconductor layer;
the N + injection regions 7 are positioned at two sides of the upper surface of the P-type body region 6;
a P + contact region 8 located at the center of the upper surface of the P-type body region 6;
a gate electrode 11 located on the upper surfaces of two adjacent P-type body regions 6 and separated from the P-type body regions 6 by a gate insulating film 9;
a source electrode 12 covering the gate electrode 11 and spaced apart from the gate electrode 11 by the interlayer insulating film 10;
a drain electrode 13 positioned on the lower surface of the N + + substrate region 1 in the semiconductor layer;
and a trap energy level region 4 formed by charged particles is arranged in the semiconductor layer and is positioned at the position, close to the N-type buffer layer, of the lower part of the N-type epitaxial layer 5.
In the present embodiment, the interfaces between the source 12 and the P + contact region 8, the N + implantation region 7, and the drain 13 and the N + + substrate region 1 are all ohmic contacts. Wherein the impurity concentration of the N + + substrate region 1 is 1.0 × 1018cm-3. The thickness of the N-type epitaxial layer 5 is 150-180 μm, and the doping concentration is 3 × 1015cm-3. Impurity concentration of P type body region 6 is 3X 1015cm-3The impurity concentration of the N + implantation region 7 is 1X 1018cm-3The impurity concentration of the P + contact region 8 is 3X 1017cm-3。
In this embodiment, the gate electrode 11 is made of polysilicon, and the gate insulating film 9 and the interlayer insulating film 10 are made of SiO2A material. The source electrode 12 is made of titanium, nickel, molybdenum or tungsten material, and the drain electrode 13 is made of titanium, nickel or silver material.
Further, the N-type buffer layer comprises an N + first buffer layer 2, the thickness of the N + first buffer layer 2 is 9-15 μm, and the doping concentration is strongDegree of 1X 1016cm-3～3×1016cm-3。
Further, the N-type buffer layer further includes an N-second buffer layer 3 on the N + first buffer layer 2; wherein the thickness of the N-second buffer layer 3 is 5-20 μm, and the doping concentration is 1 × 1015cm-3～3×1015cm-3。
In the present embodiment, the charged particles forming the trap level region 4 include, but are not limited to, protons, deuterium, and the like,3He + + and4he + +, and the like. Wherein the charged particle energy determines the trap level position. If the energy of the charged particles is too high in the irradiation process, the trap energy level region is far away from the rear surface of the semiconductor layer, if the energy is too low, the irradiation region of the charged particles is shortened, and the trap energy level region is close to the rear surface of the semiconductor layer.
In the embodiment, the buffer layer is added in the semiconductor layer to form a carrier storage pool in reverse recovery operation, so that the reduction rate of reverse recovery current of the device is reduced, and the soft recovery performance of the device is improved; meanwhile, a trap energy level is formed on the rear surface of the semiconductor layer, a large number of recombination centers exist in the trap energy level, the service life of a carrier is shortened through capturing and recombination, and therefore reverse recovery time and reverse recovery current are shortened, and the switching speed of a device is increased.
Further, a plurality of first cylindrical layers 22 are arranged below each P-type body region 6, the first cylindrical layers 22 are connected with the P-type body regions 6 and extend to the upper surface of the trap level region 4 towards the lower surface direction of the semiconductor layer, and meanwhile, a plurality of second cylindrical layers 17 are formed on the N-type epitaxial layer 5. Wherein the second columnar layer is staggered between the first columnar layers in the semiconductor layer, thereby realizing charge balance between the first columnar layer and the second columnar layer.
Specifically, the first cylindrical layer 22 has a stripe structure, and the width thereof is 2 μm to 6 μm; the width of the second columnar layer 17 is 2 μm to 10 μm.
In the present embodiment, the electric field concentration region of the device is located in the depth direction of the first columnar layer inside the semiconductor layer, and is not less than 10 μm away from the trap level region in the depth direction of the first columnar layer, which is mainly composed of the first columnar layer 22 and the second columnar layer17 is determined by the doping concentration. Therefore, in this embodiment, the impurity concentration of the first columnar layer 22 is preferably 3 × 1015cm-3～8×1015cm-3The impurity concentration of the second columnar layer 17 is 1X 1015cm-3～3×1015cm-3。
More specifically, the first cylindrical layer 22 includes an upper column 18 and a lower bet 19; an upper column 18 connects the P-type body regions 6 and a lower bet 19 is positioned below the upper column and spaced from the upper column 18 to form a spacer region 16.
That is, the first cylindrical layer 22 (i.e., P-type pillar) is continuous with the P-type body region 6, and a pair of the P-type cylindrical layer 22 and the N-type cylindrical layer 17 is a repeating unit, the P-type cylindrical layer1Is the length along the front surface of the N-type epitaxial layer of the repeating unit, P1Each P-type pillar layer 22 may be divided vertically at 5 to 20 μm with a separation region 16 composed of a part of the N-type epitaxial layer 5 interposed at a middle portion in a depth direction thereof. The P-type pillars 22 may include an upper pillar 18 and a lower pillar 19 separated by a separation region 16. This split pillar structure forms a built-in diode 20.
In the embodiment, the built-in PIN diode is formed by separating the cylindrical layers, and the soft recovery degree can be adjusted by changing the number of the PIN diodes; meanwhile, the number of PIN diodes is increased, so that the soft recovery effect is improved.
Furthermore, the device further comprises a plurality of P-collector regions 21, wherein the P-collector regions 21 are selectively arranged in the N + + substrate region 1 and are arranged at intervals under the P-type body regions 6.
Specifically, with continued reference to fig. 1, wherein the P-type body region 6 and the source and gate thereon form a basic unit 14 of a device, a plurality of basic units may form the device, and the P-collector regions 21 are spaced apart in the N + + substrate region 1 below the basic unit.
In the embodiment, the plurality of P-type collectors are arranged on the substrate, so that the drain electrode is connected with the N + + contact region and the P-type collector region, the device has the characteristics of an MOSFET and an IGBT, and the performance of the device is greatly improved; meanwhile, the P-type collector region is arranged on the rear surface of the highly-doped N + first buffer layer and under the combined action of the P-type collector region and the buffer layer, the recovery efficiency of current carriers is greatly improved, and the soft recovery performance and the high-speed switching speed are further improved in reverse recovery operation.
In summary, in the present embodiment, by providing the columnar layer inside the semiconductor layer, a trap level and an electric field concentrated portion are formed by the charged particles as a connection and trap level region between the body region and the epitaxial layer from the body region to the upper surface, and when the body channel is not formed, the electric field is in an off state, and the trap level regions are at different depth positions from each other in the depth direction of the first columnar layer. Partial area in the first buffer area is replaced by a collector area of the second conduction type, so that the device has the characteristics of both the MOSFET and the IGBT.
When the parasitic diode between the source and the drain of the semiconductor device is closed, the current carrier (electron) moves to the drain filled trap level in the semiconductor layer, so that the recombination time of the current carrier in the device is accelerated, the reverse recovery time is further shortened, and the pressure resistance can be improved. Further, by setting the electric field concentrating portion at a depth position different from the trap level region, the electric field applied to the vicinity of the trap level region can be relatively relaxed.
In addition, the MOSFET device with the super junction structure provided by this embodiment further has a thinner drift region, so that most of the forward current flows to the drain collector region through the shortest conduction path, and the thinning of the drift region reduces the on-resistance, thereby reducing the on-state loss.
Example two
On the basis of the first embodiment, this embodiment provides a method for manufacturing a MOSFET device with a super junction structure, please refer to fig. 2, where fig. 2 is a flowchart of a method for manufacturing a MOSFET device with a super junction structure according to an embodiment of the present invention, and specifically includes the following steps:
s1: epitaxially growing an N-type buffer layer on an N + + substrate;
s2: epitaxially growing an N-type epitaxial layer on the N-type buffer layer for multiple times, and selectively injecting P-type impurities after each growth to form a semiconductor layer with a plurality of first cylindrical layers and second cylindrical layers;
s3: performing P-type impurity injection on the upper surface of the N-type epitaxy to form a P-type body region, and performing N-type impurity injection and over-P-type impurity injection on the P-type body region respectively to form an N + injection region and a P + contact region;
s4: preparing a grid electrode in an N + injection region above two adjacent P type body regions, and preparing a source electrode on the whole surface of the sample;
s5: irradiating the rear surface of the N + + substrate with charged ions to form a trap level region in the semiconductor layer;
s6: selectively injecting P-type impurities into the lower surface of the N + + substrate to form a P-collector region;
s7: and forming a drain electrode on the lower surface of the N + + substrate to complete the preparation of the device.
The following describes in detail the process of the preparation method provided in this embodiment with reference to the accompanying drawings.
Referring to fig. 3a to 3i, fig. 3a to 3i are schematic diagrams illustrating a process for manufacturing a MOSFET device having a super junction structure according to an embodiment of the present invention, which specifically includes:
step 1: at a doping concentration of 1.0X 1018cm-3An N + first buffer layer 2 having an impurity concentration of 1.0 × 10 is epitaxially grown on the N + + substrate 116cm-3And a thickness of 15 μm, as shown in fig. 3 a.
Step 2: epitaxially growing an N-type second buffer layer 3 on the first buffer layer 2 under the conditions: 1 to 10. omega. cm, and a thickness of 5 to 20 μm, as shown in FIG. 3 b.
And step 3: an N-type epitaxial layer is epitaxially grown on the second buffer layer 3a plurality of times, and P-type impurities are selectively implanted after each growth to form a semiconductor layer having several first and second columnar layers 22 and 17.
Specifically, firstly, a plurality of N-type semiconductor layers are epitaxially laminated on the second buffer layer 3 for a plurality of times under the growth conditions of a single layer thickness of 2-10 μm and a bulk resistance of 1-10 Ω · cm, and P-type impurities are selectively implanted after each layer is grown. In this embodiment, B ions are selected as P-type impurity and implanted vertically at 50keV to form an impurity concentration of 3.0 × 1015cm-3As shown in fig. 3 c.
Then, annealing is carried out at the temperature of 1000-1200 ℃, and the diffusion of the P-type impurities in the column region in the multilayer N-type semiconductor is completed to form a P-column middle separation part 16, the P-type impurities below the middle separation region form a lower column 19, the P-type impurities above the middle separation region form an upper column 18, and the N-type middle separation region 16 is formed between the two. Wherein the P-column spacers 16 and the second columnar regions 17 constitute the N-type epitaxial layer 5, as shown in fig. 3 d.
And 4, step 4: p-type impurity implantation is performed on the upper surface of the N-type epitaxial layer 5 to form a P-type body region 6, and N-type impurity implantation and over-P-type impurity implantation are performed on the P-type body region 6, respectively, to form an N + implantation region 7 and a P + contact region 8, as shown in fig. 3 d.
Specifically, P-type impurities (B) are selectively implanted into the upper surface of the semiconductor layer at a relatively low energy (50keV) to form a P-type body region 6 having a doping concentration of 3.0 x 1015cm-3. Also, in each P type body region 6, N type impurity (P) is selectively implanted into a predetermined width of an annular region having an outer edge at an inclination angle of 7 degrees at 130keV, receding inward by a predetermined distance only with respect to the outer edge of the P type body region, and having a doping concentration of 1.0X 1017cm-3Forming N + source region 7, selectively implanting over-P type impurity (B) at relatively high energy (100keV) to form P type contact region 8 at the central part of the body region and with doping concentration of 3.0 × 1017cm-3
And 5: a gate electrode 11 is fabricated in the N + implant region 7 over two adjacent P-type body regions 6 while a source electrode 12 is fabricated over the entire sample surface, as shown in fig. 3 e.
First, a gate insulating film 9 is formed by thermally oxidizing the upper surface of the epitaxial layer to cover the upper surface of the semiconductor layer 5 and the P-type body region. Then, a gate electrode 11 is formed on the gate insulating film 9, the gate electrode being composed of a doped low-resistance polysilicon film, covering the entire upper surface and then selectively etching the polysilicon film by photolithography. The gate insulating film is also etched to have the same shape as the gate electrode. An interlayer insulating film 10 having a thickness of
Forming a contact hole by photolithography of the interlayer insulating filmA source electrode 12 is formed on the insulating film, an ohmic junction is formed by heat treatment through alloying, and a protective film formed on the front surface has an electrode opening to expose a part of the source electrode on the front surface of the protective film.
Step 6: the back surface of the N + + substrate is irradiated with charged ions to form trap level regions in the semiconductor layer, as shown in fig. 3 f.
Specifically, the back surface of the substrate layer is irradiated by charged particles, and then low-temperature heat treatment is carried out, wherein the charged particles have activity, if helium atoms are selected, the heat treatment temperature is 320-380 ℃ for 30-120 minutes, for example, 350 ℃ can be selected, and heat treatment is carried out for 60 minutes, so that the trap level 4 is formed.
And 7: p-type impurities are selectively implanted into the lower surface of the N + + substrate 1 to form a P-collector region 21, as shown in fig. 3g-3 h.
Specifically, a back surface substrate layer is selectively implanted B, BF2Ions and activated by laser heat treatment. The conductivity type of part of the N + contact region is changed to P type to form the collector region 21. In this process, the source electrode is not melted during the high temperature thermal anneal and most or all of the upper surface of the structure may be protected prior to the thermal anneal. Therefore, the front and rear surfaces of the epitaxial layer do not need to be turned several times, thereby improving the production efficiency.
And 8: a drain electrode 13 is formed on the lower surface of the N + + substrate 1 and alloyed by thermal annealing to form an ohmic contact as shown in fig. 3 i.
Thus, the preparation of the MOSFET device having the super junction structure is completed.
It is noted that, in the present embodiment, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Further, it should be noted that while the present embodiments provide examples of parameters including particular values, it should be appreciated that the parameters need not be exactly equal to the corresponding values, but rather approximate the corresponding values within acceptable error tolerances or design constraints.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A MOSFET device having a super junction structure, comprising:
the semiconductor layer comprises an N + + substrate region (1), an N type buffer layer and an N type epitaxial layer (5) from bottom to top;
a plurality of P type body regions (6) which are horizontally arranged at intervals and are positioned on the upper surface of the N type epitaxial layer (5) in the semiconductor layer;
the N + injection regions (7) are positioned on two sides of the upper surface of the P-type body region (6);
a P + contact region (8) located at the center of the upper surface of the P-type body region (6);
a gate (11) located on the upper surface of two adjacent P-type body regions (6) and separated from the P-type body regions (6) by a gate insulating film (9);
a source electrode (12) which covers the gate electrode (11) and is separated from the gate electrode (11) by an interlayer insulating film (10);
the drain electrode (13) is positioned on the lower surface of the N + + substrate region (1) in the semiconductor layer;
and a trap energy level region (4) formed by charged particles is further arranged in the semiconductor layer and is positioned at the position, close to the N-type buffer layer, of the lower part of the N-type epitaxial layer (5).
2. The MOSFET device of claim 1, wherein the N-type buffer layer comprises an N + first buffer layer (2), the N + first buffer layer (2) having a thickness of 9 μm to 15 μm and a doping concentration of 1 x 1016cm-3～3×1016cm-3。
3. The MOSFET device of claim 2,characterized in that the N-type buffer layer further comprises an N-second buffer layer (3) on the N + first buffer layer (2); wherein the thickness of the N-second buffer layer (3) is 5-20 μm, and the doping concentration is 1 × 1015cm-3～3×1015cm-3。
4. The MOSFET device of claim 1, wherein the charged particles comprise protons, deuterium,3He + + and4He++。
5. the MOSFET device according to claim 1, wherein a plurality of first columnar layers (22) are arranged below each P-type body region (6), the first columnar layers (22) are connected with the P-type body regions (6) and extend to the upper side of the trap level region (4) towards the lower surface of the semiconductor layer, and a plurality of second columnar layers (17) are formed on the N-type epitaxial layer (5).
6. The MOSFET device of claim 5, wherein the first cylindrical layer has a width of 2 μm to 6 μm and an impurity concentration of 3 x 1015cm-3～8×1015cm-3(ii) a The width of the second cylindrical layer is 2-10 μm, and the impurity concentration is 1 × 1015cm-3～3×1015cm-3。
7. The MOSFET device according to claim 5, wherein the first cylindrical layer (22) is a striped structure.
8. The MOSFET device of claim 5, wherein the first cylindrical layer (22) comprises an upper pillar (18) and a lower pillar (19); the upper column (18) is connected with the P-shaped body area (6), and the lower injection (19) is positioned below the upper column and has a certain interval with the upper column (18) to form an interval area (16).
9. The MOSFET device of claim 1, further comprising P-collector regions (21), wherein the P-collector regions (21) are selectively disposed in the N + + substrate region (1) and spaced directly below the P-type body regions (6).
10. A preparation method of a MOSFET device with a super junction structure is characterized by comprising the following steps:
epitaxially growing an N-type buffer layer on the N + + substrate;
epitaxially growing an N-type epitaxial layer on the N-type buffer layer for multiple times, and selectively injecting P-type impurities after each growth to form a semiconductor layer with a plurality of first cylindrical layers and second cylindrical layers;
performing P-type impurity injection on the upper surface of the N-type epitaxial layer to form a P-type body region, and performing N-type impurity injection and over-P-type impurity injection on the P-type body region respectively to form an N + injection region and a P + contact region;
preparing a grid electrode in an N + injection region above two adjacent P type body regions, and preparing a source electrode on the whole surface of the sample;
irradiating the back surface of the N + + substrate with charged ions to form a trap level region in the semiconductor layer;
selectively injecting P-type impurities into the lower surface of the N + + substrate to form a P-collector region;
and forming a drain electrode on the lower surface of the N + + substrate to finish the preparation of the device.
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