CN113517178A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Preparation method of semiconductor structure and semiconductor structure Download PDF

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Publication number
CN113517178A
CN113517178A CN202110774536.9A CN202110774536A CN113517178A CN 113517178 A CN113517178 A CN 113517178A CN 202110774536 A CN202110774536 A CN 202110774536A CN 113517178 A CN113517178 A CN 113517178A
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layer
dielectric layer
region
substrate
carbon layer
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CN113517178B (en
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刘俊杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The application relates to a preparation method of a semiconductor structure and the semiconductor structure, comprising the following steps: providing a substrate; forming an overlay mark on the substrate, wherein the overlay mark has a concave structure; and sequentially stacking a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the alignment mark, wherein the first carbon layer covers the recessed structure, and the second carbon layer has a flat upper surface. The preparation method of the semiconductor structure can prevent the measurement of the overlay mark from being influenced by measurement noise.

Description

Preparation method of semiconductor structure and semiconductor structure
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof.
Background
The measurement quality of overlay marks (OVL marks) has an important influence on the product yield, and in the actual production process, overlay marks are often influenced by some adverse factors, such as the photolithography rework process. How to ensure the quality of measurement of overlay markers under the influence of various adverse factors is a problem to be solved.
Content of application
In order to improve the measurement quality of the overlay mark, embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.
According to some embodiments, the present application provides a method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming an overlay mark on the substrate, wherein the overlay mark has a concave structure;
and sequentially stacking a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the alignment mark, wherein the first carbon layer covers the recessed structure, and the second carbon layer has a flat upper surface.
The preparation method of the semiconductor structure forms an alignment mark on the substrate, the alignment mark is provided with a concave structure, and a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer are sequentially stacked on the alignment mark. The second carbon layer has a flat upper surface, namely, the second carbon layer is not sunken any more, so that the anti-reflection layer above the second carbon layer can be uniformly deposited, the second carbon layer cannot be damaged in the process of carrying out rework treatment on the material on the upper layer of the anti-reflection layer, and the measurement of the overlay mark is prevented from being influenced by measurement noise.
In one embodiment, the method further comprises the following steps: and performing rework treatment on the photoresist pattern layer after the photoresist pattern layer is formed on the anti-reflection layer.
In one embodiment, the step of forming an overlay mark on the substrate comprises:
forming a first dielectric layer on the substrate, wherein the first dielectric layer comprises a first area and a second area;
forming a plurality of first trenches on the first region and the second region of the first dielectric layer;
filling a second dielectric layer in the first groove; the top of the second dielectric layer is flush with the top of the first dielectric layer;
forming a second trench between the first region and the second region, wherein a bottom of the second trench is located within the substrate.
In one embodiment, the method further comprises the following steps:
and forming a lining structure with an arc-shaped opening at the bottom of the second groove, wherein the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove, and the lining structure and the second groove form the recessed structure.
In one embodiment, the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises silicon dioxide.
In one embodiment, the material of the liner structure comprises tungsten.
In one embodiment, the thickness of the anti-reflection layer is less than the thickness of the second carbon layer.
According to some embodiments, another aspect of the present application provides a semiconductor structure comprising:
a substrate;
an overlay mark on the substrate, the overlay mark including a recessed structure;
a first carbon layer covering the recessed structure;
the hard mask layer, the second carbon layer and the antireflection layer are sequentially stacked on the first carbon layer, and the second carbon layer is provided with a flat upper surface.
The alignment mark in the semiconductor structure has a concave structure, and a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer are sequentially formed on the alignment mark in a stacking manner. The second carbon layer has a flat upper surface, namely, the second carbon layer is not sunken any more, so that the anti-reflection layer above the second carbon layer can be uniformly deposited, the second carbon layer cannot be damaged in the process of carrying out rework treatment on the material on the upper layer of the anti-reflection layer, and the measurement of the overlay mark is prevented from being influenced by measurement noise.
In one embodiment, the overlay mark further comprises:
a first dielectric layer having a plurality of first trenches, the first dielectric layer including a first region and a second region; each first groove is formed in the first area and the second area;
and the top of the second dielectric layer is flush with the top of the first dielectric layer.
In one embodiment, the recessed feature is located between the first region and the second region;
the recess structure includes:
a second trench, a bottom of the second trench being located within the substrate;
the lining structure is provided with an arc-shaped opening, and the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove.
In one embodiment, the top of the liner structure is flush with the top of the first dielectric layer.
In one embodiment, the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises silicon dioxide.
In one embodiment, the material of the liner structure comprises tungsten.
In one embodiment, the thickness of the anti-reflection layer is less than the thickness of the second carbon layer.
In one embodiment, the first carbon layer and the mask layer conformally cover the inner surface of the second trench.
In one embodiment, the method further comprises the following steps:
and a patterned photoresist layer formed after the rework process and positioned above the anti-reflection layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment;
FIGS. 3a to 3g are schematic cross-sectional views of structures obtained at various steps in a method for fabricating a semiconductor structure according to an embodiment;
description of reference numerals:
31. a substrate; 32. overlaying a mark; 321. a first dielectric layer; 3211. a first trench; 3212. a dielectric layer groove; 3213. a second trench; 322. a second dielectric layer; 323. a recessed structure; 3231. a lining structure; 33. a first carbon layer; 34. a hard mask layer; 35. a second carbon layer; 36. an anti-reflection layer; 37. and a photoresist pattern layer.
Detailed Description
To facilitate an understanding of the present application, embodiments of the present application will be described more fully below with reference to the accompanying drawings. Some embodiments of the present application are presented in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, an embodiment of the present application provides a method for fabricating a semiconductor structure, including the following steps:
step S11, a substrate is provided.
In step S12, an overlay mark having a recessed structure is formed on a substrate.
In step S13, a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer are sequentially stacked on the overlay mark. The first carbon layer covers the concave structure, and the second carbon layer has a flat upper surface.
In the above example, an overlay mark having a recessed structure is formed on a substrate, and a first carbon layer, a hard mask layer, a second carbon layer, and an anti-reflection layer are sequentially stacked on the overlay mark. The second carbon layer has a flat upper surface, namely, the second carbon layer is not sunken any more, so that the anti-reflection layer above the second carbon layer can be uniformly deposited, the second carbon layer cannot be damaged in the process of carrying out rework treatment on the material on the upper layer of the anti-reflection layer, and the measurement of the overlay mark is prevented from being influenced by measurement noise.
In step S11, please refer to step S11 of fig. 1 and fig. 3a, the substrate 31 is provided.
In some examples, the substrate 31 may be a silicon substrate, a silicon-on-insulator substrate, or the like, and for example, the material of the substrate 31 may be selected according to the formed semiconductor structure.
In step S12, please refer to step S12 of fig. 1 and fig. 3e, an overlay mark 32 is formed on the substrate 31, wherein the overlay mark 32 has a concave structure 323.
In some examples, the overlay mark 32 includes a current layer overlay mark or/and a previous layer overlay mark. In the chip manufacturing process, a front layer overlay mark is formed through a front layer photoetching process, a current layer overlay mark is formed through a current layer photoetching process, and an overlay error is obtained through measuring the position relation between the front layer overlay mark and the current layer overlay mark. In this embodiment, the overlay mark 32 is a front layer overlay mark.
In the present embodiment, the overlay mark 32 formed on the substrate 31 has a concave structure 323. The recess structure 323 may be recessed toward the substrate 31. The opening of the concave structure 323 may be in the shape of an arc or an inverted trapezoid. By forming the recessed structure 323, the contrast of the overlay mark 32 can be increased, and the measurement accuracy can be improved.
In step S13, referring to step S13 of fig. 1 and fig. 3f, a first carbon layer 33, a hard mask layer 34, a second carbon layer 35 and an anti-reflective layer 36 are sequentially stacked on the overlay mark 32, wherein the first carbon layer 33 covers the recess 323, and the second carbon layer 35 has a flat top surface.
For example, the hard mask layer 34 may be silicon nitride (SiN), silicon oxide, or the like, and the anti-reflective layer 36 may be silicon oxynitride (SiON). The first carbon layer 33 and the second carbon layer 35 may be made of carbon (C). For example, the first carbon layer 33 may be formed using a Chemical Vapor Deposition (CVD) process, the second carbon layer 35 may be formed using a spin-on coating process, the hard mask layer 34 and the anti-reflective layer 36 may be formed using a Chemical Vapor Deposition (CVD) process, or the like. The first carbon layer 33 may be formed to cover the upper surface of the overlay mark 32, or may cover only the recessed structures 323 of the overlay mark 32. The thicknesses of the first carbon layer 33, the hard mask layer 34, the second carbon layer 35 and the anti-reflection layer 36 may be set according to actual requirements, and optionally, the thickness of the anti-reflection layer 36 may be set to be smaller than the thickness of the second carbon layer 35, so as to improve the transmission light intensity of the anti-reflection layer 36, increase the reflection light intensity of the overlay mark 32, and improve the detection signal intensity
Since the recessed structure 323 is recessed toward the substrate 31, the first carbon layer 33 and the hard mask layer 34 covering the recessed structure 323 may also be recessed toward the substrate 31. The contrast of the overlay mark 32 can be further enhanced, and the measurement accuracy can be improved.
In this embodiment, the second carbon layer 35 covering the hard mask layer 34 has a flat upper surface, so that the anti-reflection layer 36 formed on the second carbon layer 35 is prevented from being recessed at a position opposite to the recessed structure 323, and the anti-reflection layer 36 is advantageously uniformly deposited. If the anti-reflective layer 36 is recessed toward the substrate 31, defects may be generated in the recessed portion due to deposition unevenness, so that the second carbon layer 35 under the anti-reflective layer 36 is damaged due to the defects of the anti-reflective layer 36 when the rework process is performed on the material on the anti-reflective layer 36. For example, when the photoresist pattern layer spin-coated on the anti-reflection layer 36 for the first time is re-processed, since the material of the photoresist pattern layer is close to that of the second carbon layer 35, when the photoresist pattern layer spin-coated for the first time is removed by using oxygen or acid, the oxygen or acid may be eroded into the second carbon layer 35 due to the defect of the anti-reflection layer 36, causing a defect, and causing a decrease in the measurement quality of the overlay mark.
In some examples, the material of the second carbon layer 35 may be spin-on carbon (SOC), which has good fluidity and is beneficial to forming a flat upper surface. In other examples, the second carbon layer 35 may have a certain thickness, and if the upper surface of the formed second carbon layer 35 is recessed, the upper surface of the second carbon layer 35 may be planarized by a semiconductor process such as chemical mechanical polishing, so that the second carbon layer 35 has a flat upper surface.
In some examples, referring to fig. 2, the method for fabricating a semiconductor structure further includes a step S14 of performing a rework process on the photoresist pattern layer after forming the photoresist pattern layer on the anti-reflection layer.
For example, referring to fig. 3g, a photoresist pattern layer 37 may be formed on the anti-reflection layer 36 by a semiconductor process such as spin coating or slit coating, and then the photoresist pattern layer 37 may be exposed and developed to form a photoresist pattern on the photoresist pattern layer 37. The photoresist pattern layer 37 may be reworked, i.e., the photoresist pattern layer 37 is removed, during the process of forming the photoresist pattern layer 37 due to photoresist back-sputtering, insufficient lithography quality, and the like. In this embodiment, since the anti-reflection layer 36 is deposited uniformly without defects, when the photoresist pattern layer 37 is reworked, the oxygen does not chemically react with the second carbon layer 35 under the anti-reflection layer 36 to damage the second carbon layer 35, thereby preventing measurement noise caused by the overlay mark.
In some examples, referring to fig. 2 and fig. 3b to 3e, step S12 in fig. 1 includes:
step S121 is to form a first dielectric layer on the substrate, where the first dielectric layer includes a first region and a second region.
For example, the material of the first dielectric layer 321 may include silicon nitride (SiN), silicon oxide, or the like. For example, the first dielectric layer 321 may be formed on the substrate 31 by using atomic layer deposition, chemical vapor deposition process, or the like. The first dielectric layer 321 includes a first region a and a second region B. The first area a and the second area B may have a preset distance therebetween such that a third area C exists between the first area a and the second area B.
Step S122 is to form a plurality of first trenches in the first region and the second region of the first dielectric layer.
For example, the first grooves 3211 of the first region a may be arranged equidistantly, the first grooves 3211 of the second region B may be arranged equidistantly, and the sizes of the first grooves 3211 may be equal. For example, a trench mask layer and a trench photoresist layer may be sequentially formed on the first dielectric layer 321, a predetermined pattern may be formed at a position of the trench photoresist layer corresponding to the first region a and the second region B, then the pattern on the trench photoresist layer is transferred onto the trench mask layer, the trench photoresist layer is removed, and the first dielectric layer 321 is patterned based on the trench mask layer, so that a plurality of first trenches 3211 may be formed in the first region and the second region of the first dielectric layer 321, and then the trench mask layer may be removed.
Step S123, filling a second dielectric layer in the first groove; the top of the second dielectric layer is flush with the top of the first dielectric layer.
For example, the material of the second dielectric layer 322 may include silicon dioxide (SiO)2). The second dielectric layer 322 may be formed on the first dielectric layer 321 by using atomic layer deposition or chemical vapor deposition. The second dielectric layer 322 fills the first trenches 3211, and the second dielectric layer 322 may cover the top of the first dielectric layer 321. Then, the second dielectric layer 322 is polished by a semiconductor process such as chemical mechanical polishing, and the top of the first dielectric layer 321 may be used as a polishing endpoint, so that the top of the second dielectric layer 322 is flush with the top of the first dielectric layer 321.
Step S124, a second trench is formed between the first region and the second region, wherein the bottom of the second trench is located in the substrate.
Illustratively, the second trench 3213 is located between the first region a and the second region B, i.e., at the third region C. The size of the second groove 3213 may be set according to actual requirements. In this embodiment, the second trench 3213 penetrates the first dielectric layer 321 and extends into the substrate 31, i.e., the bottom of the second trench 3213 is located in the substrate 31. For example, the third region C of the first dielectric layer 321 may be etched simultaneously in the step of forming the plurality of first trenches 3211 on the first region a and the second region B of the first dielectric layer 321, or the third region C of the first dielectric layer 321 may be etched separately to form the dielectric layer trenches 3212. The substrate 31 is then patterned based on the first dielectric layer 321 to form a second trench 3213. The patterned substrate 31 may be formed by a semiconductor process such as dry etching. In this embodiment, the bottom of the second trench 3213 is located in the substrate 31, which can further enhance the contrast of the overlay mark 32 and improve the measurement accuracy.
In some examples, referring to fig. 2 and 3e, the method for fabricating the semiconductor structure further includes:
step S125, forming a liner structure with an arc-shaped opening at the bottom of the second trench, wherein the bottom and the sidewall of the liner structure are respectively matched with the bottom and the sidewall of the second trench, and the liner structure and the second trench form a concave structure.
In particular, the material of the liner structure 3231 may include a metal, such as tungsten. The bottom and sidewalls of the liner structure 3231 conform to the bottom and sidewalls of the second trench 3213, respectively. In this embodiment, the opening of the lining structure 3231 is arc-shaped, but in other examples, the opening of the lining structure 3231 may have other shapes such as an inverted trapezoid. The liner structure 3231 and the second trench 3213 form a recessed structure 323. The second trench 3213 may be filled with a lining material to form a lining structure 3231, and the thickness of the lining material may be set according to actual requirements. The arc-shaped opening of the lining structure 3231 facilitates good coverage of the subsequent first carbon layer 33.
It should be understood that although the steps in the flowcharts of fig. 1 and 2 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1 and 2 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.
In one embodiment, a semiconductor structure is also provided. Referring to fig. 3a to 3f, the semiconductor structure includes a substrate 31, an alignment mark 32, a first carbon layer 33, a hard mask layer 34, a second carbon layer 35, and an anti-reflection layer 36. An overlay mark 32 is located on the substrate 31, the overlay mark 32 including a recessed feature 323; the first carbon layer 33 covers the recess structures 323; a hard mask layer 34, a second carbon layer 35 and an anti-reflection layer 36 are sequentially stacked on the first carbon layer 33, and the second carbon layer 35 has a flat upper surface.
For example, the substrate 31 may be a silicon substrate, a silicon-on-insulator substrate, or the like, and for example, the material of the substrate 31 may be selected according to the formed semiconductor structure.
The overlay mark 32 is formed on the substrate 31 in this embodiment such that the formed overlay mark has a concave structure 323. The recessed structure 323 may be recessed toward the substrate 31. The opening of the concave structure 323 may be in the shape of an arc or an inverted trapezoid.
For example, the hard mask layer 34 may be silicon nitride (SiN) or silicon oxide, and the anti-reflective layer 36 may be silicon oxynitride (SiON). The first carbon layer 33 and the second carbon layer 35 may be made of carbon (C). The first carbon layer 33 may be formed to cover the upper surface of the overlay mark 32, or may cover only the recessed structures 323 of the overlay mark 32. The thicknesses of the first carbon layer 33, the hard mask layer 34, the second carbon layer 35 and the anti-reflection layer 36 may be set according to actual requirements, and optionally, the thickness of the anti-reflection layer 36 may be set to be smaller than the thickness of the second carbon layer 35, so as to improve the transmission light intensity of the anti-reflection layer 36, increase the reflection light intensity of the overlay mark 32, and improve the detection signal intensity.
Since the recessed structure 323 is recessed toward the substrate 31, the first carbon layer 33 and the hard mask layer 34 covering the recessed structure 323 may also be recessed toward the substrate 31. In this embodiment, the second carbon layer 35 has a flat upper surface, that is, the upper surface of the second carbon layer 35 is not recessed any more, so as to prevent the anti-reflection layer 36 formed on the second carbon layer 35 from being recessed at a position opposite to the recessed structure 323, which is beneficial to uniform deposition of the anti-reflection layer 36. If the anti-reflective layer 36 is recessed toward the substrate 31, defects may be generated in the recessed portion due to deposition unevenness, so that the second carbon layer 35 under the anti-reflective layer 36 is damaged due to the defects of the anti-reflective layer 36 when the rework process is performed on the material on the anti-reflective layer 36.
In some examples, the material of the second carbon layer 35 may specifically be spin-on carbon (SOC), which has good fluidity and is beneficial to forming the second carbon layer 35 with a flat upper surface. In another example, the second carbon layer 35 may have a certain thickness, and if the upper surface of the formed second carbon layer 35 is concave, the upper surface of the second carbon layer 35 may be planarized by a semiconductor process such as chemical mechanical polishing, so that the second carbon layer 35 has a flat upper surface.
The overlay mark in the semiconductor structure has a recess 323, and a first carbon layer 33, a hard mask layer 34, a second carbon layer 35 and an anti-reflection layer 36 are sequentially stacked on the overlay mark. Since the second carbon layer 35 has a flat upper surface, that is, is not recessed any more, the anti-reflection layer 36 above the second carbon layer 35 can be deposited uniformly, so that the second carbon layer 35 is not damaged in the process of performing rework treatment on the material on the upper layer of the anti-reflection layer 36, and the measurement of the overlay mark is prevented from being affected by measurement noise.
In some examples, the overlay mark further includes a first dielectric layer 321 having a plurality of first trenches 3211 and a second dielectric layer 322 located in the first trenches 3211. The first dielectric layer 321 includes a first region a and a second region B. The first trench 3211 is formed in the first and second regions a and B. The top of the second dielectric layer 322 is flush with the top of the first dielectric layer 321.
For example, the material of the first dielectric layer 321 may include silicon nitride (SiN). The first dielectric layer 321 includes a first region a and a second region B. The first area a and the second area B may have a preset distance therebetween. The first trench 3211 is formed in the first and second regions a and B.
For example, the first grooves 3211 of the first region a may be arranged equidistantly, the first grooves 3211 of the second region B may be arranged equidistantly, and the sizes of the first grooves 3211 may all be equal.
For example, the material of the second dielectric layer 322 may include silicon dioxide (SiO)2). The top of the second dielectric layer 322 is flush with the top of the first dielectric layer 321.
In some examples, the recessed structures 323 are located between the first region a and the second region B. The recess structure 323 includes a second trench 3213 and a liner structure 3231. The bottom of the second trench 3213 is located within the substrate 31. The lining structure 3231 has an arc-shaped opening, and the bottom and the sidewall of the lining structure 3231 are respectively matched with the bottom and the sidewall of the second trench 3213.
Illustratively, the second trench 3213 is located between the first region a and the second region B, i.e., the third region C. The size of the second groove 3213 may be set according to actual requirements. In this embodiment, the second trench 3213 penetrates the first dielectric layer 321 and extends into the substrate 31, i.e., the bottom of the second trench 3213 is located in the substrate 31.
Illustratively, the material of the liner structure 3231 may include a metal, such as tungsten. The bottom and sidewalls of the liner structure 3231 conform to the bottom and sidewalls of the second trench 3213, respectively. In this embodiment, the opening of the lining structure 3231 is arc-shaped, but in other examples, the opening of the lining structure 3231 may have other shapes such as an inverted trapezoid. The liner structure 3231 and the second trench 3213 form a recessed structure 323. The second trench 3213 may be filled with a lining material to form a lining structure 3231, and the thickness of the lining material may be set according to actual requirements.
In some examples, the top of the liner structure 3231 is flush with the top of the first dielectric layer 321.
In some examples, the thickness of the anti-reflective layer 36 is less than the thickness of the second carbon layer 35.
In some examples, the first carbon layer 33 and the hard mask layer 34 conformally cover the inner surface of the second trench 3213.
In some examples, a patterned photoresist layer over antireflective layer 36 formed after a rework process is also included.
For example, referring to fig. 3g, a photoresist pattern layer 37 may be formed over the anti-reflective layer 36. The photoresist pattern layer 37 may be reworked, i.e., the photoresist pattern layer 37 is removed, during the process of forming the photoresist pattern layer 37 due to photoresist back-sputtering, insufficient lithography quality, and the like. In this embodiment, since the anti-reflection layer 36 is deposited uniformly without defects, when the photoresist pattern layer 37 is reworked, oxygen or acid does not chemically react with the second carbon layer 35 under the anti-reflection layer 36 to damage the second carbon layer 35, thereby preventing measurement noise from being caused to the measurement of the overlay mark. A patterned photoresist layer may also be formed over antireflective layer 36 again after the rework process.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (16)

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an overlay mark on the substrate, wherein the overlay mark has a concave structure;
and sequentially stacking a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the alignment mark, wherein the first carbon layer covers the recessed structure, and the second carbon layer has a flat upper surface.
2. The method of claim 1, further comprising: and performing rework treatment on the photoresist pattern layer after the photoresist pattern layer is formed on the anti-reflection layer.
3. The method of claim 2, wherein the step of forming an overlay mark on the substrate comprises:
forming a first dielectric layer on the substrate, wherein the first dielectric layer comprises a first area and a second area;
forming a plurality of first trenches on the first region and the second region of the first dielectric layer;
filling a second dielectric layer in the first groove; the top of the second dielectric layer is flush with the top of the first dielectric layer;
forming a second trench between the first region and the second region, wherein a bottom of the second trench is located within the substrate.
4. The method of claim 3, further comprising:
and forming a lining structure with an arc-shaped opening at the bottom of the second groove, wherein the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove, and the lining structure and the second groove form the recessed structure.
5. The method of claim 4, wherein the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises silicon dioxide.
6. The method of claim 4, wherein the liner structure comprises tungsten.
7. The method as claimed in claim 1, wherein the anti-reflection layer has a thickness smaller than that of the second carbon layer.
8. A semiconductor structure, comprising:
a substrate;
an overlay mark on the substrate, the overlay mark including a recessed structure;
a first carbon layer covering the recessed structure;
the hard mask layer, the second carbon layer and the antireflection layer are sequentially stacked on the first carbon layer, and the second carbon layer is provided with a flat upper surface.
9. The semiconductor structure of claim 8, wherein the overlay mark further comprises:
a first dielectric layer having a plurality of first trenches, the first dielectric layer including a first region and a second region; the first groove is formed in the first region and the second region;
and the top of the second dielectric layer is flush with the top of the first dielectric layer.
10. The semiconductor structure of claim 9, wherein the recessed structure is located between the first region and the second region;
the recess structure includes:
a second trench, a bottom of the second trench being located within the substrate;
the lining structure is provided with an arc-shaped opening, and the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove.
11. The semiconductor structure of claim 10, wherein a top of the liner structure is flush with a top of the first dielectric layer.
12. The semiconductor structure of claim 10, wherein the material of the first dielectric layer comprises silicon nitride and the material of the second dielectric layer comprises silicon dioxide.
13. The semiconductor structure of claim 10, wherein the liner structure comprises tungsten.
14. The semiconductor structure of claim 10, wherein a thickness of the anti-reflective layer is less than a thickness of the second carbon layer.
15. The semiconductor structure of claim 10, wherein the first carbon layer and the hard mask layer conformally cover the inner surface of the second trench.
16. The semiconductor structure of claim 8, further comprising:
and a patterned photoresist layer formed after the rework process and positioned above the anti-reflection layer.
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020192926A1 (en) * 2001-06-18 2002-12-19 Schroeder Uwe Paul High contrast lithography alignment marks for semiconductor manufacturing
US6534378B1 (en) * 1998-08-31 2003-03-18 Cypress Semiconductor Corp. Method for forming an integrated circuit device
US20070212652A1 (en) * 2006-03-08 2007-09-13 Asml Netherlands B.V. Method and system for enhanced lithographic alignment
KR20100072554A (en) * 2008-12-22 2010-07-01 주식회사 동부하이텍 Overlay mark of flash memory device and method for forming thereof
US20140065736A1 (en) * 2012-09-06 2014-03-06 Kla-Tencor Corporation Device correlated metrology (dcm) for ovl with embedded sem structure overlay targets
US20160035617A1 (en) * 2014-07-30 2016-02-04 Jong-Su Kim Overlay marks, methods of forming the same, and methods of fabricating semiconductor devices using the same
US20170077103A1 (en) * 2015-09-10 2017-03-16 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN111312591A (en) * 2020-02-25 2020-06-19 上海华力集成电路制造有限公司 Method for preventing residue from forming on overlay alignment mark
CN112750821A (en) * 2019-10-30 2021-05-04 台湾积体电路制造股份有限公司 Semiconductor device with a plurality of semiconductor chips

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534378B1 (en) * 1998-08-31 2003-03-18 Cypress Semiconductor Corp. Method for forming an integrated circuit device
US20020192926A1 (en) * 2001-06-18 2002-12-19 Schroeder Uwe Paul High contrast lithography alignment marks for semiconductor manufacturing
US20070212652A1 (en) * 2006-03-08 2007-09-13 Asml Netherlands B.V. Method and system for enhanced lithographic alignment
KR20100072554A (en) * 2008-12-22 2010-07-01 주식회사 동부하이텍 Overlay mark of flash memory device and method for forming thereof
US20140065736A1 (en) * 2012-09-06 2014-03-06 Kla-Tencor Corporation Device correlated metrology (dcm) for ovl with embedded sem structure overlay targets
US20160035617A1 (en) * 2014-07-30 2016-02-04 Jong-Su Kim Overlay marks, methods of forming the same, and methods of fabricating semiconductor devices using the same
US20170077103A1 (en) * 2015-09-10 2017-03-16 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN112750821A (en) * 2019-10-30 2021-05-04 台湾积体电路制造股份有限公司 Semiconductor device with a plurality of semiconductor chips
CN111312591A (en) * 2020-02-25 2020-06-19 上海华力集成电路制造有限公司 Method for preventing residue from forming on overlay alignment mark

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