CN113517178B - Method for preparing semiconductor structure and semiconductor structure - Google Patents
Method for preparing semiconductor structure and semiconductor structure Download PDFInfo
- Publication number
- CN113517178B CN113517178B CN202110774536.9A CN202110774536A CN113517178B CN 113517178 B CN113517178 B CN 113517178B CN 202110774536 A CN202110774536 A CN 202110774536A CN 113517178 B CN113517178 B CN 113517178B
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- overlay mark
- substrate
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The application relates to a preparation method of a semiconductor structure and the semiconductor structure, comprising the following steps: providing a substrate; forming an overlay mark on the substrate, wherein the overlay mark has a concave structure; and sequentially stacking and forming a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the overlay mark, wherein the first carbon layer covers the concave structure, and the second carbon layer has a flat upper surface. The preparation method of the semiconductor structure can enable measurement of the overlay mark to be free from influence of measurement noise.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a preparation method of a semiconductor structure and the semiconductor structure.
Background
The measurement quality of overlay mark (OVL mark) has an important influence on the product yield, and in the actual production process, the overlay mark is often affected by some adverse factors, such as photolithography reworking procedure. How to ensure the measurement quality of the overlay mark under the influence of various adverse factors is a problem to be solved by the phagocytosis.
Content of the application
In order to improve measurement quality of overlay marks, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same.
According to some embodiments, an aspect of the present application provides a method for preparing a semiconductor structure, including:
providing a substrate;
forming an overlay mark on the substrate, wherein the overlay mark has a concave structure;
and sequentially stacking and forming a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the overlay mark, wherein the first carbon layer covers the concave structure, and the second carbon layer has a flat upper surface.
The preparation method of the semiconductor structure comprises the steps of forming an overlay mark on a substrate, wherein the overlay mark is provided with a concave structure, and sequentially stacking a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the overlay mark. The second carbon layer has a flat upper surface, namely the second carbon layer is not recessed any more, so that the anti-reflection layer above the second carbon layer can be uniformly deposited, the second carbon layer is not damaged in the reworking process of the material on the upper layer of the anti-reflection layer, and the measurement of the overlay mark is prevented from being influenced by measurement noise.
In one embodiment, the method further comprises: and reworking the photoresist pattern layer after forming the photoresist pattern layer on the anti-reflection layer.
In one embodiment, the step of forming an overlay mark on the substrate includes:
forming a first dielectric layer on the substrate, wherein the first dielectric layer comprises a first area and a second area;
forming a plurality of first trenches on the first region and the second region of the first dielectric layer;
filling a second dielectric layer in the first groove; the top of the second dielectric layer is flush with the top of the first dielectric layer;
a second trench is formed between the first region and the second region, wherein a bottom of the second trench is located within the substrate.
In one embodiment, the method further comprises:
and forming an arc-shaped opening lining structure at the bottom of the second groove, wherein the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove, and the lining structure and the second groove form the concave structure.
In one embodiment, the material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes silicon dioxide.
In one embodiment, the liner structure comprises tungsten.
In one embodiment, the thickness of the anti-reflective layer is less than the thickness of the second carbon layer.
According to some embodiments, another aspect of the present application provides a semiconductor structure, comprising:
a substrate;
an overlay mark on the substrate, the overlay mark comprising a recessed structure;
a first carbon layer covering the recessed structure;
the hard mask layer, the second carbon layer and the anti-reflection layer are sequentially stacked on the first carbon layer, and the second carbon layer is provided with a flat upper surface.
The overlay mark in the semiconductor structure is provided with a concave structure, and a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer are sequentially stacked on the overlay mark. The second carbon layer has a flat upper surface, namely the second carbon layer is not recessed any more, so that the anti-reflection layer above the second carbon layer can be uniformly deposited, the second carbon layer is not damaged in the reworking process of the material on the upper layer of the anti-reflection layer, and the measurement of the overlay mark is prevented from being influenced by measurement noise.
In one embodiment, the overlay mark further comprises:
a first dielectric layer having a plurality of first trenches, the first dielectric layer including a first region and a second region; each first groove is formed in the first area and the second area;
and the top of the second dielectric layer is flush with the top of the first dielectric layer.
In one embodiment, the recessed feature is located between the first region and the second region;
the recessed structure includes:
a second trench, the bottom of which is located in the substrate;
the lining structure is provided with an arc opening, and the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove.
In one embodiment, the top of the liner structure is flush with the top of the first dielectric layer.
In one embodiment, the material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes silicon dioxide.
In one embodiment, the liner structure comprises tungsten.
In one embodiment, the thickness of the anti-reflective layer is less than the thickness of the second carbon layer.
In one embodiment, the first carbon layer and the mask layer conformally cover the inner surface of the second trench.
In one embodiment, the method further comprises:
and a photoresist layer which is formed after the reworking treatment and is positioned above the anti-reflection layer for patterning.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment;
FIGS. 3a to 3g are schematic cross-sectional views of structures obtained at various steps in a method for fabricating a semiconductor structure according to one embodiment;
reference numerals illustrate:
31. a substrate; 32. overlay mark; 321. a first dielectric layer; 3211. a first trench; 3212. a dielectric layer trench; 3213. a second trench; 322. a second dielectric layer; 323. a recessed structure; 3231. a liner structure; 33. a first carbon layer; 34. a hard mask layer; 35. a second carbon layer; 36. an anti-reflection layer; 37. and a photoresist pattern layer.
Detailed Description
In order to facilitate an understanding of the present application, embodiments of the present application will be described more fully below with reference to the accompanying drawings. Some embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including the following steps:
step S11, providing a substrate.
Step S12, forming an overlay mark on the substrate, wherein the overlay mark has a concave structure.
Step S13, sequentially stacking and forming a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the overlay mark. The first carbon layer covers the concave structure, and the second carbon layer has a flat upper surface.
In the above example, the overlay mark is formed on the substrate, the overlay mark has a concave structure, and the first carbon layer, the hard mask layer, the second carbon layer, and the anti-reflection layer are sequentially stacked on the overlay mark. The second carbon layer has a flat upper surface, namely the second carbon layer is not recessed any more, so that the anti-reflection layer above the second carbon layer can be uniformly deposited, the second carbon layer is not damaged in the reworking process of the material on the upper layer of the anti-reflection layer, and the measurement of the overlay mark is prevented from being influenced by measurement noise.
In step S11, referring to step S11 of fig. 1 and fig. 3a, a substrate 31 is provided.
In some examples, the substrate 31 may be a silicon substrate, a silicon-on-insulator substrate, or the like, for example, the material of the substrate 31 may be selected depending on the semiconductor structure being formed.
In step S12, referring to step S12 of fig. 1 and fig. 3e, an overlay mark 32 is formed on a substrate 31, and the overlay mark 32 has a concave structure 323.
In some examples, overlay mark 32 includes a current layer overlay mark or/and a previous layer overlay mark. In the chip manufacturing process, a front layer alignment mark is formed through a front layer photoetching process, a current layer alignment mark is formed through a current layer photoetching process, and alignment errors are obtained through measuring the position relationship between the front layer alignment mark and the current layer alignment mark. In this embodiment, the overlay mark 32 is a front layer overlay mark.
In this embodiment, the overlay mark 32 formed on the substrate 31 has a concave structure 323. The recess structure 323 may be recessed toward the direction in which the substrate 31 is located. The opening of the recess 323 may be arc-shaped or inverted trapezoid-shaped. By forming the recess structure 323, the contrast of the overlay mark 32 can be increased, and the measurement accuracy can be improved.
In step S13, referring to step S13 of fig. 1 and fig. 3f, a first carbon layer 33, a hard mask layer 34, a second carbon layer 35 and an anti-reflective layer 36 are sequentially stacked on the overlay mark 32, wherein the first carbon layer 33 covers the recess structure 323, and the second carbon layer 35 has a flat upper surface.
For example, the hard mask layer 34 may be silicon nitride (SiN), silicon oxide, etc., and the anti-reflective layer 36 may be silicon oxynitride (SiON). The materials of the first carbon layer 33 and the second carbon layer 35 may be carbon (C). For example, the first carbon layer 33 may be formed using a Chemical Vapor Deposition (CVD) process, the second carbon layer 35 may be formed using a spin-on process, the hard mask layer 34 and the anti-reflection layer 36 may be formed using a Chemical Vapor Deposition (CVD) process, or the like. The first carbon layer 33 may cover the upper surface of the overlay mark 32, or may cover only the recess 323 of the overlay mark 32. The thicknesses of the first carbon layer 33, the hard mask layer 34, the second carbon layer 35 and the anti-reflection layer 36 may be set according to actual requirements, and optionally, the thickness of the anti-reflection layer 36 may be set smaller than that of the second carbon layer 35 to improve the transmission light intensity of the anti-reflection layer 36, increase the reflection light intensity of the overlay mark 32, and improve the detection signal intensity
Since the recess structure 323 is recessed toward the substrate 31, the first carbon layer 33 and the hard mask layer 34 covering the recess structure 323 may also be recessed toward the substrate 31. The contrast of the overlay mark 32 can be further enhanced and the measurement accuracy can be improved.
In this embodiment, the second carbon layer 35 covered on the hard mask layer 34 has a flat upper surface, so that the anti-reflection layer 36 formed on the second carbon layer 35 is prevented from being recessed at a position opposite to the recessed structure 323, which is beneficial to uniformly depositing the anti-reflection layer 36. If the anti-reflection layer 36 is recessed toward the substrate 31, defects may be generated in the recessed portion due to uneven deposition, so that the second carbon layer 35 under the anti-reflection layer 36 is damaged due to the defects of the anti-reflection layer 36 when reworking the material on the upper layer of the anti-reflection layer 36. For example, when the photoresist pattern layer spin-coated for the first time on the anti-reflection layer 36 is reworked, since the material of the photoresist pattern layer is close to that of the second carbon layer 35, defects may be caused due to oxygen or acid attack into the second carbon layer 35 by the defects of the anti-reflection layer 36 when the photoresist pattern layer spin-coated for the first time is removed by oxygen or acid, resulting in degradation of the measurement quality of the overlay mark.
In some examples, the material of the second carbon layer 35 may be spin-on carbon (SOC), which has better fluidity and is beneficial to forming a flat upper surface. In other examples, the second carbon layer 35 may have a certain thickness, and if the upper surface of the formed second carbon layer 35 is recessed, the upper surface of the second carbon layer 35 may be planarized by a semiconductor process such as chemical mechanical polishing, so that the second carbon layer 35 has a flat upper surface.
In some examples, referring to fig. 2, the method for manufacturing a semiconductor structure further includes step S14, where the photoresist pattern layer is reworked after the photoresist pattern layer is formed on the anti-reflection layer.
For example, referring to fig. 3g, a photoresist pattern layer 37 may be formed over the anti-reflection layer 36 in a semiconductor process such as spin coating or slot coating, and then the photoresist pattern layer 37 may be further subjected to exposure, development, and the like such that a photoresist pattern is formed on the photoresist pattern layer 37. In the process of forming the photoresist pattern layer 37, reworking treatment may be performed on the photoresist pattern layer 37, i.e., the photoresist pattern layer 37 may be removed due to back splash of photoresist, insufficient photolithography quality, etc. In this embodiment, since the anti-reflection layer 36 is uniformly deposited without defects, oxygen will not chemically react with the second carbon layer 35 under the anti-reflection layer 36 during reworking the photoresist pattern layer 37, thereby damaging the second carbon layer 35, and thus avoiding measurement noise caused by overlay mark.
In some examples, referring to fig. 2 and fig. 3b to fig. 3e, step S12 in fig. 1 includes:
in step S121, a first dielectric layer is formed on a substrate, where the first dielectric layer includes a first region and a second region.
Illustratively, the material of the first dielectric layer 321 may include silicon nitride (SiN) or silicon oxide. For example, the first dielectric layer 321 may be formed on the substrate 31 using atomic layer deposition, chemical vapor deposition process, or the like. The first dielectric layer 321 includes a first region a and a second region B. The first area a and the second area B may have a preset distance therebetween such that a third area C exists between the first area a and the second area B.
In step S122, a plurality of first trenches are formed on the first region and the second region of the first dielectric layer.
For example, the first grooves 3211 of the first region a may be arranged at equal intervals, the first grooves 3211 of the second region B may be arranged at equal intervals, and the sizes of the respective first grooves 3211 may be equal. For example, a trench mask layer and a trench photoresist layer may be sequentially formed on the first dielectric layer 321, a preset pattern is formed at a position of the trench photoresist layer corresponding to the first region a and the second region B, then the pattern on the trench photoresist layer is transferred onto the trench mask layer, the trench photoresist layer is removed, and the first dielectric layer 321 is patterned based on the trench mask layer, so that a plurality of first trenches 3211 are formed in the first region and the second region of the first dielectric layer 321, and then the trench mask layer may be removed.
Step S123, filling a second dielectric layer in the first groove; the top of the second dielectric layer is flush with the top of the first dielectric layer.
For example, the material of the second dielectric layer 322 may include silicon dioxide (SiO 2 ). The second dielectric layer 322 may be formed on the first dielectric layer 321 by an atomic layer deposition or a chemical vapor deposition process. The second dielectric layer 322 fills each of the first dielectric layersTrench 3211, and at this time, second dielectric layer 322 may cover the top of first dielectric layer 321. Then, the second dielectric layer 322 is polished by using a semiconductor process such as chemical mechanical polishing, and the top of the first dielectric layer 321 may be used as a polishing endpoint, so that the top of the second dielectric layer 322 is flush with the top of the first dielectric layer 321.
In step S124, a second trench is formed between the first region and the second region, wherein a bottom of the second trench is located in the substrate.
The second trench 3213 is illustratively located between the first region a and the second region B, i.e., in the third region C. The dimensions of the second grooves 3213 may be set according to actual requirements. In this embodiment, the second trench 3213 penetrates the first dielectric layer 321 and extends into the substrate 31, i.e. the bottom of the second trench 3213 is located in the substrate 31. For example, the third region C of the first dielectric layer 321 may be etched simultaneously in the step of forming the plurality of first trenches 3211 on the first region a and the second region B of the first dielectric layer 321, or the third region C of the first dielectric layer 321 may be etched separately to form the dielectric layer trenches 3212. Thereafter, the substrate 31 is patterned based on the first dielectric layer 321, thereby forming a second trench 3213. The patterned substrate 31 may employ a semiconductor process such as dry etching. In this embodiment, the bottom of the second trench 3213 is located in the substrate 31, so that the contrast of the overlay mark 32 can be further enhanced, and the measurement accuracy can be improved.
In some examples, referring to fig. 2 and 3e, the method for preparing the semiconductor structure further includes:
in step S125, an arc-shaped opening liner structure is formed at the bottom of the second trench, and the bottom and the side wall of the liner structure are respectively matched with the bottom and the side wall of the second trench, and the liner structure and the second trench form a concave structure.
Specifically, the material of the liner structure 3231 can include a metal, such as tungsten. The bottom and side walls of the lining structure 3231 conform to the bottom and side walls of the second channel 3213, respectively. In this embodiment, the opening of the lining structure 3231 is arc-shaped, and in other examples, the opening of the lining structure 3231 may have other shapes such as inverted trapezoid. The liner structure 3231 and the second trench 3213 constitute a recess structure 323. The second trenches 3213 may be filled with a liner material to form a liner structure 3231, and a thickness of the liner material may be set according to actual needs. The arcuate open liner structure 3231 facilitates good coverage of the subsequent first carbon layer 33.
It should be understood that, although the steps in the flowcharts of fig. 1 and 2 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 and 2 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, a semiconductor structure is also provided. Referring to fig. 3a to 3f, the semiconductor structure includes a substrate 31, an overlay mark 32, a first carbon layer 33, a hard mask layer 34, a second carbon layer 35, and an anti-reflective layer 36. An overlay mark 32 is located on the substrate 31, the overlay mark 32 comprising a recessed feature 323; the first carbon layer 33 covers the recess structure 323; the hard mask layer 34, the second carbon layer 35 and the anti-reflection layer 36 are sequentially stacked on the first carbon layer 33, and the second carbon layer 35 has a flat upper surface.
By way of example, the substrate 31 may be a silicon substrate, a silicon-on-insulator substrate, or the like, and the material of the substrate 31 may be selected, for example, in accordance with the semiconductor structure being formed.
The overlay mark 32 is formed on the substrate 31 in this embodiment such that the overlay mark is formed with a recessed structure 323. The recess structure 323 may be recessed toward the direction in which the substrate 31 is located. The opening of the recess 323 may be arc-shaped or inverted trapezoid-shaped.
For example, the hard mask layer 34 may be silicon nitride (SiN) or silicon oxide, and the anti-reflective layer 36 may be silicon oxynitride (SiON). The materials of the first carbon layer 33 and the second carbon layer 35 may be carbon (C). The first carbon layer 33 may cover the upper surface of the overlay mark 32, or may cover only the recess 323 of the overlay mark 32. The thicknesses of the first carbon layer 33, the hard mask layer 34, the second carbon layer 35 and the anti-reflection layer 36 may be set according to actual requirements, and optionally, the thickness of the anti-reflection layer 36 may be set smaller than that of the second carbon layer 35, so as to improve the transmission light intensity of the anti-reflection layer 36, increase the reflection light intensity of the overlay mark 32, and improve the detection signal intensity.
Since the recess structure 323 is recessed toward the substrate 31, the first carbon layer 33 and the hard mask layer 34 covering the recess structure 323 may also be recessed toward the substrate 31. In this embodiment, the second carbon layer 35 has a flat upper surface, i.e. the upper surface of the second carbon layer 35 is not recessed any more, so as to avoid the anti-reflective layer 36 formed above the second carbon layer 35 being recessed at a position opposite to the recessed structure 323, which is beneficial for uniform deposition of the anti-reflective layer 36. If the anti-reflection layer 36 is recessed toward the substrate 31, defects may be generated in the recessed portion due to uneven deposition, so that the second carbon layer 35 under the anti-reflection layer 36 is damaged due to the defects of the anti-reflection layer 36 when reworking the material on the upper layer of the anti-reflection layer 36.
In some examples, the material of the second carbon layer 35 may be specifically spin-on carbon (SOC), which has better fluidity and is beneficial to forming the second carbon layer 35 with a flat upper surface. In other examples, the second carbon layer 35 may have a certain thickness, and if the upper surface of the formed second carbon layer 35 is recessed, the upper surface of the second carbon layer 35 may be planarized by a semiconductor process such as chemical mechanical polishing, so that the second carbon layer 35 has a flat upper surface.
The overlay mark in the semiconductor structure has a concave structure 323, and a first carbon layer 33, a hard mask layer 34, a second carbon layer 35 and an anti-reflection layer 36 are stacked in order on the overlay mark. Since the second carbon layer 35 has a flat upper surface, i.e. no longer recessed, the anti-reflective layer 36 over the second carbon layer 35 can be deposited uniformly, so that the second carbon layer 35 is not damaged during the reworking of the material on top of the anti-reflective layer 36, and the measurement of the overlay mark is protected from measurement noise.
In some examples, the overlay mark further includes a first dielectric layer 321 having a plurality of first trenches 3211 and a second dielectric layer 322 located within the first trenches 3211. The first dielectric layer 321 includes a first region a and a second region B. The first trench 3211 is formed in the first region a and the second region B. The top of the second dielectric layer 322 is flush with the top of the first dielectric layer 321.
Illustratively, the material of the first dielectric layer 321 may include silicon nitride (SiN). The first dielectric layer 321 includes a first region a and a second region B. The first region a and the second region B may have a preset distance therebetween. The first trench 3211 is formed in the first region a and the second region B.
For example, the first grooves 3211 of the first region a may be arranged at equal intervals, the first grooves 3211 of the second region B may be arranged at equal intervals, and the first grooves 3211 may have equal sizes.
For example, the material of the second dielectric layer 322 may include silicon dioxide (SiO 2 ). The top of the second dielectric layer 322 is flush with the top of the first dielectric layer 321.
In some examples, the recessed feature 323 is located between the first region a and the second region B. The recess structure 323 includes a second trench 3213 and a liner structure 3231. The bottom of the second trench 3213 is located within the substrate 31. The inner lining structure 3231 has an arc-shaped opening, and the bottom and the side walls of the inner lining structure 3231 are respectively matched with the bottom and the side walls of the second groove 3213.
The second trench 3213 is illustratively located between the first region a and the second region B, i.e., the third region C. The dimensions of the second grooves 3213 may be set according to actual requirements. In this embodiment, the second trench 3213 penetrates the first dielectric layer 321 and extends into the substrate 31, i.e. the bottom of the second trench 3213 is located in the substrate 31.
By way of example, the material of the liner structure 3231 can include a metal, such as tungsten. The bottom and side walls of the lining structure 3231 conform to the bottom and side walls of the second channel 3213, respectively. In this embodiment, the opening of the lining structure 3231 is arc-shaped, and in other examples, the opening of the lining structure 3231 may have other shapes such as inverted trapezoid. The liner structure 3231 and the second trench 3213 constitute a recess structure 323. The second trenches 3213 may be filled with a liner material to form a liner structure 3231, and a thickness of the liner material may be set according to actual needs.
In some examples, the top of liner structure 3231 is flush with the top of first dielectric layer 321.
In some examples, the thickness of the anti-reflective layer 36 is less than the thickness of the second carbon layer 35.
In some examples, first carbon layer 33 and hard mask layer 34 conformally cover the inner surfaces of second trenches 3213.
In some examples, a photoresist layer patterned over antireflective layer 36 formed after the rework process is also included.
For example, referring to fig. 3g, a photoresist pattern layer 37 may be formed over the anti-reflection layer 36. In the process of forming the photoresist pattern layer 37, reworking treatment may be performed on the photoresist pattern layer 37, i.e., the photoresist pattern layer 37 may be removed due to back splash of photoresist, insufficient photolithography quality, etc. In this embodiment, since the anti-reflection layer 36 is uniformly deposited without defects, oxygen or acid will not react with the second carbon layer 35 under the anti-reflection layer 36 to damage the second carbon layer 35 during reworking the photoresist pattern layer 37, thereby avoiding measurement noise caused by overlay mark. A patterned photoresist layer may also be formed over antireflective layer 36 again after the rework process.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (16)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming an overlay mark on the substrate, wherein the overlay mark has a concave structure;
sequentially stacking a first carbon layer, a hard mask layer, a second carbon layer and an anti-reflection layer on the overlay mark, wherein the first carbon layer covers the concave structure, and the second carbon layer has a flat upper surface;
the overlay mark comprises a first dielectric layer with a plurality of first grooves, the first dielectric layer comprises a first area and a second area, the first grooves are formed in the first area and the second area, and the concave structure is located between the first area and the second area.
2. The method of fabricating a semiconductor structure of claim 1, further comprising: and reworking the photoresist pattern layer after forming the photoresist pattern layer on the anti-reflection layer.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein the step of forming an overlay mark on the substrate comprises:
forming a first dielectric layer on the substrate, wherein the first dielectric layer comprises a first area and a second area;
forming a plurality of first trenches on the first region and the second region of the first dielectric layer;
filling a second dielectric layer in the first groove; the top of the second dielectric layer is flush with the top of the first dielectric layer;
a second trench is formed between the first region and the second region, wherein a bottom of the second trench is located within the substrate.
4. The method of fabricating a semiconductor structure of claim 3, further comprising:
and forming an arc-shaped opening lining structure at the bottom of the second groove, wherein the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove, and the lining structure and the second groove form the concave structure.
5. The method of claim 4, wherein the material of the first dielectric layer comprises silicon nitride and the material of the second dielectric layer comprises silicon dioxide.
6. The method of claim 4, wherein the liner structure comprises tungsten.
7. The method of claim 1, wherein the thickness of the anti-reflective layer is less than the thickness of the second carbon layer.
8. A semiconductor structure, comprising:
a substrate;
an overlay mark on the substrate, the overlay mark comprising a recessed structure;
a first carbon layer covering the recessed structure;
the hard mask layer, the second carbon layer and the anti-reflection layer are sequentially stacked on the first carbon layer, and the second carbon layer is provided with a flat upper surface;
the overlay mark comprises a first dielectric layer with a plurality of first grooves, the first dielectric layer comprises a first area and a second area, the first grooves are formed in the first area and the second area, and the concave structure is located between the first area and the second area.
9. The semiconductor structure of claim 8, wherein the overlay mark further comprises:
and the top of the second dielectric layer is flush with the top of the first dielectric layer.
10. The semiconductor structure of claim 9, wherein the recess structure comprises:
a second trench, the bottom of which is located in the substrate;
the lining structure is provided with an arc opening, and the bottom and the side wall of the lining structure are respectively matched with the bottom and the side wall of the second groove.
11. The semiconductor structure of claim 10, wherein a top of the liner structure is flush with a top of the first dielectric layer.
12. The semiconductor structure of claim 10, wherein the material of the first dielectric layer comprises silicon nitride and the material of the second dielectric layer comprises silicon dioxide.
13. The semiconductor structure of claim 10, wherein the liner structure comprises tungsten.
14. The semiconductor structure of claim 10, wherein a thickness of the anti-reflective layer is less than a thickness of the second carbon layer.
15. The semiconductor structure of claim 10, wherein the first carbon layer and the hard mask layer conformally cover an inner surface of the second trench.
16. The semiconductor structure of claim 8, further comprising:
and a photoresist layer which is formed after the reworking treatment and is positioned above the anti-reflection layer for patterning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110774536.9A CN113517178B (en) | 2021-07-08 | 2021-07-08 | Method for preparing semiconductor structure and semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110774536.9A CN113517178B (en) | 2021-07-08 | 2021-07-08 | Method for preparing semiconductor structure and semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113517178A CN113517178A (en) | 2021-10-19 |
| CN113517178B true CN113517178B (en) | 2023-06-27 |
Family
ID=78067101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110774536.9A Active CN113517178B (en) | 2021-07-08 | 2021-07-08 | Method for preparing semiconductor structure and semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113517178B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534378B1 (en) * | 1998-08-31 | 2003-03-18 | Cypress Semiconductor Corp. | Method for forming an integrated circuit device |
| KR20100072554A (en) * | 2008-12-22 | 2010-07-01 | 주식회사 동부하이텍 | Overlay mark of flash memory device and method for forming thereof |
| CN111312591A (en) * | 2020-02-25 | 2020-06-19 | 上海华力集成电路制造有限公司 | Method for preventing residue from forming on overlay alignment mark |
| CN112750821A (en) * | 2019-10-30 | 2021-05-04 | 台湾积体电路制造股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020192926A1 (en) * | 2001-06-18 | 2002-12-19 | Schroeder Uwe Paul | High contrast lithography alignment marks for semiconductor manufacturing |
| US7598024B2 (en) * | 2006-03-08 | 2009-10-06 | Asml Netherlands B.V. | Method and system for enhanced lithographic alignment |
| US9093458B2 (en) * | 2012-09-06 | 2015-07-28 | Kla-Tencor Corporation | Device correlated metrology (DCM) for OVL with embedded SEM structure overlay targets |
| KR20160015094A (en) * | 2014-07-30 | 2016-02-12 | 삼성전자주식회사 | Overlay Marks, methods of Fabricating the Same, and Method of fabricating Semiconductor Devices Using the Same |
| KR102302597B1 (en) * | 2015-09-10 | 2021-09-15 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
-
2021
- 2021-07-08 CN CN202110774536.9A patent/CN113517178B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534378B1 (en) * | 1998-08-31 | 2003-03-18 | Cypress Semiconductor Corp. | Method for forming an integrated circuit device |
| KR20100072554A (en) * | 2008-12-22 | 2010-07-01 | 주식회사 동부하이텍 | Overlay mark of flash memory device and method for forming thereof |
| CN112750821A (en) * | 2019-10-30 | 2021-05-04 | 台湾积体电路制造股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN111312591A (en) * | 2020-02-25 | 2020-06-19 | 上海华力集成电路制造有限公司 | Method for preventing residue from forming on overlay alignment mark |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113517178A (en) | 2021-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0225026A (en) | Manufacture of semiconductor device | |
| CN111640656B (en) | Semiconductor device and method of forming the same | |
| US9171731B2 (en) | Method of forming the gate with the LELE double pattern | |
| KR20070116986A (en) | A non-critical complementary masking method for poly-1 definition in flash memory device fabrication | |
| CN110690117B (en) | Semiconductor structure and forming method thereof | |
| CN113517178B (en) | Method for preparing semiconductor structure and semiconductor structure | |
| CN116736440B (en) | Preparation process of multi-height waveguide | |
| KR100219550B1 (en) | Anti-reflective coating layer and pattern forming method using the same | |
| US6140206A (en) | Method to form shallow trench isolation structures | |
| US7541255B2 (en) | Method for manufacturing semiconductor device | |
| US6165878A (en) | Method of manufacturing semiconductor device | |
| US6171896B1 (en) | Method of forming shallow trench isolation by HDPCVD oxide | |
| KR20010064079A (en) | A method for forming alignment mark with improved alignment accuracy | |
| CN113725080B (en) | Method of forming planarization layer and pattern forming method using the same | |
| JPH0980740A (en) | Exposure mask and production of semiconductor device | |
| CN111986989A (en) | Semiconductor structure and forming method thereof | |
| EP1160843A1 (en) | Planarizing anti-reflective coating layer with improved light absorption | |
| JP2748465B2 (en) | Method for manufacturing semiconductor device | |
| TWI694520B (en) | Semiconductor substrate and method of processing the same | |
| CN111489960B (en) | Semiconductor structure and forming method thereof | |
| KR100286901B1 (en) | Shallow Trench Manufacturing Method for Isolation of Semiconductor Devices | |
| KR100325626B1 (en) | Method for forming shallow trench isolation | |
| KR100328692B1 (en) | Method for forming metal line in semiconductor device | |
| KR100475138B1 (en) | Method for Forming Semiconductor Device | |
| US20060008971A1 (en) | Method for fabricating shallow trench isolation layer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |