CN113516935A

CN113516935A - Source electrode driving circuit and detection method thereof, display device and driving method thereof

Info

Publication number: CN113516935A
Application number: CN202010272169.8A
Authority: CN
Inventors: 朱学辉; 张俊瑞; 王志东; 周丽佳; 彭析竹; 项欣; 刘小乔
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-04-09
Filing date: 2020-04-09
Publication date: 2021-10-19
Anticipated expiration: 2040-04-09
Also published as: CN113516935B

Abstract

The invention discloses a source electrode driving circuit and a detection method thereof, a display device and a driving method thereof, wherein a control circuit is configured to output a trigger signal according to signals of an enable end, a gate end, a k-th counting output end and an N-th counting output end; the data output counter is configured to enable the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generation circuit is configured to cause the plurality of generation output terminals of the signal generation circuit to sequentially output the data control signal according to the count control signals output from the 1 st count output terminal to the nth count output terminal; the data processing output circuit is configured to receive a data signal to be displayed and a data control signal, and output the data signal to be displayed to a data input terminal of the display panel through the data output terminal according to the data control signal after processing the data signal to be displayed.

Description

Source electrode driving circuit and detection method thereof, display device and driving method thereof

Technical Field

The present invention relates to the field of circuit technologies, and in particular, to a source driving circuit and a detection method thereof, and a display device and a driving method thereof.

Background

The display device comprises a display panel, a source electrode driving circuit and a grid electrode driving circuit. The display panel is provided with criss-cross grid lines, data lines, thin film transistors and pixel electrodes. The grid line is connected with the grid electrode driving circuit, the data line is connected with the source electrode driving circuit, the grid electrode of the thin film transistor is connected with the grid line, the source electrode is connected with the data line, and the drain electrode is connected with the pixel electrode. The grid driving circuit scans the grid lines line by line so as to enable the thin film transistor to be started line by line; meanwhile, the source electrode driving circuit outputs data signals to all the data lines simultaneously, the data signals are transmitted to the source electrode of the turned-on thin film transistor through the data lines and loaded onto the pixel electrode through the drain electrode of the thin film transistor, so that the pixel electrode is charged, and the display function of the display panel is further realized.

In practical applications, in order to determine the quality of the source driving circuit, the source driving circuit generally needs to be detected. However, the method of detecting the source driving circuit usually takes a long time, resulting in a waste of time.

Disclosure of Invention

The embodiment of the invention provides a source electrode driving circuit and a detection method thereof, a display device and a driving method thereof, which are used for detecting the source electrode driving circuit and reducing the time used for detection.

An embodiment of the present invention provides a source driving circuit, including: the control circuit, the data output counter, the signal generating circuit and the data processing output circuit; the data output counter is provided with a plurality of counting output ends, and the plurality of counting output ends comprise a 1 st counting output end to an Nth counting output end which are sequentially arranged; wherein N is an integer greater than 1;

the control circuit is respectively electrically connected with an enable end, a gate end, a k-th counting output end, an Nth counting output end and the data output counter, and is configured to output a trigger signal to the data output counter according to signals of the enable end, the gate end, the k-th counting output end and the Nth counting output end; wherein k is an integer and 1< k < N;

the data output counter is configured to enable the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal;

the signal generating circuit is configured to receive the count control signals output by the 1 st to nth count output terminals, and cause the plurality of generating output terminals of the signal generating circuit to sequentially output data control signals according to the count control signals output by the 1 st to nth count output terminals;

the data processing output circuit is configured to receive a data signal to be displayed and the data control signal, and output the data signal to be displayed to a data input terminal of a display panel through a data output end according to the data control signal after processing the data signal to be displayed.

Optionally, in an embodiment of the present invention, the control circuit includes: an or gate and an alternative selector;

a first input end of the OR gate is electrically connected with the enabling end, a second input end of the OR gate is electrically connected with an output end of the alternative selector, and an output end of the OR gate is electrically connected with the data output counter;

the control end of the two-choice selector is electrically connected with the gating end, the first input end of the two-choice selector is electrically connected with the Nth counting output end, and the second input end of the two-choice selector is electrically connected with the kth counting output end.

Optionally, in an embodiment of the present invention, the data output counter includes a plurality of latches connected in cascade; the output end of one latch is correspondingly and electrically connected with one counting output end;

the input end of the 1 st stage latch is electrically connected with the control circuit and is configured to receive the trigger signal; in each two adjacent stages of the latches, the input end of the latch at the next stage is electrically connected with the output end of the latch at the previous stage;

the control end of the odd-numbered stage latch is electrically connected with the first clock signal end, and the control end of the even-numbered stage latch is electrically connected with the second clock signal end.

Optionally, in an embodiment of the present invention, the signal generating circuit includes a plurality of switching circuits; one switch circuit is correspondingly and electrically connected with one generation output end; one counting output end is correspondingly and electrically connected with the control ends of at least two switch circuits;

the switch circuit is configured to output a data control signal through the electrically connected generation output according to a count control signal of the electrically connected count output.

Optionally, in an embodiment of the present invention, the plurality of switch circuits includes a 1 st switch circuit to a 2 nd switch circuit that are sequentially arranged; the nth counting output end is electrically connected with the control end of the 2N-1 th switching circuit and the control end of the 2 nth switching circuit, N is an integer and is more than or equal to 1 and less than or equal to N;

the input end of the 2n-1 switching circuit electrically connected with the odd number counting output ends is electrically connected with the third clock signal end, and the input end of the 2n switching circuit electrically connected with the odd number counting output ends is electrically connected with the second clock signal end;

the input end of the 2n-1 switch circuit electrically connected with the even number of counting output ends is electrically connected with the fourth clock signal end, and the input end of the 2n switch circuit electrically connected with the even number of counting output ends is electrically connected with the first clock signal end.

Optionally, in an embodiment of the present invention, the switching circuit includes: the circuit comprises a transmission gate, a first inverter, a switching transistor and a buffer;

the input end of the transmission gate is used as the input end of the switch circuit, the first control end of the transmission gate is electrically connected with the input end of the first phase inverter, the second control end of the transmission gate is electrically connected with the output end of the first phase inverter, and the output end of the transmission gate is electrically connected with the input end of the buffer;

the input end of the first inverter is used as the control end of the switch circuit, and the output end of the first inverter is electrically connected with the grid electrode of the switch transistor;

the source electrode of the switch transistor is electrically connected with a grounding end, and the drain electrode of the switch transistor is electrically connected with the input end of the buffer;

and the output end of the buffer is electrically connected with the corresponding generation output end.

The embodiment of the invention also provides a detection method of the source electrode driving circuit, which comprises the following steps:

in a first detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the Nth counting output end; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output by the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and the data control signal, processes the data signal to be displayed and outputs the data signal to each data input terminal of the display panel through a data output end according to the data control signal; the gating end loads a first gating signal;

in a second detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and the data control signal, processes the data signal to be displayed and outputs the data signal to a corresponding data input terminal in the display panel through a part of data output ends according to the data control signal; and the gating end loads a second gating signal.

The embodiment of the invention also provides a display device which comprises the source electrode driving circuit.

Optionally, in an embodiment of the present invention, the method further includes: a display panel and a gate driving circuit;

the display panel comprises a plurality of grid lines, a plurality of data lines and a plurality of data input terminals; wherein one of the data input terminals is electrically connected to at least one of the data lines;

the grid driving circuit is electrically connected with the grid lines respectively;

the source electrode driving circuits are respectively electrically connected with the data input terminals; wherein one of the data output terminals is electrically connected to one of the data input terminals.

The embodiment of the invention also provides a driving method of the display device, which comprises the following steps:

in a first display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the Nth counting output end; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output by the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and the data control signal, and outputs the data signal to a data input terminal of the display panel through a data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a first display mode; the gating end loads a first gating signal;

in a second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and the data control signal, and outputs the data signal to a corresponding data input terminal in the display panel through a part of data output ends according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode; and the gating end loads a second gating signal.

The invention has the following beneficial effects:

according to the source electrode driving circuit and the detection method thereof provided by the embodiment of the invention, in the first detection mode, the control circuit can output the trigger signal to the data output counter according to the signals of the enabling end, the gating end and the Nth counting output end by loading the first gating signal to the gating end; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, processes the data signal to be displayed and outputs the data signal to a data input terminal of the display panel through a data output end according to the data control signal. Therefore, each data input terminal can input a data signal, so that each data line can input the data signal, namely, a row of sub-pixels in the display panel can input the signals, and the working state of the source electrode driving circuit corresponding to each sub-pixel in the row can be detected when the signals are input.

In addition, in the second detection mode, the control circuit can output a trigger signal to the data output counter according to signals of the enable end, the strobe end and the kth counting output end by loading a second strobe signal to the strobe end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, processes the data signal to be displayed and outputs the data signal to a data input terminal of the display panel through a data output end according to the data control signal. Therefore, data signals can be input to only part of the data input terminals, so that data signals can be input to part of the data lines without inputting data signals to all the data input terminals, and then, part of sub-pixels in one row of the display panel can be switched to sub-pixels in the next row after inputting signals, so that part of sub-pixels in the next row can input signals, and the working state of the source electrode driving circuit when the corresponding row is switched with the row is detected.

In the display device and the driving method thereof provided by the embodiment of the invention, in the first display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable terminal, the gate terminal and the Nth counting output terminal; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, and outputs the display data signal to a data input terminal of the display panel through the data output end according to the data control signal after the data signal to be displayed is processed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a first display mode. This makes it possible to display the entire display area of the display panel.

In the second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, and outputs the display data signal to a corresponding data input terminal in the display panel through a part of data output ends according to the data control signal after the data signal to be displayed is processed; and the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode. This makes it possible to display a picture in a partial area in the display area of the display panel, thereby reducing power consumption.

Drawings

FIG. 1 is a schematic diagram of a source driver circuit and a display panel according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a source driver circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a switch circuit according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method for detecting a source driver circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of some signals in an embodiment of the present invention;

FIG. 6 is a timing diagram of further signals in an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 8 is a flowchart of a driving method of a display device according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1, a source driving circuit according to an embodiment of the present invention may include: a control circuit 100, a data output counter 200, a signal generation circuit 300, and a data processing output circuit 400; wherein, the data output counter 200 has a plurality of count output terminals including the 1 st count output terminal CNT-1 to the nth count output terminal CNT-N arranged in sequence; wherein N is an integer greater than 1 (in fig. 1, N ═ 44 is taken as an example);

the control circuit 100 is electrically connected to the enable terminal EN, the gate terminal CS, the kth count output terminal CNT-k, the nth count output terminal CNT-N, and the data output counter 200, respectively, and the control circuit 100 is configured to output a trigger signal to the data output counter 200 according to signals of the enable terminal EN, the gate terminal CS, the kth count output terminal CNT-k, and the nth count output terminal CNT-N; wherein k is an integer and 1< k < N; (k-8 in fig. 1 is taken as an example);

the data output counter 200 is configured to cause the 1 st to nth count output terminals CNT-N to sequentially output count control signals according to a trigger signal;

the signal generating circuit 300 is configured to receive the count control signals output from the 1 st to nth count output terminals CNT-N and cause the plurality of generating output terminals of the signal generating circuit 300 to sequentially output the data control signals according to the count control signals output from the 1 st to nth count output terminals CNT-N;

the data processing output circuit 400 is configured to receive a data signal to be displayed and a data control signal, and output the data signal to be displayed to the data input terminal of the display panel 500 through the data output terminal according to the data control signal after processing the data signal to be displayed.

The source driving circuit provided by the embodiment of the present invention may include: the control circuit, data output counter, signal generation circuit and data processing output circuit. In the first detection mode, the control circuit can output a trigger signal to the data output counter according to signals of the enable end, the strobe end and the Nth counting output end by loading a first strobe signal to the strobe end; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, processes the data signal to be displayed and outputs the data signal to a data input terminal of the display panel through a data output end according to the data control signal. Therefore, each data input terminal can input a data signal, so that each data line can input the data signal, namely, a row of sub-pixels in the display panel can input the signals, and the working state of the source electrode driving circuit corresponding to each sub-pixel in the row can be detected when the signals are input.

In addition, in the source driving circuit provided in the embodiment of the present invention, when in the second detection mode, the control circuit may output the trigger signal to the data output counter according to the signals of the enable terminal, the strobe terminal, and the kth count output terminal by loading the second strobe signal to the strobe terminal; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, processes the data signal to be displayed and outputs the data signal to a data input terminal of the display panel through a data output end according to the data control signal. Therefore, data signals can be input to only part of the data input terminals, so that data signals can be input to part of the data lines without inputting data signals to all the data input terminals, and then, part of sub-pixels in one row of the display panel can be switched to sub-pixels in the next row after inputting signals, so that part of sub-pixels in the next row can input signals, and the working state of the source electrode driving circuit when the corresponding row is switched with the row is detected.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

In particular implementation, k may be set to any one of the values 2 to N-1 in the embodiment of the present invention. For example, as shown in fig. 1 and fig. 2, N may be 44, 50, 60, 80, or the like. And k may be 8, 20, 30, 40, or the like. Of course, in practical applications, the source driving circuit is required by different display panels, and therefore, the values of N and k may be determined according to the requirements of practical applications, and are not limited herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 1 and fig. 2, the control circuit 100 may include: an or gate 110 and an alternative selector 120; wherein the content of the first and second substances,

a first input terminal of the or gate 110 is electrically connected to the enable terminal EN, a second input terminal of the or gate 110 is electrically connected to an output terminal of the one-of-two selector 120, and an output terminal of the or gate 110 is electrically connected to the data output counter 200;

the control terminal of the one-of-two selector 120 is electrically connected to the gate terminal CS, the first input terminal of the one-of-two selector 120 is electrically connected to the nth count output terminal CNT-N, and the second input terminal of the one-of-two selector 120 is electrically connected to the kth count output terminal CNT-k.

In practical implementation, in the embodiment of the present invention, the or gate 110 may enable the output terminal thereof to output a low level when the signals input to the first input terminal and the second input terminal thereof are both low levels. And, the or gate 110 may have its output terminal output a high level when a signal inputted to at least one of the first input terminal and the second input terminal thereof is a high level. It should be noted that, in practical applications, the structure and the operation principle of the or gate 110 may be substantially the same as those in the related art, and are not described herein again.

In practical implementation, in the embodiment of the present invention, as shown in fig. 1 and fig. 2, the data output counter 200 may include a plurality of latches SK-1, SK-2, … … SK-8, … … SK-N-1, SK-N connected in cascade; the output end Q of one latch SK-n is correspondingly and electrically connected with one counting output end CNT-n; and N is an integer and N is not less than 1 and not more than N. And, the input terminal D of the 1 st stage latch SK-1 is electrically connected to the control circuit 100, and is configured to receive a trigger signal, i.e., the input terminal D of the 1 st stage latch SK-1 is electrically connected to the output terminal of the or gate 110. In each two adjacent stages of latches, the input end D of the next stage of latch SK-n +1 is electrically connected with the output end Q of the previous stage of latch SK-n; the control terminal C of the odd-numbered stage latch is electrically connected to the first clock signal terminal CK1, and the control terminal C of the even-numbered stage latch is electrically connected to the second clock signal terminal CK 2.

In practical implementation, in the embodiment of the present invention, the latch may change the output terminal Q thereof to follow the input terminal D when the control terminal C thereof is at a high level, that is, the levels of the output terminal Q and the input terminal D may be the same. When the control terminal C changes from high level to low level, the output terminal Q keeps the state of the previous moment until the next time the control terminal C changes to high level. It should be noted that, in practical applications, the structure and the operation principle of the latch may be substantially the same as those in the related art, and are not described herein again.

In practical implementation, in the embodiment of the present invention, as shown in FIG. 1 and FIG. 2, the signal generating circuit 300 may include a plurality of switching circuits TK-z (z is an integer and 1. ltoreq. z.ltoreq.2N); wherein, a switch circuit is correspondingly and electrically connected with a generation output end; one counting output end is electrically connected with the control ends of at least two switch circuits correspondingly. And the switching circuit is configured to output the data control signal through the electrically connected generation output according to the count control signal of the electrically connected count output.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 1 and fig. 2, the plurality of switching circuits may include a 1 st switching circuit TK-1 to a 2N th switching circuit TK-2N arranged in sequence; wherein the Nth count output terminal CNT-N is electrically connected with the control terminal S of the 2N-1 th switching circuit TK-2N-1 and the control terminal S of the 2N th switching circuit TK-2N. And the output KO of the 2n-1 th switching circuit TK-2n-1 is electrically connected with the 2n-1 th generation output CTRL-2n-1, and the output KO of the 2 n-th switching circuit TK-2n is electrically connected with the 2 n-th generation output CTRL-2 n. And N is an integer and N is not less than 1 and not more than N.

Also, the input terminal IN of the 2n-1 st switching circuit TK-2n-1 to which the odd number of count output terminals are electrically connected is electrically connected to the third clock signal terminal CK3, and the input terminal IN of the 2 n-th switching circuit TK-2n to which the odd number of count output terminals are electrically connected is electrically connected to the second clock signal terminal CK 2. For example, the input terminal IN of the 1 st switching circuit TK-1 to which the 1 st count output terminal CNT-1 is electrically connected, the input terminal IN of the 5 th switching circuit TK-5 to which the 3 rd count output terminal CNT-3 is electrically connected, and the input terminal IN of the 9 th switching circuit TK-9 to which the 5 th count output terminal CNT-5 is electrically connected are electrically connected to the third clock signal terminal CK 3. The rest of the same principles are analogized, and are not described herein.

Also, the input terminal IN of the 2 n-th switching circuit TK-2n to which the odd-numbered count output terminals are electrically connected is electrically connected to the second clock signal terminal CK 2. For example, the input terminal IN of the 2 nd switching circuit TK-2 to which the 1 st count output terminal CNT-1 is electrically connected, the input terminal IN of the 6 th switching circuit TK-6 to which the 3 rd count output terminal CNT-3 is electrically connected, and the input terminal IN of the 10 th switching circuit TK-10 to which the 5 th count output terminal CNT-5 is electrically connected are electrically connected to the second clock signal terminal CK 2. The rest of the same principles are analogized, and are not described herein.

And, the input terminal IN of the 2n-1 th switching circuit TK-2n-1, to which the even number of count output terminals are electrically connected, is electrically connected to the fourth clock signal terminal CK 4. For example, the input terminal IN of the 3 rd switching circuit TK-3 to which the 2 nd count output terminal CNT-2 is electrically connected, the input terminal IN of the 7 th switching circuit TK-7 to which the 4 th count output terminal CNT-4 is electrically connected, and the input terminal IN of the 11 th switching circuit TK-11 to which the 6 th count output terminal CNT-6 is electrically connected are electrically connected to the fourth clock signal terminal CK 4. The rest of the same principles are analogized, and are not described herein.

Also, the input terminal IN of the 2 n-th switching circuit TK-2n to which the even-numbered count output terminals are electrically connected is electrically connected to the first clock signal terminal CK 1. For example, the input terminal IN of the 4 th switching circuit TK-4 to which the 2 nd count output terminal CNT-2 is electrically connected, the input terminal IN of the 8 th switching circuit TK-8 to which the 4 th count output terminal CNT-4 is electrically connected, and the input terminal IN of the 12 th switching circuit TK-12 to which the 6 th count output terminal CNT-6 is electrically connected are electrically connected to the first clock signal terminal CK 1. The rest of the same principles are analogized, and are not described herein.

In practical implementation, in the embodiment of the invention, as shown in fig. 2 and 3, the switching circuit TK-z (z is an integer and 1 ≦ z ≦ 2N) may include: a transmission gate TM, a first inverter N1, a switching transistor M0, and a buffer H0; the input end of the transmission gate TM is used as the input end of the switch circuit (i.e., the input end of the transmission gate TM is electrically connected to the input end IN of the switch circuit), the first control end of the transmission gate TM is electrically connected to the input end of the first inverter N1, the second control end of the transmission gate TM is electrically connected to the output end of the first inverter N1, and the output end of the transmission gate TM is electrically connected to the input end of the buffer H0. The input terminal of the first inverter N1 serves as a control terminal of the switch circuit (i.e., the input terminal of the first inverter N1 is electrically connected to the control terminal S of the switch circuit), and the output terminal of the first inverter N1 is electrically connected to the gate of the switching transistor M0. The source of the switching transistor M0 is electrically connected to the ground GND, and the drain of the switching transistor M0 is electrically connected to the input terminal of the buffer H0. The output terminal of the buffer H0 is electrically connected to the corresponding generation output terminal, i.e., the output terminal of the buffer H0 serves as the output terminal KO of the switch circuit.

In practical implementation, in the embodiment of the present invention, the transmission gate TM outputs the signal at its input end through its output end when its first input end is at low level and its second input end is at high level. It should be noted that, in practical applications, the structure and the operation principle of the transmission gate TM may be substantially the same as those in the related art, and are not described herein again.

In practical implementation, in the embodiment of the present invention, the first inverter N1 may invert the signal input to its input terminal and output the inverted signal through its output terminal. It should be noted that, in practical applications, the structure and the operation principle of the first inverter N1 may be substantially the same as those of the inverters in the related art, and are not described herein again.

In particular implementations, in embodiments of the present invention, buffer H0 may include an even number of second inverters. Wherein the even number of second inverters are sequentially arranged in series. Illustratively, as shown in FIG. 3, the buffer H0 may include 2 second inverters N2-1, N2-2. Wherein, the input end of the second inverter N2-1 is electrically connected with the output end of the transmission gate TM, the output end of the second inverter N2-1 is electrically connected with the input end of the second inverter N2-2, and the output end of the second inverter N2-1 is used as the output end of the buffer H0, namely, the output end of the second inverter N2-2 is electrically connected with the output end KO of the switch circuit TK-z.

The foregoing is merely an example of the specific structure of the source driving circuit provided in the embodiment of the present disclosure, and in the specific implementation, the specific structure is not limited to the structure provided in the embodiment of the present disclosure, and may be other structures known to those skilled in the art, and is not limited herein.

Based on the same inventive concept, an embodiment of the present invention further provides a method for detecting the source driving circuit, as shown in fig. 4, the method may include the following steps:

s401, in a first detection mode, a control circuit outputs a trigger signal to a data output counter according to signals of an enable end, a gate end and an Nth counting output end; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, processes the data signal to be displayed and outputs the processed data signal to each data input terminal of the display panel through the data output end according to the data control signal; the gating end loads a first gating signal;

s402, in a second detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, processes the data signal to be displayed and outputs the processed data signal to a corresponding data input terminal in the display panel through a part of data output ends according to the data control signal; wherein the gating end loads the second gating signal.

The following describes a method for detecting the source driving circuit according to an embodiment of the present invention with reference to timing diagrams shown in fig. 1, fig. 2, fig. 5, and fig. 6. In this case, N-44 and k-8 are taken as examples. Wherein CK1 represents a signal CK1 of the first clock terminal CK1, CK2 represents a signal CK2 of the second clock terminal CK2, CK3 represents a signal CK3 of the third clock terminal CK3, CK4 represents a signal CK4 of the fourth clock terminal CK4, EN represents a signal of the enable terminal EN, CNT-1 to CNT-N represent count control signals of the 1 st to nth count output terminals CNT-1 to CNT-N, and CTRL-1 to CTRL-2N represent data control signals of the 1 st to 2 nth generation output terminals CTRL-1 to CTRL-2N.

With reference to fig. 1, fig. 2 and fig. 5, in the first detection mode, the method for detecting the source driving circuit according to the embodiment of the present invention may include the following steps:

in the first detection mode, in the TF0 phase, the gate CS is applied with the first gate signal of low level, so that the two-select selector 120 inputs the signal of the 44 th count output terminal CNT-44 to the second input terminal of the or gate 110, so that the or gate 110 inputs the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the second input terminal thereof and the signal of the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

Also, the count control signal CNT-1 of the 1 st count output terminal CNT-1 is input to the input terminal D of the 2 nd stage latch SK-2, and the 2 nd stage latch SK-2 makes the 2 nd count output terminal CNT-2 output the count control signal CNT-2 under the control of the signal CK2 of the second clock signal terminal CK 2. The input terminal IN of the 3 rd switching circuit TK-3 receives a signal CK4 of the fourth clock signal terminal CK4, and the 3 rd switching circuit TK-3 outputs a high-level signal of the fourth clock signal terminal CK4 to the 3 rd generation output terminal CTRL-3 under the control of a count control signal CNT-2 output from a 2 nd count output terminal CNT-2, so that the 3 rd generation output terminal CTRL-3 outputs a data control signal CTRL-3. And the input terminal IN of the 4 th switching circuit TK-4 receives the signal CK1 of the first clock signal terminal CK1, and the 4 th switching circuit TK-4 outputs a high-level signal of the first clock signal terminal CK1 to the 4 th generation output terminal CTRL-4 under the control of the count control signal CNT-2 output from the 2 nd count output terminal CNT-2, so that the 4 th generation output terminal CTRL-4 outputs the data control signal CTRL-4.

The rest of the same principles are analogized in turn, and are not described herein.

The count control signal CNT-43 of the 43 th count output terminal CNT-43 is input to the input terminal D of the 44 th stage latch SK-44, and the 44 th stage latch SK-44 causes the 44 th count output terminal CNT-44 to output the count control signal CNT-44 under the control of the signal CK2 of the second clock signal terminal CK 2. The input terminal IN of the 87 th switching circuit TK-87 receives the signal CK4 of the fourth clock signal terminal CK4, and the 87 th switching circuit TK-87 outputs a high-level signal of the fourth clock signal terminal CK4 to the 87 th generation output terminal CTRL-87 under the control of the count control signal CNT-44 output from the 44 th count output terminal CNT-44, so that the 87 th generation output terminal CTRL-87 outputs the data control signal CTRL-87. And the input terminal IN of the 88 th switching circuit TK-88 receives the signal CK1 of the first clock signal terminal CK1, and the 88 th switching circuit TK-88 outputs a signal of a high level of the first clock signal terminal CK1 to the 88 th generation output terminal CTRL-88 under the control of the count control signal CNT-44 output from the 44 th count output terminal CNT-44, so that the 88 th generation output terminal CTRL-88 can output the data control signal CTRL-88.

The data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-88, and outputs the data signal to be displayed to each data input terminal 540 of the display panel 500 through the data output terminals CO-1 to CO-88 according to the data control signals ctrl-1 to ctrl-88 after the data signal to be displayed is processed. In this way, signals can be respectively input to each sub-pixel in a row of sub-pixels in the display panel 500, so that the working state of the source driving circuit when the signals are input to the sub-pixels in the row can be detected.

With reference to fig. 1, fig. 2 and fig. 6, in the second detection mode, the method for detecting the source driving circuit according to the embodiment of the present invention may include the following steps:

in the second detection mode, in the TF1 phase, the strobe terminal CS is applied with the second strobe signal of high level, so that the two-select selector 120 inputs the signal of the 8 th count output terminal CNT-8 to the second input terminal of the or gate 110, so that the or gate 110 inputs the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the second input terminal thereof and the signal of the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The count control signal CNT-7 of the 7 th count output terminal CNT-7 is input to the input terminal D of the 8 th stage latch SK-8, and the 8 th stage latch SK-8 causes the 8 th count output terminal CNT-8 to output the count control signal CNT-8 under the control of the signal CK2 of the second clock signal terminal CK 2. The input terminal IN of the 15 th switching circuit TK-15 receives the signal CK4 of the fourth clock signal terminal CK4, and the 15 th switching circuit TK-15 outputs a high-level signal of the fourth clock signal terminal CK4 to the 15 th generation output terminal CTRL-15 under the control of the count control signal CNT-8 output from the 8 th count output terminal CNT-8, so that the 15 th generation output terminal CTRL-15 outputs the data control signal CTRL-15. And the input terminal IN of the 16 th switching circuit TK-16 receives the signal CK1 of the first clock signal terminal CK1, and the 16 th switching circuit TK-16 outputs a signal of a high level of the first clock signal terminal CK1 to the 16 th generation output terminal CTRL-16 under the control of the count control signal CNT-8 output from the 8 th count output terminal CNT-8, so that the 16 th generation output terminal CTRL-16 outputs the data control signal CTRL-16.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and after processing the data signal to be displayed, outputs the data signal to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 according to the data control signals ctrl-1 to ctrl-16, so that signals can be input to a part of the sub-pixels in one row of the sub-pixels in the display panel 500.

After that, the TF2 stage is entered. In the TF2 phase, the gate CS is applied with the second gate signal of high level, so that the two-select selector 120 inputs the signal of the 8 th count output terminal CNT-8 to the second input terminal of the or gate 110, so that the or gate 110 inputs the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the second input terminal thereof and the signal of the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK1 to the 1 st count output terminal CNT-1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and after the data signal to be displayed is processed, outputs the data signal to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 according to the data control signals ctrl-1 to ctrl-16, so as to input signals to a part of subpixels in another row of subpixels in the display panel 500.

In this way, the source driving circuit can be switched to the sub-pixels in the next row after inputting signals to some sub-pixels in one row of the display panel 500, so that some sub-pixels in the next row can input signals, and thus the operating state of the source driving circuit when switching between the corresponding row and the corresponding row can be detected.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the source electrode driving circuit. The principle of the display device to solve the problem is similar to the source driving circuit, so the implementation of the display device can be referred to the implementation of the source driving circuit, and repeated details are not repeated herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1 and fig. 7, the display device may further include: a display panel 500 and a gate driving circuit 530. The display panel 500 includes a plurality of gate lines 520, a plurality of data lines 510, and a plurality of data input terminals 540. The gate driving circuits 530 are electrically connected to the gate lines 520, respectively. The source driver circuits 550 are electrically connected to the data input terminals 540, respectively.

The display panel 500 has a plurality of pixel units, and each pixel unit has a plurality of sub-pixels. Such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Illustratively, a thin film transistor and a pixel electrode are provided in the sub-pixel. The grid line is connected with the grid electrode driving circuit, the data line is connected with the source electrode driving circuit, the grid electrode of the thin film transistor is connected with the grid line, the source electrode is connected with the data line, and the drain electrode is connected with the pixel electrode. Illustratively, the gate driving circuit scans the gate lines line by line to turn on the thin film transistors line by line; meanwhile, the source electrode driving circuit outputs data signals to all the data lines simultaneously, the data signals are transmitted to the source electrode of the turned-on thin film transistor through the data lines and loaded onto the pixel electrode through the drain electrode of the thin film transistor, so that the pixel electrode is charged, and the display function of the display panel is further realized.

In particular, in the embodiment of the present invention, one data input terminal may be electrically connected to at least one data line, and one data output terminal may be electrically connected to one data input terminal. Illustratively, as shown in fig. 7, one data input terminal may be electrically connected to one data line pair, and one data output terminal may be electrically connected to one data input terminal.

It should be noted that, for the structure of the source driving circuit in the display device in the embodiment of the present invention, reference may be made to the above description, which is not described herein again.

In specific implementation, in the embodiment of the present invention, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a display device, as shown in fig. 8, which may include the following steps:

s810, in a first display mode, the control circuit outputs a trigger signal to the data output counter according to signals of an enable end, a gate end and an Nth counting output end; the data output counter enables the 1 st counting output end to the Nth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the Nth counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, and outputs the display data signal to a data input terminal of the display panel through the data output end according to the data control signal after the data signal to be displayed is processed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a first display mode; the gating end loads a first gating signal;

s820, in the second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enable end, the gate end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signal; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the k counting output end; the data processing output circuit receives a data signal to be displayed and a data control signal, and outputs the display data signal to a corresponding data input terminal in the display panel through a part of data output ends according to the data control signal after the data signal to be displayed is processed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode; wherein the gating end loads the second gating signal.

It should be noted that the sequence of step S810 and step S820 is not distinguished. In practical applications, step S810 may be located before step S820, or step S810 may be located after step S820, which is not limited herein.

In a specific implementation, in step S810, the entire display area of the display panel 500 may be displayed with a screen. In step S820, a partial area in the display area of the display panel 500 may be caused to display a screen, so that power consumption may be reduced.

The following describes a driving method of the display device according to an embodiment of the present invention with reference to timing charts shown in fig. 1, fig. 2, fig. 5, and fig. 6. In this case, N-44 and k-8 are taken as examples.

With reference to fig. 1, fig. 2 and fig. 5, in the first display mode, the method for driving the display device according to the embodiment of the present invention may include the following steps:

in the first display mode, the gate terminal CS is applied with the first gate signal of the low level during the TF0 phase, so that the one-out-of-two selector 120 inputs the signal of the 44 th count output terminal CNT-44 to the second input terminal of the or gate 110.

This enables the or gate 110 to input a trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the signals of the second input terminal and the enable terminal EN thereof, and the 1 st stage latch SK-1 enables the 1 st count output terminal CNT-1 to output a corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The data processing output circuit 400 receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to each data input terminal of the display panel 500 through the data output terminal according to the data control signal. In addition, the gate driving circuit loads a corresponding signal to the gate line to turn on the thin film transistor in each sub-pixel in the row, so that the drain of the thin film transistor is loaded onto the pixel electrode to charge the pixel electrode, and further, all the sub-pixels in the row of the display panel 500 are charged. After each row of sub-pixels in the display panel 500 is charged, the entire display area of the display panel 500 can be displayed.

As shown in fig. 1, fig. 2 and fig. 6, in the second display mode, the method for driving the display device according to the embodiment of the present invention may include the following steps:

in the second display mode, in the TF1 phase, the strobe terminal CS is applied with the second strobe signal of high level, so that the two-select selector 120 inputs the signal of the 8 th count output terminal CNT-8 to the second input terminal of the or gate 110, so that the or gate 110 inputs the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the second input terminal thereof and the signal of the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and outputs the data signal to be displayed to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 according to the data control signals ctrl-1 to ctrl-16 after the data signal to be displayed is processed. And, the gate driving circuit loads a corresponding signal to the gate line to turn on the thin film transistor in each sub-pixel in the row, so that the drain of the thin film transistor is loaded onto the pixel electrode to charge the pixel electrode, and further, part of the sub-pixels in one row of the display panel 500 are charged to display part of the area in the display area of the display panel 500.

The data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and outputs the data signal to be displayed to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 according to the data control signals ctrl-1 to ctrl-16 after the data signal to be displayed is processed. And, the gate driving circuit loads a corresponding signal to the gate line to turn on the thin film transistor in each sub-pixel in the row, so that the drain of the thin film transistor is loaded onto the pixel electrode to charge the pixel electrode, and further charge a part of sub-pixels in another row of the display panel 500. After the charging of part of the sub-pixels in all the rows of the display panel 500 is completed, part of the area in the display area of the display panel 500 may be displayed, so that power consumption may be reduced.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A source driver circuit, comprising: the control circuit, the data output counter, the signal generating circuit and the data processing output circuit; the data output counter is provided with a plurality of counting output ends, and the plurality of counting output ends comprise a 1 st counting output end to an Nth counting output end which are sequentially arranged; wherein N is an integer greater than 1;

2. The source driver circuit of claim 1, wherein the control circuit comprises: an or gate and an alternative selector;

3. The source drive circuit of claim 1, wherein the data output counter comprises a plurality of latches in cascade; the output end of one latch is correspondingly and electrically connected with one counting output end;

4. The source driver circuit according to any one of claims 1 to 3, wherein the signal generation circuit includes a plurality of switch circuits; one switch circuit is correspondingly and electrically connected with one generation output end; one counting output end is correspondingly and electrically connected with the control ends of at least two switch circuits;

5. The source driver circuit according to claim 4, wherein the plurality of switch circuits includes 1 st to 2 nth switch circuits arranged in sequence; the nth counting output end is electrically connected with the control end of the 2N-1 th switching circuit and the control end of the 2 nth switching circuit, N is an integer and is more than or equal to 1 and less than or equal to N;

6. The source drive circuit of claim 5, wherein the switching circuit comprises: the circuit comprises a transmission gate, a first inverter, a switching transistor and a buffer;

7. A method for detecting a source driving circuit according to any one of claims 1 to 6, comprising:

8. A display device comprising the source driver circuit according to any one of claims 1 to 6.

9. The display device of claim 8, further comprising: a display panel and a gate driving circuit;

10. A driving method of a display device according to claim 8 or 9, comprising: