CN113515184A - B code decoding and time synchronization method with reduced cost - Google Patents
B code decoding and time synchronization method with reduced cost Download PDFInfo
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- CN113515184A CN113515184A CN202110741496.8A CN202110741496A CN113515184A CN 113515184 A CN113515184 A CN 113515184A CN 202110741496 A CN202110741496 A CN 202110741496A CN 113515184 A CN113515184 A CN 113515184A
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Abstract
The invention relates to a cost-reducing B code decoding and time setting method, which is based on a cost-reducing B code decoding and time setting system.A GD32 single chip microcomputer is respectively connected with a CPU through a UART serial port and GPIO pins; the method comprises the steps of 1 to 6, wherein in the step 5, the GD32 single chip microcomputer sends the current second time to the CPU through the UART serial port, and the CPU does not immediately display the current second time; in step 6, after capturing the rising edge of the pulse per second signal at the current second time, the GD32 single chip microcomputer sends the rising edge to the CPU through the GPIO pin, and the CPU immediately displays the current second time after receiving the rising edge of the pulse per second signal; the whole structure is ingenious and reasonable in design, debugging is convenient, hardware cost is low, on one hand, the occupied area of a PCB is greatly reduced, and then the production and design cost of the PCB is reduced, and on the other hand, the power consumption of the GD32 single chip microcomputer is low, and extra heat dissipation treatment is not needed; and the time synchronization precision can be improved while the B code source can be rapidly decoded.
Description
Technical Field
The present invention relates to the field of B-code decoding and time synchronization technology, and more particularly, to a cost-reducing B-code decoding and time synchronization method.
Background
The IRIG time code sequence is a time information transmission system proposed and commonly used by the range instrument group (IRIG) under the U.S. department of defense. The time code sequence is divided into G, A, B, E, H, D coding formats, the most widely used is IRIG-B format, which is called B code for short, and the outstanding advantage is that the time synchronization signal and time code information such as second, minute, hour, day and the like are loaded into a signal carrier with the frequency of 1 kHz.
The IRIG-B signal must now be decoded and identified for pulse width detection and quickly uploaded to the CPU 26 using the decoding interval for synchronous timing. But the current time is provided after the "on time" signal of the B code, and there is a delay no matter how fast the decoding and transmission are. For example, as shown in fig. 1, the existing time synchronization method is generally as follows: the B code source 21 of the GPS is sent to the CPU 26 after passing through the RS485 chip 22, the FPGA chip 23, the hundred mega PHY chip 24, and the network chip 25 in sequence, which has the following disadvantages:
1. the costs of the FPGA chip 23, the hundred mega PHY chip 24, and the network chip 25 are high;
2. the FPGA chip 23, the hundred mega PHY chip 24 and the network chip 25 occupy a large area of the PCB, so that the production and design costs of the PCB are increased;
3. the power consumption of the FPGA chip 23, the hundred mega PHY chip 24, and the network chip 25 is large, and a large amount of power consumption and heat are easily generated, so that additional heat dissipation processing is required;
4. the whole structure is complex, and the debugging difficulty is high;
therefore, in the present patent application, the applicant elaborately researched a method for decoding and timing B codes with reduced cost to solve the above problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention mainly aims to provide a cost-reducing B code decoding and time synchronization method which has the advantages of ingenious and reasonable overall structure design, convenience in debugging and lower hardware cost, on one hand, the occupied area of a PCB is greatly reduced, and then the production and design cost of the PCB is reduced, and on the other hand, the power consumption of a GD32 single chip microcomputer is low, and extra heat dissipation treatment is not needed; and the time synchronization precision can be improved while the B code source can be rapidly decoded.
In order to achieve the purpose, the invention adopts the following technical scheme:
a reduced cost type B code decoding and time setting method is based on a reduced cost type B code decoding and time setting system, wherein the reduced cost type B code decoding and time setting system comprises a GD32 single chip microcomputer, a CPU and an RS485 chip used for receiving RS485 signals sent by a B code source from a GPS;
the output end of the RS485 chip is connected with the GD32 single chip microcomputer and is used for converting the received RS485 signal into a TTL signal which can be identified by the GD32 single chip microcomputer and sending the TTL signal to the GD32 single chip microcomputer;
the GD32 singlechip is provided with a UART serial port with a baud rate of 921600bps and a GPIO pin with rising edge interrupt capture enabling, and the GD32 singlechip is respectively connected with the CPU through the UART serial port and the GPIO pin;
the method comprises the following steps:
step 1: the GD32 singlechip captures the B code signal;
step 2: the GD32 singlechip decodes the captured B code signal;
and step 3: the GD32 singlechip acquires the current first time by decoding the B code signal;
and 4, step 4: the single chip microcomputer GD32 increases the current first time by preset seconds to obtain a current second time;
and 5: the GD32 single-chip microcomputer sends the current second time to the CPU through the UART serial port, and the CPU temporarily stores the current second time after receiving the current second time and does not immediately display the current second time;
step 6: after capturing the rising edge of the pulse per second signal at the current second time, the GD32 single chip microcomputer sends the captured rising edge of the pulse per second signal corresponding to the current second time to the CPU through the GPIO pin, and the CPU immediately displays the current second time after receiving the rising edge of the pulse per second signal.
As a preferable scheme, in step 4, the preset second is 1 second.
Preferably, in step 3, the GD32 single-chip microcomputer also acquires leap second information by decoding the B code signal.
As a preferable scheme, in step 4, the GD32 single-chip microcomputer firstly determines the time to come after the preset second by leap second information, and then increases the current first time by the preset second to obtain the current second time.
Compared with the prior art, the invention has obvious advantages and beneficial effects, particularly: the GD32 single chip microcomputer is connected with the CPU through the UART serial port and the GPIO pin, the whole structure is skillfully and reasonably designed, the debugging is convenient, the hardware cost is low, on one hand, the occupied area of a PCB is greatly reduced, and then the production and design cost of the PCB is reduced, on the other hand, the GD32 single chip microcomputer is low in power consumption, and extra heat dissipation treatment is not needed; and the time synchronization precision can be improved while the B code source can be rapidly decoded.
To more clearly illustrate the structural features and effects of the present invention, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
Drawings
FIG. 1 is a general schematic block diagram of the prior art;
FIG. 2 is a schematic block diagram of a preferred embodiment of the present invention;
FIG. 3 is a flow chart of the preferred embodiment of the present invention.
The reference numbers illustrate:
11. b code source 12, RS485 chip
13. GD32 single-chip microcomputer 14 and CPU
21. B code source 22 and RS485 chip
23. FPGA chip 24, hundred mega PHY chip
25. Network chip 26, CPU.
Detailed Description
The invention is further described with reference to the following detailed description and accompanying drawings.
As shown in fig. 2 and fig. 3, a method for decoding and time-setting a reduced-cost B code is based on a system for decoding and time-setting a reduced-cost B code, wherein the system for decoding and time-setting a reduced-cost B code comprises a GD32 single chip 13, a CPU, and an RS485 chip 12 for receiving an RS485 signal sent by a B code source 11 from a GPS;
the output end of the RS485 chip 12 is connected with the GD32 single chip microcomputer 13 and is used for converting the received RS485 signal into a TTL signal which can be identified by the GD32 single chip microcomputer 13 and sending the TTL signal to the GD32 single chip microcomputer 13;
the GD32 singlechip 13 is provided with a UART serial port with a baud rate of 921600bps and a GPIO pin with rising edge interrupt capture enabling, and the GD32 singlechip 13 is respectively connected with the CPU 14 through the UART serial port and the GPIO pin; in this embodiment, the RS485 chip 12 is an ISL3152EIBZ of InterSil company, and the GD32 single chip microcomputer 13 is a GD32 single chip microcomputer 13 with a main frequency of 108MHz of GD32F103C8T6 of beijing mega innovative company. It should be noted that the present embodiment is not limited to the RS485 chip 12 and the GD32 single chip microcomputer 13 of the above models, and may also be an RS485 chip 12 and a GD32 single chip microcomputer 13 of other models, which is not limited herein. The method comprises the following steps:
step 1: the GD32 singlechip 13 captures B code signals, namely receives two continuous P code sources;
step 2: the GD32 singlechip 13 decodes the captured B code signal;
and step 3: the GD32 singlechip 13 obtains the current first time and leap second information by decoding the B code signal;
and 4, step 4: the GD32 single-chip microcomputer 13 judges the time to be arrived after the preset second through leap second information, and then increases the current first time by the preset second to obtain the current second time; in this embodiment, the preset second is 1 second, but may be other times, and is not limited herein. The GD32 single-chip microcomputer 13 decodes the 60-code source to the 68-code source to obtain a positive and negative leap second advance notice, and then obtains a preset second to be increased.
The following examples illustrate the general case:
the current first time is XX years X month X day 08: 59: 58, no leap second identification is received, the current second time is shown as XX years, X month X day 08: 59: 59;
if the current first time is XX year X month X day 08: 59: 58 and the negative leap second announcement flag is received, the current second time is displayed as XX years, X month, X day 09: 00: 00; it should be noted that, when the negative leap second announcement flag indicates that the second value is 59 short;
if the current first time is XX year X month X day 08: 59: 59 and receiving the leap second preview flag, the current second time is displayed as XX year, X month, X day 08: 59: 60, adding a solvent to the mixture; it should be noted that the second value of 60 is only present when the positive leap second forenotice is received.
And 5: the GD32 single-chip microcomputer 13 sends the current second time to the CPU 14 through the UART serial port, and the CPU 14 temporarily stores the current second time after receiving the current second time and does not immediately display the current second time;
step 6: after capturing the rising edge of the pulse per second signal at the current second time, the GD32 single chip microcomputer 13 sends the captured rising edge of the pulse per second signal corresponding to the current second time to the CPU 14 through the GPIO pin, and after receiving the rising edge of the pulse per second signal, the CPU 14 immediately enters an interrupt program to modify the current second time into the system time of the CPU 14, that is, the current second time is immediately displayed, so that the system time of the CPU 14 is synchronized with the time of the GPS, and accurate time synchronization is realized.
At present, as data transmission requires time no matter how fast, there are inaccurate places in time, namely, synchronization is difficult to realize. In the embodiment, the GPIO pin is introduced to output the pulse per second, and the generated timing error is an error of a rising edge of the pulse per second, which can be almost ignored. Therefore, the embodiment can realize accurate time setting.
In this embodiment, the GD32 single-chip microcomputer 13 decodes the 1 to 58 code sources to obtain the current time; b code decoding is realized through the GD32 single-chip microcomputer 13, so that the hardware cost is low, and the software portability is high; moreover, the power consumption of the GD32 singlechip 13 is within 100mW, and extra heat dissipation treatment is not needed.
In the prior art, the logic programming workload of the FPGA chip 23 is large, the code is difficult to transplant, and once the peripheral device stops production and is disconnected, the logic code needs to be modified and developed again. However, in this embodiment, the decoding program of the GD32 single chip microcomputer 13 and the time synchronization program of the CPU 14 are written in C language, and the software is easily migrated to other single chip microcomputers and the CPU 14.
Next, step 5 and step 6 will be roughly described, taking the preset second as 1 second as an example:
assuming that the current first time obtained by decoding by the GD32 single-chip microcomputer 13 is 1/second at 1 month/1 day in 2021 year and no leap second preview flag is received, the current second time actually uploaded to the CPU 14 is 1/2/second at 1 month/1 day in 2021 year, and the CPU 14 does not immediately display the second time after receiving the time of 1/2/second at 1 month/1 day in 2021 year, but immediately displays the second time after waiting for the rising edge of the second pulse signal corresponding to the current second time sent by the GPIO pin of the GD32 single-chip microcomputer 13.
The design key points of the invention lie in that the GD32 single chip microcomputer is respectively connected with the CPU through the UART serial port and the GPIO pin, the whole structure is skillfully and reasonably designed, the debugging is convenient, the hardware cost is lower, on one hand, the occupation of the area of the PCB is greatly reduced, and then the production and design cost of the PCB is reduced, on the other hand, the GD32 single chip microcomputer has low power consumption, and does not need extra heat dissipation treatment; and the time synchronization precision can be improved while the B code source can be rapidly decoded.
Claims (4)
1. A method for decoding and timing a B code with reduced cost is characterized in that: the system is based on a cost-reducing B code decoding and time setting system, wherein the cost-reducing B code decoding and time setting system comprises a GD32 single chip microcomputer, a CPU and an RS485 chip used for receiving an RS485 signal sent by a B code source from a GPS;
the output end of the RS485 chip is connected with the GD32 single chip microcomputer and is used for converting the received RS485 signal into a TTL signal which can be identified by the GD32 single chip microcomputer and sending the TTL signal to the GD32 single chip microcomputer;
the GD32 singlechip is provided with a UART serial port with a baud rate of 921600bps and a GPIO pin with rising edge interrupt capture enabling, and the GD32 singlechip is respectively connected with the CPU through the UART serial port and the GPIO pin;
the method comprises the following steps:
step 1: the GD32 singlechip captures the B code signal;
step 2: the GD32 singlechip decodes the captured B code signal;
and step 3: the GD32 singlechip acquires the current first time by decoding the B code signal;
and 4, step 4: the single chip microcomputer GD32 increases the current first time by preset seconds to obtain a current second time;
and 5: the GD32 single-chip microcomputer sends the current second time to the CPU through the UART serial port, and the CPU temporarily stores the current second time after receiving the current second time and does not immediately display the current second time;
step 6: after capturing the rising edge of the pulse per second signal at the current second time, the GD32 single chip microcomputer sends the captured rising edge of the pulse per second signal corresponding to the current second time to the CPU through the GPIO pin, and the CPU immediately displays the current second time after receiving the rising edge of the pulse per second signal.
2. The method for decoding and synchronizing B-code according to claim 1, wherein: in step 4, the preset second is 1 second.
3. The method for decoding and synchronizing B-code according to claim 1, wherein: in step 3, the GD32 single-chip microcomputer also acquires leap second information by decoding the B code signal.
4. The method of claim 3, wherein the method further comprises: in step 4, the GD32 single-chip microcomputer determines the time to be reached after the preset second through leap second information, and then increases the current first time by the preset second to obtain the current second time.
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Cited By (1)
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| CN114415780A (en) * | 2021-12-30 | 2022-04-29 | 研祥智慧物联科技有限公司 | IRIG-B code-based time synchronization method and device |
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Application publication date: 20211019 |