CN113506769A - Method for forming rear-end structure containing MIM capacitor - Google Patents
Method for forming rear-end structure containing MIM capacitor Download PDFInfo
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- CN113506769A CN113506769A CN202110718860.9A CN202110718860A CN113506769A CN 113506769 A CN113506769 A CN 113506769A CN 202110718860 A CN202110718860 A CN 202110718860A CN 113506769 A CN113506769 A CN 113506769A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Abstract
The application discloses a forming method of a rear end structure comprising an MIM capacitor, wherein the MIM capacitor is of a step type, the MIM capacitor is formed in a second interlayer dielectric, the second interlayer dielectric is formed on a dielectric layer, the dielectric layer is formed on a first interlayer dielectric, a metal connecting line is formed in the first interlayer dielectric, the height of the interlayer dielectric above a second electrode of the MIM capacitor is higher than that of the interlayer dielectric above a first electrode, and the height of the interlayer dielectric above the first electrode is higher than that of the interlayer dielectric above the metal connecting line, and the method comprises the following steps: etching to expose the first electrode of the first target area, the second electrode of the second target area and the metal connecting line of the third target area, forming a first through hole in the first target area, forming a second through hole in the second target area and forming a third through hole in the third target area; forming a metal layer, wherein the metal layer fills the first through hole, the second through hole and the third through hole; and carrying out planarization treatment.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a forming method of a rear-end structure comprising an MIM capacitor.
Background
Capacitive elements are often used in integrated circuits such as radio frequency, monolithic microwave, etc. as electronic passive devices. Common capacitor elements include metal-oxide-semiconductor (MOS) capacitors, PN junction (positive negative junction) capacitors, metal-insulator-metal (MIM) capacitors, and the like.
The MIM capacitor can provide electrical characteristics superior to MOS capacitors and PN junction capacitors in some special applications, because the MOS capacitors and the PN junction capacitors are limited by their structures, and when operating, the electrodes easily generate a hole layer, which reduces the frequency characteristics, and the MIM capacitor can provide better frequency and temperature-related characteristics. In addition, MIM capacitors can be formed in the interlayer metal and metal interconnect processes during semiconductor fabrication, which also reduces the difficulty and complexity of integration with front-end processes in integrated circuit fabrication.
Referring to fig. 1 to 2, schematic diagrams illustrating formation of a backend structure including a MIM capacitor according to the related art are shown. As shown in fig. 1, a metal connection 111 is formed in a first interlayer dielectric (ILD) 110, a dielectric layer 120 is formed on the first interlayer dielectric 110, a step-type second interlayer dielectric 130 is formed on the dielectric layer 120, and a step-type MIM capacitor (including a first electrode 131, a second electrode 132, and a capacitor dielectric layer 133 covering the second electrode 132) is formed in the second interlayer dielectric 130.
In the subsequent process, a contact via hole for leading out the first electrode 131, the second electrode 132 and the metal connection line 111 needs to be formed, before this, the third dielectric layer 130 needs to be planarized, fig. 2 shows a schematic cross-sectional view of the planarized third dielectric layer 130, and in the subsequent process, the first electrode 131, the second electrode 132 and the metal connection line 111 need to be opened by etching. However, since the thicknesses of the dielectrics above the first electrode 131, the second electrode 132 and the metal line 111 have a step difference (i.e., h1 < h2 < h3), in the subsequent etching process, different processes need to be designed to sequentially open each metal layer according to different film thicknesses above each metal layer, which is complex in process and high in manufacturing cost.
Disclosure of Invention
The application provides a method for forming a back-end structure comprising an MIM capacitor, which can solve the problem of complex process caused by large step difference in the process of opening a metal film in the method for forming the back-end structure comprising the step-type MIM capacitor provided in the related art.
In one aspect, an embodiment of the present application provides a method for forming a backend structure including an MIM capacitor, where the MIM capacitor is a step type, and includes a first electrode, a capacitor dielectric, and a second electrode;
the MIM capacitor is formed in a second interlayer dielectric, the second interlayer dielectric is formed on the dielectric layer, the dielectric layer is formed on the first interlayer dielectric, a metal connecting line is formed in the first interlayer dielectric, the height of the second interlayer dielectric above the second electrode is higher than that of the second interlayer dielectric above the first electrode, and the height of the second interlayer dielectric above the first electrode is higher than that of the second interlayer dielectric above the metal connecting line;
the method comprises the following steps:
etching to expose a first electrode of a first target area, a second electrode of a second target area and a metal connecting wire of a third target area, forming a first through hole in the first target area, forming a second through hole in the second target area and forming a third through hole in the third target area;
forming a metal layer filling the first through hole, the second through hole and the third through hole;
and carrying out planarization treatment, wherein a first contact through hole is formed in the metal layer in the first through hole, a second contact through hole is formed in the metal layer in the second through hole, and a third contact through hole is formed in the metal layer in the third through hole.
Optionally, the first electrode and the second electrode comprise a titanium nitride (TiN) layer.
Optionally, the capacitance medium includes a silicon nitride (SiN) layer.
Optionally, the second interlayer dielectric includes an oxide layer.
Optionally, the capacitance medium covers the second electrode and separates the first electrode from the second electrode.
Optionally, before the etching, the method further includes:
forming the dielectric layer on the first interlayer dielectric;
forming a first oxide layer on the dielectric layer;
sequentially forming a first electrode layer, a first capacitance medium layer and a second electrode layer on the first oxide layer;
etching to remove the second electrode layer and the capacitor dielectric layer in other areas except the area where the second electrode is located, wherein the rest second electrode layer forms the second electrode;
depositing a second capacitance dielectric layer;
etching to remove the first capacitor dielectric layer, the second capacitor dielectric layer and the first electrode layer in other areas except the area where the capacitor dielectric is located, wherein the remaining first capacitor dielectric layer and the remaining second capacitor dielectric layer form the capacitor dielectric, and the remaining first electrode layer forms the first electrode;
depositing a second oxide layer, the second oxide layer and the first oxide layer constituting the first interlayer dielectric.
Optionally, the metal layer comprises copper (Cu).
Optionally, the metal line includes copper.
Optionally, the dielectric layer includes nitride doped silicon carbide (NDC).
The technical scheme at least comprises the following advantages:
in the manufacturing process of the rear end structure of the stepped MIM capacitor, after the interlayer dielectric layer on the stepped MIM capacitor is deposited, the first electrode, the second electrode and the metal connecting line of the MIM capacitor are opened by directly etching the interlayer dielectric layer covered above the MIM capacitor and the metal connecting line with smaller thickness difference, so that metal layers are formed and planarized, and the problems that in the related technology, planarization is carried out first and then different etching procedures are required to be designed to open the metal layers in sequence to overcome the problem that the process is complicated due to the step thickness difference of the interlayer dielectric are solved, and the manufacturing cost is reduced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 2 are schematic diagrams illustrating formation of a backend structure including a MIM capacitor provided in the related art;
fig. 3 is a flow chart of a method for forming a backend structure including a MIM capacitor according to an exemplary embodiment of the present application;
fig. 4-8 are schematic diagrams illustrating formation of a backend structure including a MIM capacitor according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 3, a flow chart of a method for forming a backend structure including a MIM capacitor according to an exemplary embodiment of the present application is shown, the method including:
step S1, etching is performed to expose the first electrode of the first target area, the second electrode of the second target area, and the metal connection line of the third target area, so as to form a first via hole in the first target area, a second via hole in the second target area, and a third via hole in the third target area.
Step S2, a metal layer is formed, and the metal layer fills the first via, the second via, and the third via.
Referring to fig. 6, a schematic cross-sectional view before etching is performed is shown. As shown in fig. 6, a metal connection line 311 is formed in the first interlayer dielectric 310, a dielectric layer 320 is formed on the first interlayer dielectric 310, a second interlayer dielectric 330 is formed on the dielectric layer 320, and a step-type MIM capacitor is formed in the second interlayer dielectric 330, and includes a first electrode 331, a capacitor dielectric 333, and a second electrode 332, where the second electrode 333 is covered by the capacitor dielectric 332 and the capacitor dielectric 332 isolates the first electrode 331 from the second electrode 332.
Since the MIM capacitor is step-shaped, the third interlayer dielectric 330 is formed by deposition, the third interlayer dielectric 330 is step-shaped, the height of the second interlayer dielectric above the second electrode 332 is higher than the height of the second interlayer dielectric above the first electrode 331, and the height of the second interlayer dielectric above the first electrode 331 is higher than the height of the second interlayer dielectric above the metal wire 311; meanwhile, since the height of the second electrode 332 is higher than that of the first electrode 331, and the height of the first electrode 331 is higher than that of the metal connection line 311, the thicknesses of the second electrode 332, the first electrode 331 and the second dielectric layer 330 above the metal connection line 311 are relatively close.
Referring to fig. 7, a schematic cross-sectional view through the formation of a metal layer after etching is shown. As shown in fig. 7, a photolithography process may be used to etch the first target region, the second target region, and the third target region, such that the first electrode 331 of the first target region is exposed, the second electrode 332 of the second target region is exposed, and the metal connection line 311 of the third target region is exposed, and since the thicknesses of the second electrode 332, the first electrode 331, and the second dielectric layer 330 above the metal connection line 311 are relatively close, the thin film layers may be opened by one etching.
Optionally, the metal layer 340 and the metal line 311 include copper, and the metal layer 340 may be formed by electroplating.
Optionally, the metal layer 340 includes aluminum or tungsten, and the metal layer 340 may be formed by depositing aluminum or tungsten through a Physical Vapor Deposition (PVD) process.
Optionally, the first electrode 331 and the second electrode 332 comprise a titanium nitride layer, and the capacitor dielectric 333 comprises a silicon nitride layer; optionally, the dielectric layer 320 includes NDC; optionally, the first interlayer dielectric 310 and the second interlayer dielectric 330 comprise an oxide layer (e.g., silicon dioxide (SiO)2) Layers).
Step S3, performing planarization treatment, wherein the metal layer in the first via forms a first contact via, the metal layer in the second via forms a second contact via, and the metal layer in the third via forms a third contact via.
Referring to fig. 8, a schematic cross-sectional view of forming the first contact via, and the first contact via is shown. Illustratively, as shown in fig. 8, the planarization process may be performed by a Chemical Mechanical Polishing (CMP) process, wherein the metal layer in the first via forms a first contact via 341, the metal layer in the second via forms a second contact via 342, and the metal layer in the third via forms a third contact via 343.
To sum up, in the embodiment of the present application, after depositing an interlayer dielectric layer on a stepped MIM capacitor in a process of manufacturing a rear end structure including the stepped MIM capacitor, the first electrode, the second electrode, and the metal connection line of the MIM capacitor are opened by directly etching the interlayer dielectric layer covered above the MIM capacitor and the metal connection line with a small difference in thickness, thereby forming metal layers and planarizing the metal layers.
Optionally, in this embodiment of the application, before step S1, the method further includes:
forming a dielectric layer on the first interlayer dielectric; forming a first oxide layer on the dielectric layer; sequentially forming a first electrode layer, a first capacitor dielectric layer and a second electrode layer on the first oxide layer; etching to remove the second electrode layer and the capacitor dielectric layer in other areas except the area where the second electrode is located, and forming a second electrode by the remaining second electrode layer; depositing a second capacitance dielectric layer; etching to remove the first capacitor dielectric layer, the second capacitor dielectric layer and the first electrode layer in other areas except the area where the capacitor dielectric is located, wherein the residual first capacitor dielectric layer and the residual second capacitor dielectric layer form the capacitor dielectric, and the residual first electrode layer forms the first electrode; and depositing a second oxide layer, wherein the second oxide layer and the first oxide layer form a first interlayer medium.
Referring to fig. 4, a schematic cross-sectional view of a dielectric layer, a first oxide layer, a first electrode layer, a first capacitor dielectric layer, and a second electrode layer deposited in sequence is shown. As shown in fig. 4, a dielectric layer 320 is formed on the first interlayer dielectric 310, a first oxide layer 3301 is formed on the dielectric layer 320, a first electrode layer 3311 is formed on the first oxide layer 3301, a capacitor dielectric layer 3331 is formed on the first electrode layer 3311, and a second electrode layer 3321 is formed on the capacitor dielectric layer 3331. The first oxide layer 3301 is a thin film layer forming the second interlayer dielectric 330, the first electrode layer 3311 is a thin film layer forming the first electrode 331, the capacitor dielectric layer 3331 is a thin film layer forming the capacitor dielectric 333, and the second electrode layer 3321 is a thin film layer forming the first electrode 332.
Referring to fig. 5, a schematic cross-sectional view of the second capacitor dielectric layer deposited after etching to remove the second electrode layer in the other region except the region where the second electrode is located is shown. As shown in fig. 5, after removing the second electrode layer and the capacitor dielectric layer in other regions except the region where the second electrode is located, the remaining second electrode layer forms a second electrode 332. The deposited second capacitor dielectric layer 3332 is a thin film layer that forms the capacitor dielectric 333.
Referring to fig. 6, a schematic cross-sectional view after deposition of a second oxide layer is shown. As shown in fig. 6, after the first capacitor dielectric layer 3311, the second capacitor dielectric layer 3332 and the first electrode layer 3311 in the other region except the region where the capacitor dielectric 333 is located are removed by etching, the capacitor dielectric 333 is formed by the remaining first capacitor dielectric layer 3331 and the second capacitor dielectric layer 3332, the first electrode layer 3311 is formed by the remaining first electrode layer 331, and the second interlayer dielectric 330 is formed by the deposited second oxide layer 3302 and the first oxide layer 3301.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (9)
1. The forming method of the back-end structure comprising the MIM capacitor is characterized in that the MIM capacitor is of a step type and comprises a first electrode, a capacitor medium and a second electrode;
the MIM capacitor is formed in a second interlayer dielectric, the second interlayer dielectric is formed on the dielectric layer, the dielectric layer is formed on the first interlayer dielectric, a metal connecting line is formed in the first interlayer dielectric, the height of the second interlayer dielectric above the second electrode is higher than that of the second interlayer dielectric above the first electrode, and the height of the second interlayer dielectric above the first electrode is higher than that of the second interlayer dielectric above the metal connecting line;
the method comprises the following steps:
etching to expose a first electrode of a first target area, a second electrode of a second target area and a metal connecting wire of a third target area, forming a first through hole in the first target area, forming a second through hole in the second target area and forming a third through hole in the third target area;
forming a metal layer filling the first through hole, the second through hole and the third through hole;
and carrying out planarization treatment, wherein a first contact through hole is formed in the metal layer in the first through hole, a second contact through hole is formed in the metal layer in the second through hole, and a third contact through hole is formed in the metal layer in the third through hole.
2. The method of claim 1, wherein the first electrode and the second electrode comprise a titanium nitride layer.
3. The method of claim 2, wherein the capacitive dielectric comprises a silicon nitride layer.
4. The method of any of claims 1 to 3, wherein the second interlayer dielectric comprises an oxide layer.
5. The method of claim 4, wherein the capacitive medium encapsulates the second electrode and isolates the first and second electrodes.
6. The method of claim 5, wherein prior to said etching, further comprising:
forming the dielectric layer on the first interlayer dielectric;
forming a first oxide layer on the dielectric layer;
sequentially forming a first electrode layer, a first capacitance medium layer and a second electrode layer on the first oxide layer;
etching to remove the second electrode layer and the capacitor dielectric layer in other areas except the area where the second electrode is located, wherein the rest second electrode layer forms the second electrode;
depositing a second capacitance dielectric layer;
etching to remove the first capacitor dielectric layer, the second capacitor dielectric layer and the first electrode layer in other areas except the area where the capacitor dielectric is located, wherein the remaining first capacitor dielectric layer and the remaining second capacitor dielectric layer form the capacitor dielectric, and the remaining first electrode layer forms the first electrode;
depositing a second oxide layer, the second oxide layer and the first oxide layer constituting the first interlayer dielectric.
7. The method of claim 6, wherein the metal layer comprises copper.
8. The method of claim 7, wherein the metal line comprises copper.
9. The method of claim 8, wherein the dielectric layer comprises NDC.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050063048A (en) * | 2003-12-19 | 2005-06-28 | 매그나칩 반도체 유한회사 | Method for forming mim capacitor of semiconductor device |
| KR20100065834A (en) * | 2008-12-09 | 2010-06-17 | 주식회사 동부하이텍 | Method for manufacturing a semiconductor device |
| CN112259522A (en) * | 2020-10-28 | 2021-01-22 | 华虹半导体(无锡)有限公司 | Rear-end structure comprising MIM capacitor and manufacturing method thereof |
| CN112259520A (en) * | 2020-10-14 | 2021-01-22 | 华虹半导体(无锡)有限公司 | Forming method of MIM capacitor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050063048A (en) * | 2003-12-19 | 2005-06-28 | 매그나칩 반도체 유한회사 | Method for forming mim capacitor of semiconductor device |
| KR20100065834A (en) * | 2008-12-09 | 2010-06-17 | 주식회사 동부하이텍 | Method for manufacturing a semiconductor device |
| CN112259520A (en) * | 2020-10-14 | 2021-01-22 | 华虹半导体(无锡)有限公司 | Forming method of MIM capacitor |
| CN112259522A (en) * | 2020-10-28 | 2021-01-22 | 华虹半导体(无锡)有限公司 | Rear-end structure comprising MIM capacitor and manufacturing method thereof |
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