CN116504714A - Manufacturing method of rear section structure - Google Patents

Manufacturing method of rear section structure Download PDF

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Publication number
CN116504714A
CN116504714A CN202310603832.1A CN202310603832A CN116504714A CN 116504714 A CN116504714 A CN 116504714A CN 202310603832 A CN202310603832 A CN 202310603832A CN 116504714 A CN116504714 A CN 116504714A
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CN
China
Prior art keywords
layer
upper electrode
etching
dielectric layer
lower electrode
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Pending
Application number
CN202310603832.1A
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Chinese (zh)
Inventor
向超
范晓
余航
王龙鑫
杨倩
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Priority to CN202310603832.1A priority Critical patent/CN116504714A/en
Publication of CN116504714A publication Critical patent/CN116504714A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Abstract

The application discloses a manufacturing method of a rear section structure, which comprises the following steps: forming a second etching stop layer, wherein the second etching stop layer covers the exposed surfaces of the lower electrode layer, the capacitance medium layer, the first etching stop layer and the upper electrode, the upper electrode is formed on the capacitance medium layer, the capacitance medium layer is formed on the lower electrode layer, the lower electrode layer is formed on the second medium layer, the second medium layer is formed on the barrier layer, the barrier layer is formed on the first medium layer, a metal connecting wire is formed in the first medium layer, and the width of the bottom of the capacitance medium layer is larger than that of the upper electrode; covering the photoresist on the second etching stop layer through a photoetching process to expose a region to be etched; etching to remove the second etching stop layer and the lower electrode layer at the periphery of the photoresist, etching to a preset depth in the second dielectric layer, and forming a lower electrode of the MIM capacitor by the residual lower electrode layer, wherein the width of the lower electrode is larger than that of the bottom of the capacitor dielectric layer; removing the photoresist; and forming a third dielectric layer.

Description

Manufacturing method of rear section structure
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a back-end structure.
Background
Semiconductor integrated circuit fabrication processes include front end of line (FEOL) processes and back end of line (BEOL) processes. The back-end process is to form several layers of conductive metal wires on the wafer integrated with the transistor, wherein the metal wires of different layers are electrically connected through contact holes (via), and the metal wires are insulated and isolated through interlayer dielectric (inter layer dielectric, ILD) layers.
In a semiconductor integrated circuit, a capacitor is an indispensable device in an analog chip and a radio frequency chip, and the accuracy of the capacitor often directly affects the performance of the whole chip, and thus, an integrated metal-insulator-metal (MIM) capacitor becomes a conventional choice of high-performance analog and radio frequency chips in a back-end process of the integrated circuit.
Among MIM capacitors, a high dielectric constant (dielectric constant K is greater than 4) MIM capacitor (hereinafter referred to simply as "high-K MIM capacitor") is widely used because of its large capacitance per unit area and small footprint. Referring to fig. 1, a schematic cross-sectional view of a contact hole (via) etched during a fabrication process of a high-K MIM capacitor according to the related art is shown, and exemplary is shown in fig. 1:
the first dielectric layer 111 is formed with a barrier layer 120, the first dielectric layer 111 is formed with a metal connecting wire 130, the barrier layer 120 is formed with a second dielectric layer 112, the second dielectric layer is formed with a high-K MIM capacitor with a step-shaped cross section, the high-K MIM capacitor sequentially comprises a lower electrode layer 141, a capacitor dielectric layer 143 and an upper electrode layer 142 from bottom to top, and an etching stop layer 150 is formed on the upper surface of the high-K MIM capacitor, wherein the capacitor dielectric layer 143 is made of a high-K dielectric, the cross section of the high-K dielectric layer is a step-shaped, the lower bottom of the step-shaped capacitor dielectric layer 143 and the lower electrode layer 141 are equal in width in the transverse direction, the upper bottom of the step-shaped capacitor dielectric layer 143 and the upper electrode layer 142 are equal in width in the transverse direction, and the upper electrode layer 142 is smaller than the lower electrode layer 143 in the transverse direction.
After etching, a first via hole 101, a second via hole 102 and a third via hole 103 are formed in the second dielectric layer 112 and the barrier layer 120, the upper electrode layer 142 at the bottom of the first via hole 101 is exposed, the lower electrode layer 141 at the bottom of the second via hole 102 is exposed, and the metal connection line 130 at the bottom of the third via hole 103 is exposed. In general, the upper and lower electrode layers and the metal wiring are made of different materials, and after the contact hole etching is performed, the upper and lower electrode layers and the metal wiring are exposed, and meanwhile, the capacitor dielectric layer 143 is also exposed by etching because it is located on the lower electrode layer 141 and has the same width as that of the lower electrode layer, so that the high-K material forming the capacitor dielectric layer 143 may pollute the upper and lower electrode layers, the metal wiring and the equipment chamber, and reduce the reliability and yield of the device product.
Disclosure of Invention
The application provides a manufacturing method of a back-end structure, which can solve the problem that the reliability and yield of a device are poor due to the fact that a capacitor dielectric layer of an MIM capacitor needs to be opened in etching of a contact hole in the back-end structure integrated with the MIM capacitor in the related technology, and the method comprises the following steps:
forming a second etching stop layer, wherein the second etching stop layer covers the exposed surfaces of a lower electrode layer, a capacitance medium layer, a first etching stop layer and an upper electrode, the upper electrode is formed on the capacitance medium layer, the capacitance medium layer is formed on the lower electrode layer, the lower electrode layer is formed on the second medium layer, the second medium layer is formed on a blocking layer, the blocking layer is formed on a first medium layer, a metal connecting wire is formed in the first medium layer, the section of the capacitance medium layer is in a two-stage step shape, the width of the top of the two-stage step-shaped capacitance medium layer is the same as the width of the upper electrode, the width of the bottom of the two-stage step-shaped capacitance medium layer is larger than the width of the upper electrode, and the first etching blocking layer surrounds the periphery of the upper electrode;
covering a photoresist on the second etching stop layer through a photoetching process to expose a region to be etched, wherein the photoresist covers the upper electrode, the capacitor dielectric layer and the first etching stop layer;
etching to remove the second etching stop layer and the lower electrode layer at the periphery of the photoresist, etching to a preset depth in the second dielectric layer, and forming a lower electrode of the MIM capacitor by the residual lower electrode layer, wherein the width of the lower electrode is larger than that of the bottom of the two-stage step capacitor dielectric layer;
removing the photoresist;
forming a third dielectric layer, wherein the third dielectric layer covers the exposed surfaces of the second etching stop layer, the lower electrode and the first dielectric layer;
in the subsequent etching steps of the first contact hole, the second contact hole and the third contact hole, the capacitor dielectric layer is not exposed, the first contact hole is used for contacting with the upper electrode, the second contact hole is used for contacting with the lower electrode, and the third contact hole is used for contacting with the metal connecting line.
In some embodiments, before forming the second etch stop layer, the method further comprises:
sequentially forming a lower electrode layer, a capacitance dielectric layer and an upper electrode layer on the second dielectric layer;
covering a photoresist on a preset area on the upper electrode layer through a photoetching process to expose an area to be etched;
etching to remove the upper electrode layers of other areas except the preset area, etching to the preset depth of the capacitor dielectric layers of other areas except the preset area, wherein the section of the capacitor dielectric layer after etching is two-stage step type, and the rest upper electrode layers form the upper electrode of the MIM capacitor;
removing the photoresist;
forming a first etching stop layer, wherein the first etching stop layer covers the exposed areas of the upper electrode and the capacitance medium layer;
etching, namely removing the top end of the upper electrode layer and a first etching stop layer on the peripheral side of the upper electrode, wherein the section of the capacitor dielectric layer is three-stage-type after etching, and the rest first etching stop layer is positioned on a second-stage of the capacitor dielectric layer and surrounds the peripheral side of the upper electrode;
and etching to remove the capacitance dielectric layer at the periphery of the first etching stop layer, wherein the sections of the rest capacitance dielectric layers are of two-stage step type, and the bottom width of the two-stage step type capacitance dielectric layer is smaller than the width of the lower electrode layer.
In some embodiments, after the forming the third dielectric layer, the method further includes:
forming a first through hole and a second through hole in the third dielectric layer, forming a third through hole in the second dielectric layer, the third dielectric layer and the barrier layer, wherein an upper electrode at the bottom of the first through hole is exposed, a lower electrode at the bottom of the second through hole is exposed, the second through hole does not penetrate through the capacitance dielectric layer, and a metal connecting wire at the bottom of the third through hole is exposed;
and filling metal layers in the first through hole, the second through hole and the third through hole, wherein the metal layers in the first through hole form the first contact hole, the metal layers in the second through hole form the second contact hole, and the metal layers in the third through hole form the third contact hole.
In some embodiments, the capacitive dielectric layer comprises an aluminum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.
In some embodiments, the upper electrode or the lower electrode comprises a titanium nitride layer.
In some embodiments, the barrier layer comprises an NDC layer.
In some embodiments, the first etch stop layer and the second etch stop layer comprise a silicon nitride layer.
The technical scheme of the application at least comprises the following advantages:
through integrating the MIM capacitor in the dielectric layer of the back-end structure in the manufacturing process of the back-end structure of the semiconductor integrated circuit, the width of the capacitor dielectric layer of the MIM capacitor is smaller than that of the lower electrode, and in the subsequent contact hole etching process, a lead-out area can be arranged at the position of the lower electrode, which exceeds the capacitor dielectric layer, so that the capacitor dielectric layer does not need to be opened in etching, the pollution of high-K materials is reduced, and the reliability and the yield of the device are improved to a certain extent.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a contact hole etched during a process of manufacturing a high-K MIM capacitor according to the related art;
FIG. 2 is a flow chart of a method of fabricating a back-end structure provided in an exemplary embodiment of the present application;
fig. 3 to 13 are schematic views illustrating formation of a rear structure according to an exemplary embodiment of the present application;
FIG. 14 is a flowchart of a method of fabricating a back end structure provided in an exemplary embodiment of the present application;
fig. 15 is a flowchart of a method for fabricating a back-end structure according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Referring to fig. 2, a flowchart of a method for manufacturing a back-end structure according to an exemplary embodiment of the present application is shown, and as shown in fig. 2, the method includes:
step S1, forming a second etching stop layer, wherein the second etching stop layer covers the exposed surfaces of a lower electrode layer, a capacitance medium layer, a first etching stop layer and an upper electrode, the upper electrode is formed on the capacitance medium layer, the capacitance medium layer is formed on the lower electrode layer, the lower electrode layer is formed on the second medium layer, the second medium layer is formed on a blocking layer, the blocking layer is formed on the first medium layer, a metal connecting wire is formed in the first medium layer, the section of the capacitance medium layer is in a two-stage step shape, the width of the top of the two-stage step-shaped capacitance medium layer is the same as that of the upper electrode, the width of the bottom of the two-stage step-shaped capacitance medium layer is larger than that of the upper electrode, and the first etching blocking layer surrounds the periphery of the upper electrode.
Referring to fig. 8, a schematic cross-sectional view after forming a second etch stop layer is shown. As shown in fig. 8, the second etching stop layer 360 covers the exposed surfaces of the lower electrode layer 341, the capacitor dielectric layer 343, the first etching stop layer 350 and the upper electrode 342, the upper electrode 342 is formed on the capacitor dielectric layer 343, the capacitor dielectric layer 343 is formed on the lower electrode layer 341, the lower electrode layer 341 is formed on the second dielectric layer 3121, the second dielectric layer 3121 is formed on the barrier layer 320, the barrier layer 320 is formed on the first dielectric layer 311, the metal connection line 330 is formed in the first dielectric layer 311, the cross section of the capacitor dielectric layer 343 is in a two-stage step shape, the width of the top of the two-stage step capacitor dielectric layer 343 is the same as the width of the upper electrode 342, the width of the bottom of the two-stage step capacitor dielectric layer 343 is larger than the width of the upper electrode 342, and the first etching barrier layer 350 surrounds the periphery of the upper electrode 342 and is located above the second stage step.
Wherein the capacitance dielectric layer 343 comprises a high-K material layer, which may comprise, for example, aluminum oxide (Al 2 O 3 ) Layer, hafnium oxide (HfO) 2 ) Layers or zirconium dioxide (ZrO 2 ) A layer; the upper electrode 342 and the lower electrode layer 341 may include a titanium nitride (TiN) layer; the first dielectric layer 311 and the second dielectric layer 3121 include silicon dioxide (SiO 2 ) A layer; the metal wire 330 includes a copper (Cu) layer. In some embodiments, the barrier layer 320 comprises a doped silicon carbide (nitride doped silicon carbide, NDC) layer, and the thickness of the barrier layer 320 ranges from 200 angstromsTo 1000 angstroms (which may be 500 angstroms, for example), first etch stop layer 350 and second etch stop layer 360 comprise silicon nitride (Si) 3 N 4 ) The second etch stop layer 360 may be formed by depositing a silicon nitride layer by a chemical vapor deposition (chemical vapor deposition, CVD) process, the thickness of the second etch stop layer 360 ranging from 200 a to 1500 a (which may be 800 a, for example).
And S2, covering a photoresist on the second etching stop layer through a photoetching process to expose a region to be etched, wherein the photoresist covers the upper electrode, the capacitor dielectric layer and the first etching stop layer.
Referring to fig. 9, a schematic cross-sectional view of a photoresist overlaid on a second etch stop layer by a photolithographic process is shown. Illustratively, as shown in fig. 9, a photoresist 402 may be formed on the second etching stop layer 360 by a photolithography process, where the area covered by the photoresist 402 is a region corresponding to the bottom electrode of the MIM capacitor, and encapsulates the upper electrode 342, the capacitor dielectric layer 343 and the first etching stop layer 350.
And S3, etching to remove the second etching stop layer and the lower electrode layer on the periphery of the photoresist, etching to a preset depth in the second dielectric layer, and forming a lower electrode of the MIM capacitor by the residual lower electrode layer, wherein the width of the lower electrode is larger than that of the bottom of the two-stage step capacitor dielectric layer.
And S4, removing the photoresist.
Referring to fig. 10, a schematic cross-sectional view is shown after etching to form the bottom electrode. Illustratively, as shown in fig. 10, the second etching stop layer 360 and the lower electrode layer 341 in other regions are removed except for the region covered by the photoresist 402 (the region corresponding to the lower electrode), and the second dielectric layer 3121 in other regions is etched to a predetermined depth, and the remaining lower electrode layer 341 forms the lower electrode of the MIM capacitor. The width of the lower electrode 341 in the transverse direction is larger than that of the capacitance medium layer 343, and the contact hole of the lower electrode is formed in the area of the lower electrode 341 beyond the capacitance medium layer 343, so that pollution caused by opening the capacitance medium layer 343 can be avoided.
And S5, forming a third dielectric layer, wherein the third dielectric layer covers the exposed surfaces of the second etching stop layer, the lower electrode and the first dielectric layer.
In the subsequent etching steps of the first contact hole, the second contact hole and the third contact hole, the capacitance medium layer is not exposed, the first contact hole is used for contacting with the upper electrode, the second contact hole is used for contacting with the lower electrode, and the third contact hole is used for contacting with the metal connecting wire.
Referring to fig. 11, a schematic cross-sectional view of forming a third dielectric layer is shown. For example, the third dielectric layer 3122 may be formed by depositing a silicon dioxide layer by a CVD process, and then planarizing the third dielectric layer 3122 (e.g., by a chemical mechanical polishing (chemical mechanical planarization, CMP) process).
In summary, in the embodiment of the present application, by integrating the MIM capacitor in the dielectric layer of the back-end structure in the manufacturing process of the back-end structure of the semiconductor integrated circuit, since the width of the capacitor dielectric layer of the MIM capacitor is smaller than that of the lower electrode, in the subsequent contact hole etching process, the lead-out area can be set at the position of the lower electrode beyond the capacitor dielectric layer to form the corresponding contact hole, so that the capacitor dielectric layer does not need to be opened in etching, pollution of high-K materials is reduced, and reliability and yield of the device are improved to a certain extent.
Referring to fig. 14, a flowchart of a method for manufacturing a back-end structure according to an exemplary embodiment of the present application is shown, where the method may be a method performed before step S1 in the embodiment of fig. 2, and as shown in fig. 14, the method includes:
in step S101, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer are sequentially formed on the second dielectric layer.
Step S102, a photoresist is covered on a preset area on the upper electrode layer through a photoetching process, and the area needing etching is exposed.
Referring to fig. 3, a schematic cross-sectional view of a photoresist layer overlying an upper electrode layer after forming a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer over a second dielectric layer is shown. As shown in fig. 3, a lower electrode layer 341 may be formed by depositing a titanium nitride layer on the second dielectric layer 3121 through a CVD process, a capacitor dielectric layer 343 may be formed by depositing a high K material layer on the lower electrode layer 341 through a CVD process, an upper electrode layer 342 may be formed by depositing a titanium nitride layer on the capacitor dielectric layer 343 through a CVD process, a photoresist 401 may be coated on the upper electrode layer 342 through a photolithography process, and a region to be etched may be exposed, wherein a predetermined region coated by the photoresist 401 is a region corresponding to the upper electrode.
The thickness of the lower electrode layer 341 ranges from 300 a to 1000 a (e.g., it may be 500 a), the thickness of the capacitance dielectric layer 343 ranges from 50 a to 300 a (e.g., it may be 190 a), and the thickness of the upper electrode layer 342 ranges from 300 a to 1000 a (e.g., it may be 500 a).
Step S103, etching is carried out, the upper electrode layers of other areas except the preset area are removed, etching is carried out to the preset depth of the capacitor dielectric layers of the other areas except the preset area, the section of the etched capacitor dielectric layer is in a two-stage step shape, and the remaining upper electrode layers form the upper electrode of the MIM capacitor.
Step S104, removing the photoresist.
Referring to fig. 4, a schematic cross-sectional view is shown after etching to form the upper electrode. As shown in fig. 4, after etching is performed to remove the photoresist 401, the upper electrode layer in the other area outside the predetermined area is removed, the capacitor dielectric layer 343 in the other area outside the predetermined area is etched to a predetermined depth, the remaining upper electrode layer forms the upper electrode 342 of the MIM capacitor, the cross section of the capacitor dielectric layer 343 after etching is two-stage step type, and the etched area of the capacitor dielectric layer 343 is etched to a depth of 30 to 150 angstroms (for example, it may be etched by 100 angstroms), which is the step difference between the first stage step and the second stage step.
In step S105, a first etching stop layer is formed, and the first etching stop layer covers the exposed areas of the upper electrode and the capacitor dielectric layer.
Referring to fig. 5, a schematic cross-sectional view of forming a first etch stop layer is shown. Illustratively, as shown in fig. 5, the first etch stop layer 350 may be formed by depositing a silicon nitride layer by a CVD process, and the thickness of the first etch stop layer 350 may range from 400 a to 1200 a (e.g., it may be 800 a).
And S106, etching, namely removing the top end of the upper electrode layer and the first etching stop layer on the peripheral side of the upper electrode, wherein the section of the etched capacitor dielectric layer is three-stage steps, and the rest of the first etching stop layer is positioned on the second-stage steps of the capacitor dielectric layer and surrounds the peripheral side of the upper electrode.
Referring to fig. 6, a schematic cross-sectional view of a three level stepped capacitive dielectric layer formed after etching is shown. Illustratively, as shown in fig. 6, the first etching stop layer 350 on the top end of the upper electrode layer 342 and on the peripheral side of the upper electrode layer 342 may be removed by etching using a dry etching process, and the remaining first etching stop layer 350 is located on the second step of the capacitance dielectric layer 343 and surrounds the peripheral side of the upper electrode layer 342.
Step S107, etching is performed to remove the capacitance dielectric layer at the periphery of the first etching stop layer, the section of the rest capacitance dielectric layer is of a two-stage step type, and the bottom width of the two-stage step type capacitance dielectric layer is smaller than the width of the lower electrode layer.
Referring to fig. 7, a schematic cross-sectional view of etching away the capacitor dielectric layer on the periphery of the first etch stop layer is shown. For example, the capacitor dielectric layer on the peripheral side of the first etching stop layer 350 may be removed by a wet etching process, and the cross section of the remaining capacitor dielectric layer 343 is in a two-stage step shape, where the bottom width of the two-stage step-shaped capacitor dielectric layer 343 is smaller than the width of the lower electrode layer 341.
In step S108, a second etching stop layer is formed, and the second etching stop layer covers the exposed surfaces of the lower electrode layer, the capacitor dielectric layer, the upper electrode and the first etching stop layer.
Referring to fig. 15, a flowchart illustrating a method for fabricating a back-end structure according to an exemplary embodiment of the present application may be a method performed after step S5 in the embodiment of fig. 2, as shown in fig. 15, and the method includes:
in step 501, a first via hole and a second via hole are formed in the third dielectric layer, and a third via hole is formed in the second dielectric layer, the third dielectric layer and the barrier layer, the upper electrode at the bottom of the first via hole is exposed, the lower electrode at the bottom of the second via hole is exposed, the second via hole does not pass through the capacitor dielectric layer, and the metal wire at the bottom of the third via hole is exposed.
Referring to fig. 12, a schematic cross-sectional view after forming the first, second and third vias is shown. As shown in fig. 12, the first via 301, the second via 302, and the third via 303 may be formed by photolithography and etching processes, the upper electrode 342 at the bottom of the first via 301 is exposed, the lower electrode 341 at the bottom of the second via 302 is exposed, the second via does not pass through the capacitor dielectric layer 343, and the metal wire 330 at the bottom of the third via 303 is exposed.
Step 502, filling metal layers in the first through hole, the second through hole and the third through hole, wherein the metal layers in the first through hole form a first contact hole, the metal layers in the second through hole form a second contact hole, and the metal layers in the third through hole form a third contact hole.
Referring to fig. 13, a schematic cross-sectional view after forming the first, second and third contact holes is shown. Illustratively, as shown in FIG. 13, step 502 includes, but is not limited to: forming a metal layer filling the first through hole 301, the second through hole 302 and the third through hole 303; a planarization process (for example, a planarization process may be performed by a CMP process) is performed, and the metal layers outside the first via 301, the second via 302, and the third via 303 are removed, where the metal layer in the first via 301 forms a first contact hole 371, the metal layer in the second via 302 forms a second contact hole 372, and the metal layer in the third via 303 forms a third contact hole 373.
If the metal layer comprises a copper layer, the copper layer may be formed by an electroplating process, if the metal layer comprises an aluminum (Al) layer, the aluminum layer may be deposited by a physical vapor deposition (physical vapor deposition, PVD) process, and if the metal layer comprises a tungsten (W) layer, the tungsten layer may be deposited by a CVD process.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (7)

1. A method of making a posterior segment structure, comprising:
forming a second etching stop layer, wherein the second etching stop layer covers the exposed surfaces of a lower electrode layer, a capacitance medium layer, a first etching stop layer and an upper electrode, the upper electrode is formed on the capacitance medium layer, the capacitance medium layer is formed on the lower electrode layer, the lower electrode layer is formed on the second medium layer, the second medium layer is formed on a blocking layer, the blocking layer is formed on a first medium layer, a metal connecting wire is formed in the first medium layer, the section of the capacitance medium layer is in a two-stage step shape, the width of the top of the two-stage step-shaped capacitance medium layer is the same as the width of the upper electrode, the width of the bottom of the two-stage step-shaped capacitance medium layer is larger than the width of the upper electrode, and the first etching blocking layer surrounds the periphery of the upper electrode;
covering a photoresist on the second etching stop layer through a photoetching process to expose a region to be etched, wherein the photoresist covers the upper electrode, the capacitor dielectric layer and the first etching stop layer;
etching to remove the second etching stop layer and the lower electrode layer at the periphery of the photoresist, etching to a preset depth in the second dielectric layer, and forming a lower electrode of the MIM capacitor by the residual lower electrode layer, wherein the width of the lower electrode is larger than that of the bottom of the two-stage step capacitor dielectric layer;
removing the photoresist;
forming a third dielectric layer, wherein the third dielectric layer covers the exposed surfaces of the second etching stop layer, the lower electrode and the first dielectric layer;
in the subsequent etching steps of the first contact hole, the second contact hole and the third contact hole, the capacitor dielectric layer is not exposed, the first contact hole is used for contacting with the upper electrode, the second contact hole is used for contacting with the lower electrode, and the third contact hole is used for contacting with the metal connecting line.
2. The method of claim 1, wherein prior to forming the second etch stop layer, further comprising:
sequentially forming a lower electrode layer, a capacitance dielectric layer and an upper electrode layer on the second dielectric layer;
covering a photoresist on a preset area on the upper electrode layer through a photoetching process to expose an area to be etched;
etching to remove the upper electrode layers of other areas except the preset area, etching to the preset depth of the capacitor dielectric layers of other areas except the preset area, wherein the section of the capacitor dielectric layer after etching is two-stage step type, and the rest upper electrode layers form the upper electrode of the MIM capacitor;
removing the photoresist;
forming a first etching stop layer, wherein the first etching stop layer covers the exposed areas of the upper electrode and the capacitance medium layer;
etching, namely removing the top end of the upper electrode layer and a first etching stop layer on the peripheral side of the upper electrode, wherein the section of the capacitor dielectric layer is three-stage-type after etching, and the rest first etching stop layer is positioned on a second-stage of the capacitor dielectric layer and surrounds the peripheral side of the upper electrode;
and etching to remove the capacitance dielectric layer at the periphery of the first etching stop layer, wherein the sections of the rest capacitance dielectric layers are of two-stage step type, and the bottom width of the two-stage step type capacitance dielectric layer is smaller than the width of the lower electrode layer.
3. The method of claim 2, wherein after forming the third dielectric layer, further comprising:
forming a first through hole and a second through hole in the third dielectric layer, forming a third through hole in the second dielectric layer, the third dielectric layer and the barrier layer, wherein an upper electrode at the bottom of the first through hole is exposed, a lower electrode at the bottom of the second through hole is exposed, the second through hole does not penetrate through the capacitance dielectric layer, and a metal connecting wire at the bottom of the third through hole is exposed;
and filling metal layers in the first through hole, the second through hole and the third through hole, wherein the metal layers in the first through hole form the first contact hole, the metal layers in the second through hole form the second contact hole, and the metal layers in the third through hole form the third contact hole.
4. A method according to any one of claims 1 to 3, wherein the capacitive dielectric layer comprises an aluminium oxide layer, a hafnium oxide layer or a zirconium oxide layer.
5. The method of claim 4, wherein the upper electrode or the lower electrode comprises a titanium nitride layer.
6. The method of claim 5, wherein the barrier layer comprises an NDC layer.
7. The method of claim 6, wherein the first etch stop layer and the second etch stop layer comprise a silicon nitride layer.
CN202310603832.1A 2023-05-26 2023-05-26 Manufacturing method of rear section structure Pending CN116504714A (en)

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