CN113496880A - Method for thickening bottom oxide layer of silicon carbide substrate - Google Patents
Method for thickening bottom oxide layer of silicon carbide substrate Download PDFInfo
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- CN113496880A CN113496880A CN202010251282.8A CN202010251282A CN113496880A CN 113496880 A CN113496880 A CN 113496880A CN 202010251282 A CN202010251282 A CN 202010251282A CN 113496880 A CN113496880 A CN 113496880A
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- oxide layer
- silicon carbide
- thermal oxidation
- carbide substrate
- layer
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000008719 thickening Effects 0.000 title claims abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 84
- 230000003647 oxidation Effects 0.000 claims abstract description 42
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910002804 graphite Inorganic materials 0.000 claims description 4
- 239000010439 graphite Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method for thickening a bottom oxidation layer of a silicon carbide substrate, which is characterized by comprising the following steps of: providing a silicon carbide substrate; forming a groove structure in the silicon carbide substrate; performing a first thermal oxidation to form a top oxide layer, a bottom oxide layer and a sidewall oxide layer in the trench structure; depositing a protective layer on the top oxide layer, the bottom oxide layer and the sidewall oxide layer; etching to remove the protective layer covering the bottom oxide layer until the bottom oxide layer and the side wall oxide layer are exposed to form an etching area; performing a second thermal oxidation for forming an oxide layer on the bottom oxide layer in the etching region; wherein the thermal oxidation process is carried out at a temperature of greater than 1100 ℃.
Description
Technical Field
The present invention relates to a silicon carbide substrate, and more particularly, to a method for thickening a bottom oxide layer of a silicon carbide substrate.
Background
In semiconductor device fabrication, the formation of the silicon oxide layer is typically performed thermally. Silicon dioxide is grown by heating a silicon or silicon carbide surface. Oxidation of Silicon carbide (SiC) produces a buildup of carbon clusters and a high density of accumulated charge at the oxide/Silicon carbide interface. Therefore, after the thermal oxidation, another annealing step after a long time oxidation is usually performed. Silicon carbide is considered to be an excellent material for power switching devices because of its wide energy gap, high critical breakdown field strength, and high thermal conductivity. In addition, the lattice matching between the silicon carbide substrate and the gallium nitride is better than that of the sapphire substrate, and thus, the silicon carbide substrate is widely used in semiconductor devices.
Disclosure of Invention
The main object of the present invention is to provide a crystalline structure of a silicon carbide substrate that can increase the thickness of the bottom oxide layer of the silicon carbide substrate. In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the invention provides a method for thickening a bottom oxidation layer of a silicon carbide substrate, which is characterized by comprising the following steps: providing a silicon carbide substrate; forming a groove structure in the silicon carbide substrate; performing a first thermal oxidation to form a top oxide layer, a bottom oxide layer and a sidewall oxide layer in the trench structure; depositing a protective layer on the top oxide layer, the bottom oxide layer and the sidewall oxide layer; etching to remove the protective layer covering the bottom oxide layer until the bottom oxide layer and the side wall oxide layer are exposed to form an etching area; performing a second thermal oxidation for forming an oxide layer on the bottom oxide layer in the etching region; wherein the thermal oxidation process is carried out at a temperature of greater than 1100 ℃. Such as 1100 c to 1600 c.
According to one aspect of the present invention, the silicon carbide substrate has a (0001) plane on the upper surface and a lateral surface
A crystal plane. The trench structure is formed by photolithography and etching. The material of the protective layer is graphite.
According to another aspect of the invention, the first thermal oxidation is carried out by thermal oxidation of wet oxygen, by thermal oxidation of dry oxygen or by the gaseous molecules NO and N2Gas environment of OAnd (6) executing. The first thermal oxidation is carried out by nitrogen series element gas molecules NO, NO2,N2O and NH3Is performed in the environment of at least one of (1).
These and other advantages will become apparent to the reader from the following description of the preferred embodiments and the appended claims.
Drawings
The present invention will be more fully understood from the detailed description and the schematic drawings of the embodiments of the invention described below; it should be understood, however, that the intention is not to limit the invention to the particular embodiments described.
FIG. 1 is a schematic view of a silicon carbide substrate according to an embodiment of the present invention;
FIG. 2 is a schematic view of forming a photoresist pattern on a silicon carbide substrate according to an embodiment of the present invention;
FIG. 3 is a schematic view of a silicon carbide substrate etched to form a trench in accordance with one embodiment of the present invention;
FIG. 4 is a schematic view of a trench in a silicon carbide substrate according to an embodiment of the present invention;
FIG. 5 is a schematic view of a trench in a silicon carbide substrate that is subjected to a thermal oxidation process in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of depositing a passivation layer on the trench structure according to the embodiment of the present invention;
FIG. 7 is a schematic diagram of an embodiment of etching to remove a bottom layer;
FIG. 8 is a schematic view of a second thermal oxidation process performed on the bottom of a trench in a SiC substrate according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a trench structure for forming a thick bottom oxide layer according to an embodiment of the present invention.
The main part reference numbers:
100 vertical plane of horizontal upper surface 104 of silicon carbide substrate 102
106 photoresist pattern 108 etch region 110 trench
112 remaining photoresist 114 trench bottom 116 trench sidewalls
Oxide layer on sidewalls of oxide layer 122 at bottom of trench 120 on top surface 118
124 silicon carbide substrate upper surface oxidation layer 126 capping layer 128 sidewall layer
130 bottom layer 132 etch oxide layer at the bottom of region 134
Detailed Description
The present invention will be described with respect to particular embodiments and aspects thereof, which are described as illustrative of structures or process flows of the invention and are not intended to limit the claims thereto. Thus, the present invention is capable of embodiments in addition to those specifically described and preferred embodiments illustrated and described herein, as well as of other embodiments.
The method for producing a silicon carbide substrate having a thickened bottom oxide layer according to the present invention will be described below. First, a silicon carbide (SiC) substrate 100 is provided, as shown in fig. 1. In the present invention, the silicon carbide substrate 100 has a horizontal upper surface 102 and a vertical surface 104. In one embodiment, the silicon carbide substrate 100 has a top surface plane (0001) and a lateral plane
And (5) kneading.
In one embodiment, the silicon carbide substrate 100 may be applied to an Insulated Gate Bipolar Transistor (IGBT) semiconductor device. The IGBT semiconductor element adopts a Trench (Trench) structure. In the trench structure, the original horizontal gate is changed to the vertical gate. In the trench-structured IGBT element, since Depletion regions (Depletion regions) of adjacent cells do not come close to each other, a parasitic Junction Gate Field Effect Transistor (JFET) Region is eliminated. In addition, the trench-structured IGBT element can effectively suppress Latch-Up (Latch-Up).
A photoresist pattern 106 is then formed on the silicon carbide substrate 100, defining an etched region 108, as shown in fig. 2. Wherein the photoresist pattern 106 can be realized by Photolithography (Photolithography Process). Then, the photoresist pattern 106 is used as a mask to perform etching to form a trench110 as shown in fig. 3. The length, width, and depth of the trench 110 may be designed according to different elements. The etching process is, for example, wet etching, dry etching, sputter etching, or other methods. In some embodiments, the etching process to form trenches 110 includes the use of one or more etchant materials. In some embodiments, the etchant material includes the use of Cl2、SF6、HBr、HCl、CF4、CHF3、C2F6、C4F8Or other similar etchant material.
The remaining photoresist 112 is then removed to form a bottom 114, a trench for sidewalls 116, and an upper surface 118, as shown in fig. 4. Next, Thermal Oxidation (Thermal Oxidation) is performed to form an oxide layer 120 at the bottom of the trench, an oxide layer 122 at the sidewall of the trench, and an oxide layer 124 at the top surface of the silicon carbide substrate 100 for the bottom 114 and the sidewall 116 of the trench, respectively, and the top surface 118 of the silicon carbide substrate 100. In this embodiment, a thermal oxidation process is performed at a temperature of 1450 ℃ or lower (e.g., 1100 ℃ to 1450 ℃), and a thermal oxidation is performed on the surface of the trench structure of the silicon carbide substrate to form an oxide layer thin film.
The thermal oxidation process may form the oxide layer thin film by a thermal oxidation method using wet oxygen, or form the oxide layer thin film by a thermal oxidation method using dry oxygen and nitrogen. The thicknesses of the oxide layer 120 at the bottom of the trench, the oxide layer 122 at the sidewall of the trench, and the oxide layer 124 on the top surface of the silicon carbide substrate 100 can be controlled and determined by the process temperature, the thermal oxidation time, the thermal oxidation method, or other parameter conditions.
In another embodiment, the thermal oxidation process may form the oxide layer film by thermally oxidizing the surface of the trench structure of the silicon carbide substrate in a gas molecule (NO) environment containing nitrogen and oxygen. For example, in a gas molecule (N) containing nitrogen and oxygen2O) is performed, the surface of the trench structure of the silicon carbide substrate is thermally oxidized to form an oxide layer thin film. In addition, the nitrogen-containing gas contains NO and N as gas molecules containing nitrogen and oxygen2And under the atmosphere of O, thermally oxidizing the surface of the groove structure of the silicon carbide substrate to form an oxide layer film.
Next, a protection layer is deposited on the trench structure, as shown in fig. 6. The protection layer includes a cap layer 126 covering the upper surface 124 of the trench structure, a sidewall layer 128 and a bottom layer 130. The material of the protective layer is selected from high temperature resistant materials, such as graphite (graphite).
Then, an etch is performed to remove the material of the bottom layer 130 until the oxide layer 120 at the bottom of the trench and the oxide layer 122 at the sidewall of the trench are exposed, so as to form an etch region 132, as shown in fig. 7. During the etching, the sidewall layer 128 can protect the oxide layer 122 on the trench sidewall and thus is not etched away. In some embodiments, the etchant material is H2Or O2。
Thereafter, a second thermal oxidation is performed in the etching region 132 for forming an oxide layer 134 at the bottom of the trench. In this embodiment, the thermal oxidation process is performed at a temperature greater than 1100 ℃, for example, 1100 ℃ to 1600 ℃, and thermal oxidation is performed on the bottom of the trench structure of the silicon carbide substrate to form an oxide layer film. The trench Oxide layer structure is formed by adding the thickness of the original trench Bottom Oxide layer 120 to the thickness of the Oxide layer formed by thermal oxidation in the etching region 132, so as to form a Thick Bottom Oxide (TBO) 134 in the silicon carbide substrate 100. The second heating oxidation process may refer to the heating oxidation process described above.
Finally, the material of the cap layer 126 and the sidewall layer 128 are removed to form the silicon carbide substrate 100 with a thick bottom oxide layer, as shown in fig. 9.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method for thickening a bottom oxide layer of a silicon carbide substrate, comprising: providing a silicon carbide substrate; forming a trench structure in the silicon carbide substrate; performing a first thermal oxidation to form a top oxide layer, a bottom oxide layer and a sidewall oxide layer in the trench structure; depositing a protective layer on the top oxide layer, the bottom oxide layer and the sidewall oxide layer; etching to remove the protective layer covering the bottom oxide layer until the bottom oxide layer and the sidewall oxide layer are exposed to form an etching region; and performing a second thermal oxidation to form an oxide layer on the bottom oxide layer in the etching region; wherein the thermal oxidation process is carried out at a temperature of greater than 1100 ℃.
2. The method of claim 1, wherein the silicon carbide substrate has a top 0001 crystal plane and a lateral surface
A crystal plane.
3. The method of claim 1, wherein the trench structure is formed by an etching process.
4. The method of claim 3, wherein the etchant material of the etching process comprises at least one of: cl2、SF6、HBr、HCl、CF4、CHF3、C2F6、C4F8。
5. The method of claim 1, wherein the protective layer is graphite.
6. The method of claim 1, further comprising removing the cap layer and the sidewall layer of the passivation layer.
7. The method of claim 1, wherein the first thermal oxidation process is performed by a wet-oxygen thermal oxidation process.
8. The method of claim 1, wherein the first thermal oxidation process is performed by dry oxygen thermal oxidation.
9. The method of claim 1, wherein the first thermal oxidation process is performed in an environment of nitrogen-containing gas molecules.
10. The method of claim 1, wherein the first thermal oxidation process is performed on nitrogen-containing gas molecules NO, NO2,N2O and NH3Is performed in the environment of at least one of (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010251282.8A CN113496880A (en) | 2020-04-01 | 2020-04-01 | Method for thickening bottom oxide layer of silicon carbide substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010251282.8A CN113496880A (en) | 2020-04-01 | 2020-04-01 | Method for thickening bottom oxide layer of silicon carbide substrate |
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| Publication Number | Publication Date |
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| CN113496880A true CN113496880A (en) | 2021-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010251282.8A Withdrawn CN113496880A (en) | 2020-04-01 | 2020-04-01 | Method for thickening bottom oxide layer of silicon carbide substrate |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090114969A1 (en) * | 2007-11-06 | 2009-05-07 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
| CN103839807A (en) * | 2012-11-20 | 2014-06-04 | 北大方正集团有限公司 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
| JP2020035867A (en) * | 2018-08-29 | 2020-03-05 | ラピスセミコンダクタ株式会社 | Method of manufacturing semiconductor device, and semiconductor device |
-
2020
- 2020-04-01 CN CN202010251282.8A patent/CN113496880A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090114969A1 (en) * | 2007-11-06 | 2009-05-07 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
| CN103839807A (en) * | 2012-11-20 | 2014-06-04 | 北大方正集团有限公司 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
| JP2020035867A (en) * | 2018-08-29 | 2020-03-05 | ラピスセミコンダクタ株式会社 | Method of manufacturing semiconductor device, and semiconductor device |
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