CN113488469B

CN113488469B - Semiconductor memory device and method for manufacturing the same

Info

Publication number: CN113488469B
Application number: CN202110771803.7A
Authority: CN
Inventors: 张魁
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2023-10-17
Anticipated expiration: 2041-07-08
Also published as: CN113488469A

Abstract

The present disclosure provides a semiconductor memory device and a method for manufacturing the same, and relates to the technical field of semiconductors. The semiconductor memory device includes: alternately stacking nitride layers and memory combination units; the outer layer of the storage combination unit is a gate layer, the inner side of the gate layer is an annular channel region, and the inner side of the channel region is an annular floating body; at least one pair of through holes penetrating the memory cell to break the annular floating body and the channel region; at least one pair of through holes, wherein a source electrode is filled in one through hole and is only contacted with channel regions at two sides; the other through hole is filled with a drain electrode, and the drain electrode is only contacted with channel regions at two sides. The present disclosure can improve the integration level of a semiconductor memory device.

Description

Semiconductor memory device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor memory device and a method of manufacturing the same.

Background

In order to meet consumer demands for excellent performance and low cost, high integration is a development direction of semiconductor memory devices. In general, the degree of integration is determined by the area occupied by the unit memory cells.

In order to improve the integration level, a capacitor-free memory cell capable of greatly reducing the occupied area of the memory cell is proposed on the basis of a conventional memory cell having one transistor and one capacitor.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a semiconductor memory device and a method for manufacturing the same, which can improve the integration of the semiconductor memory device.

According to one aspect of the present disclosure, there is provided a semiconductor memory device including:

alternately stacking nitride layers and memory combination units; the outer layer of the storage combination unit is a gate layer, the inner side of the gate layer is an annular channel region, and the inner side of the channel region is an annular floating body;

at least one pair of through holes penetrating through the memory cell to break the ring-shaped floating body and the channel region;

one through hole is filled with a source electrode, and the source electrode is only contacted with the channel regions at two sides; and the other through hole is filled with a drain electrode, and the drain electrode is only contacted with the channel regions at two sides.

Optionally, the method further comprises:

and the gate oxide layer is formed between the gate electrode layer and the channel region, and is annular.

Optionally, the inside of the floating body is filled with an insulator.

Optionally, the doping concentration of the channel region is lower than the doping concentration of the floating body.

Optionally, quantum dots are doped in the floating body.

Alternatively, in a direction perpendicular to the stacking direction, a plurality of the memory cells are provided, and a plurality of the memory cells are arranged at intervals, each of the memory cells corresponding to at least one pair of the through holes, and the source electrode and the drain electrode.

Optionally, in the stacking direction, the storage unit has multiple layers.

Optionally, in the case that the through holes have a plurality of pairs, one of the adjacent through holes is used for filling the source electrode, and the other through hole is used for filling the drain electrode.

Alternatively, the thicknesses of the floating body, the channel region, and the gate layer are the same in the stacking direction.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor memory device, including:

providing a substrate;

sequentially and alternately depositing a nitride layer and an oxide layer on the substrate to form a laminated structure;

etching a first through hole penetrating through the laminated structure;

etching part of the oxide layer through the first through hole to form an oxide layer groove;

sequentially depositing an annular gate oxide layer, a channel region and a floating body in the oxide layer groove;

etching at least one pair of second through holes penetrating through the laminated structure at different positions, wherein the second through holes break the annular channel region and the floating body;

filling at least one pair of the second through holes with different materials to form a source electrode and a drain electrode which are connected with the channel region;

etching a third through hole penetrating the rest laminated structure;

and etching the rest oxide layer through the third through hole, and depositing a gate material layer to form a gate layer on the outer side of the gate oxide layer.

Optionally, sequentially depositing a ring-shaped gate oxide layer, a channel region and a floating body in the oxide layer groove includes:

depositing a gate oxide layer in the oxide layer groove, wherein the annular gate oxide layer is formed on the inner side of the rest oxide layer;

depositing a channel region material layer in the first through hole, wherein the channel region material layer fills the rest oxide layer grooves;

etching part of the channel region material layer to form a ring-shaped channel region in contact with the gate oxide layer in the rest of the oxide layer grooves;

depositing a floating body material layer in the first through hole, wherein the floating body material layer fills the rest oxide layer grooves;

and etching part of the floating body material layer to form a ring-shaped floating body which is in contact with the channel region in the rest of the oxide layer groove.

Optionally, the method further comprises:

and filling an insulating material layer in the first through hole so as to fill the first through hole and the rest of the oxide layer groove.

Optionally, filling at least one pair of the second vias with different materials to form a source and a drain connecting the channel region includes:

depositing an insulating material in the second via;

etching the insulating material in the second through hole to form a fourth through hole exposing the channel region;

source material is deposited within the fourth via to form the source, or drain material is deposited within the fourth via to form the drain.

etching part of the floating body through the second through hole to form a floating body groove;

depositing an insulating material in the second through hole and filling the floating body groove;

etching the insulating material in the second through hole, and reserving the insulating material in the floating body groove;

source material is deposited within the second via to form the source, or drain material is deposited within the second via to form the drain.

Alternatively, in the case of the pair of second vias Kong Youduo, a different material is deposited within adjacent ones of the second vias.

Optionally, etching the first via through the stacked structure includes:

and etching a plurality of first through holes penetrating through the laminated structure, wherein the first through holes are arranged at intervals.

The semiconductor memory device provided by the exemplary embodiments of the present disclosure is provided by alternately stacking a nitride layer and a memory cell, and the memory cell includes a ring-shaped floating body, a channel region, and a gate layer therein, and filling a source and a drain in a pair of through holes breaking the ring-shaped floating body and the channel region. In one aspect, the broken memory cell may form at least two memory cells, and the two memory cells may share a pair of source and drain, so that the occupied area of the memory cells may be reduced. On the other hand, a plurality of layers of memory cells may be stacked in the stacking direction, and twice as many memory cells as those formed by the plurality of layers of memory cells may share the same pair of source and drain, so that the occupied area of the memory cells may be further reduced. In still another aspect, a plurality of pairs of through holes may be formed in the same memory cell, so that the ring-shaped floating body and the channel region may be broken into a plurality of segments, thereby forming more memory cells and improving the integration level of the memory cells in the semiconductor memory device. On the other hand, since the floating body is disposed inside the channel region and is not in direct contact with the source and drain, there is no leakage of charges, and thus the data retention time of the floating body is enhanced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 shows a cross-sectional view of a capacitor-less dynamic random access memory.

Fig. 2a is a schematic structural diagram of a semiconductor memory device according to an exemplary embodiment of the present disclosure.

Fig. 2b shows a schematic cross-sectional view of the semiconductor memory device provided in fig. 2a in A-A direction.

Fig. 3 is a schematic cross-sectional view of a semiconductor memory device provided with a plurality of memory cells according to an exemplary embodiment of the present disclosure.

Fig. 4 (a) -4 (l) are explanatory diagrams of manufacturing a semiconductor memory device according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.

The above described features, structures or characteristics may be combined in any suitable manner in one or more embodiments, such as the possible, interchangeable features as discussed in connection with the various embodiments. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the inventive aspects may be practiced without one or more of the specific details, or with other methods, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the application.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc. The terms "first" and "second" are used merely as labels, and are not intended to limit the number of their objects.

Referring to fig. 1, a cross-sectional view of a capacitor-less dynamic random access memory (Dynamic Random Access Memory, DRAM) is shown.

As shown in fig. 1, a gate 110 may be formed on a silicon substrate 120. The silicon substrate 120 is formed by sequentially stacking a first silicon layer 121, an oxide layer 123, and a second silicon layer 125. The gate electrode 110 is formed by sequentially stacking a gate insulating layer 111 and a gate conductive layer 113. The source 130 and the drain 140 are formed in the second silicon layer 125 at both sides of the gate 110. A floating channel body 150 electrically isolated from the first silicon layer 121 is formed in the second silicon layer 125 between the source 130 and the drain 140. The capacitor-less dynamic random access memory stores a data value of "1" or "0" by accumulating holes or electrons within the floating channel body 150.

In further research, the applicant found that there is still room for a reduction in the footprint of the memory cells in the capacitor-less dynamic random access memory described above.

Based on this, exemplary embodiments of the present disclosure provide a semiconductor memory device to further reduce the occupied area of memory cells in a capacitor-less dynamic random access memory, thereby improving the integration level of the semiconductor memory device. Referring to fig. 2 (a) and 2 (b), the semiconductor memory device may include a nitride layer 210 and a memory cell 230 alternately stacked, and at least one pair of via holes 250, wherein:

in practice, the bottom-most nitride layer 210 may be deposited on the substrate 200, and then the nitride layer 210 and the memory cell 230 are sequentially alternately deposited on the substrate 200. The nitride layer 210 may be deposited from a silicon nitride material, and the substrate 200 may be a silicon substrate, silicon germanium substrate, or the like.

In practical applications, the number of the nitride layers 210 and the storage combination units 230 can be determined according to practical needs. When there is only one layer in the memory combining unit 230, the nitride layer 210 may have two layers; when the memory cell 230 has a plurality of layers, the nitride layer 210 may be provided one more layer than the memory cell 230. The exemplary embodiments of the present disclosure are not particularly limited as to the number of storage unit combinations 230.

In the exemplary embodiment of the present disclosure, the memory cell 230 includes a gate layer 231, a gate oxide layer 232, a channel region 233, and a floating body 234, wherein the gate layer 231 is located at the outermost layer of the memory cell 230 in a direction perpendicular to the stacking direction, the channel region 233 is annular inside the gate layer 231, and the floating body 234 is annular inside the annular channel region 233.

From the standpoint of storing data, the floating body 234 corresponds to a hole storage unit, and the floating body 234 is a heavily doped semiconductor structure, for example, a semiconductor silicon is doped with more chromium, antimony, aluminum, gallium, or other ions to increase the conductivity of the floating body 234, and the doping concentration of the floating body 234 is higher than that of the channel region 233, so that the valence band of the floating body 234 is higher than that of the channel region 233, that is, more electrons are in the floating body 234.

In the exemplary embodiments of the present disclosure, in order to further increase the number of electrons stored in the floating body 234, quantum dots may also be doped in the floating body 234. Quantum dots are semiconductor nanostructures that tie excitons in three spatial directions. One quantum dot has a small number (1-100) of electrons, holes or hole pairs, i.e. it has an electric charge that is an integer multiple of the meta-charge. Accordingly, the number of electrons in the floating body 234 may be increased by doping the quantum dots in the floating body 234.

In the exemplary embodiments of the present disclosure, the channel region 233 is obtained by simultaneously doping n-type or p-type ions while depositing a semiconductor material. Wherein the doping concentration of the channel region 233 is lower than the doping concentration of the floating body 234 such that the valence band of the floating body 234 is higher than the valence band of the channel region 233.

The semiconductor memory device provided in the exemplary embodiment of the present disclosure further includes at least one pair of via holes 250 penetrating the memory cell assembly 230 from different locations, respectively, as shown in fig. 2 (b), in order to break the ring-shaped floating body 234 and channel region 233 in the memory cell assembly 230 so that one memory cell assembly 230 is divided into two memory cells.

In addition, it is also necessary to form a source electrode 260 and a drain electrode 270 in the pair of through holes 250. One of the through holes 250 is filled with a source electrode 260, and the source electrode 260 is only in contact with the channel regions 233 at two sides and can be separated from the floating body 234 by an insulator; the other through hole 250 is filled with a drain 270, and the drain 270 is also only in contact with the channel regions 233 on both sides, and may be separated from the floating body 234 by an insulator. In this way, since the floating body 234 is not in direct contact with the source 260 and the drain 270, there is no leakage of charges, and thus the data retention time of the floating body 234 is enhanced.

To space apart two memory cells formed by one memory cell 230, an insulator 235 may be filled inside the annular floating body 234 to avoid conductive connection between the two memory cells.

As can be seen from the above-described structure, in the semiconductor memory device provided in the exemplary embodiment of the present disclosure, two memory cells formed of one memory cell 230 may share a pair of the source electrode 260 and the drain electrode 270, so that the occupied area of the memory cell may be reduced.

In addition, a plurality of memory cell combinations 230 may be stacked in the stacking direction, and twice as many memory cells as the plurality of memory cell combinations 230 may share the same pair of source 260 and drain 270, so that the occupation area of the memory cell may be further reduced.

Further, a plurality of pairs of through holes 250 may be formed in the same memory cell 230, so that the ring-shaped floating body 234 and the channel region 233 may be broken into a plurality of segments, thereby forming more memory cells and improving the integration of the memory cells in the semiconductor memory device.

In the case where there are a plurality of pairs of the through holes 250, when one through hole 250 is used to fill the source electrode 260, the other through hole 250 needs to fill the drain electrode 270 in the adjacent through holes 250.

Referring to fig. 3, in practical applications, a plurality of memory cells 230 may be provided in a direction perpendicular to the stacking direction to increase the integration of memory cells in the semiconductor memory device. Wherein the plurality of storage combination units 230 need to be arranged at intervals.

In practical use, for ease of processing, the thicknesses of the floating body 234, the channel region 233, and the gate layer 231 are the same in the stacking direction, and the floating body 234 and the gate layer 231 are located on both sides of the channel region 233, separated by the channel region 233. The specific thicknesses of the floating body 234, the channel region 233, and the gate layer 231 are not particularly limited in the exemplary embodiments of the present disclosure.

A method of manufacturing a semiconductor memory device in an exemplary embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

It should be appreciated that the drawings are not drawn to scale from actual device structures for purposes of illustrating process effects.

In an exemplary embodiment of the present disclosure, the main manufacturing process steps of the semiconductor memory device are as follows:

step 10, providing a substrate;

step 20, alternately depositing a nitride layer and an oxide layer on the substrate in turn to form a laminated structure;

step 30, etching a first through hole penetrating through the laminated structure;

step 40, etching part of the oxide layer through the first through hole to form an oxide layer groove;

step 50, sequentially depositing an annular gate oxide layer, a channel region and a floating body in the oxide layer groove;

step 60, etching at least one pair of second through holes penetrating through the laminated structure at different positions, wherein the second through holes break the annular channel region and the floating body;

step 70, filling different materials in at least one pair of second through holes to form a source electrode and a drain electrode connected with the channel region;

step 80, etching a third through hole penetrating through the rest of the laminated structure;

step 90, etching the remaining oxide layer through the third via hole, and depositing a gate material layer to form a gate layer outside the gate oxide layer.

The manufacturing process of the semiconductor memory device will be described by a specific implementation method.

Specifically, the manufacturing process of the semiconductor memory device includes the following steps:

as shown in fig. 4 (a), a substrate 200 is provided, and nitride layers 210 and oxide layers 410 are sequentially and alternately deposited on the surface of the substrate 200 to form a stacked structure. The substrate 200 may be a silicon substrate, a germanium-silicon substrate, a doped silicon substrate, or the like. Nitride layer 210 may be deposited from silicon nitride and oxide layer 410 may be deposited from silicon oxide.

In practical applications, the cross-sectional shape of the substrate 200 may be circular, rectangular, square, or the like, to which the exemplary embodiments of the present disclosure are not particularly limited.

As shown in fig. 4 (b), the first via 420 is etched through the stack, for example, by means of a patterned etch. The first via 420 needs to penetrate through at least all of the oxide layer 410, and may also penetrate through the entire stacked structure to leak out of the substrate 200. In addition, in order to protect the laminate structure during etching, an abrasive layer 430 may also be provided on top of the laminate structure. The shape of the first through hole 420 is determined by the shape of the patterned mask layer, and the specific shape of the patterned mask layer can be determined according to the actual situation, which is not described herein.

In addition, it should be noted that, in the deposited stacked structure, the bottom layer and the top layer are both the nitride layer 210 for protecting the oxide layer 410.

As shown in fig. 4 (c), an etching material is determined according to the etching selectivity of the nitride layer 210 and the oxide layer 410, and the etching material is introduced into the first via hole 420 to etch a portion of the oxide layer 410 through the first via hole 420, thereby forming an oxide layer recess 440.

As shown in fig. 4 (d), a gate oxide material is deposited in the oxide layer recess 440 by atomic layer deposition or the like to form a ring-shaped gate oxide layer 232 deposited inside the oxide layer 410.

As shown in fig. 4 (e), a channel region material layer is deposited in the oxide layer recess 440 through the first via 420, the channel region material layer filling the remaining oxide layer recess 440. The material of the channel region material layer can be a semiconductor material, and n-type or p-type ions can be added in situ at the same time when the semiconductor material is deposited to form a semiconductor conductive channel.

Next, a portion of the channel region material layer is etched through the first via 420 to form a ring-shaped channel region 233 in contact with the gate oxide layer 232 in the remaining oxide layer recess 440, the channel region 233 being located inside the gate oxide layer 232. In the process of etching part of the channel region material layer, a dry etching process, a self-aligned etching process and the like can be adopted.

As shown in fig. 4 (f), a floating body material layer is deposited in the oxide layer recess 440 through the first via 420, the floating body material layer filling the oxide layer recess 440. The material for depositing the floating body material layer may be a semiconductor material, a metal material, or the like. In addition, quantum dots can be added into the material of the floating body material layer to store more electrons.

Next, a portion of the floating body material layer is etched through the first via 420 to form a ring-shaped floating body 234 inside the channel region 233 in the oxide layer recess 440. In the process of etching part of the floating body material layer, a dry etching process, a self-aligned etching process and the like can be adopted.

Fig. 4 (g) shows a cross-sectional view of the semiconductor memory device shown in fig. 4 (f) in the B-B direction, and as can be seen from fig. 4 (g), the gate oxide layer 232, the channel region 233, and the floating body 234 are formed in a ring shape.

In addition, it is also necessary to fill the first via 420 with a layer of insulating material as shown in fig. 4 (g) to fill the first via 420 and the remaining oxide layer recess 440, forming the insulator 235 filled inside the annular floating body 234.

As shown in fig. 4 (h), at least one pair of second through holes 450 penetrating the above-mentioned stacked structure are etched at different positions, and the second through holes 450 break the annular channel region 233 and the floating body 234.

The process of filling at least one pair of second vias 450 with different materials to form a source 260 and drain 270 connecting channel regions 233 is described in two different ways:

the first way is: as shown in fig. 4 (i), an insulating material is deposited in the second via 450, and the insulating material in the second via 450 is patterned etched to form a fourth via 460 exposing the channel region 233. Source material is deposited in the fourth via 460 to form the source 260 and drain material is deposited in the other fourth via 460 to form the drain 270.

Another way is: as shown in fig. 4 (j), a portion of the floating body 234 is etched through the second via 450 based on the etching ratio, forming a floating body groove 470; an insulating material is deposited in the second via 450 and fills the floating body recess 470. Etching the insulating material in the second via 450, leaving the insulating material in the floating body recess 470; source material is deposited in the second via 450 to form the source 260 and drain material is deposited in the other second via 450 to form the drain 270.

Finally, the remaining oxide layer 410 in the stack is removed using a patterned etch, e.g., as shown in fig. 4 (k), a third via 480 may be etched through the remaining stack; the remaining oxide layer 410 is etched through the third via 480 and a gate material layer is deposited to form a gate layer 231 outside the gate oxide layer 232, wherein the gate layer 231 may be metal, polysilicon, or the like. The number and positions of the third through holes 480 may be set according to actual needs, and are not particularly limited herein.

In practical applications, as shown in fig. 4 (l), there may be a plurality of pairs of second through holes 450, and the plurality of second through holes 450 may be disposed at intervals on a circumference centered on the first through hole 420. Adjacent two of the second vias 450 have different materials deposited therein to form a source 260 and a drain 270.

For a semiconductor memory device, a plurality of first vias 420 may be etched through the stacked structure to form a structure including a plurality of memory cells as shown in fig. 3.

The method for manufacturing the semiconductor memory device according to the exemplary embodiment of the present disclosure is merely illustrative, and the manufacturing process of each component is not limited in this disclosure.

It should be understood that, in various embodiments of the present disclosure, the sequence number of each process described above does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the exemplary embodiments of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A semiconductor memory device, comprising:

alternately stacking nitride layers and memory combination units; the outer layer of the storage combination unit is a gate layer, the inner side of the gate layer is an annular channel region, the inner side of the channel region is an annular floating body, and the floating body is a hole storage unit;

2. The semiconductor memory device according to claim 1, further comprising:

3. The semiconductor memory device according to claim 2, wherein an inside of the floating body is filled with an insulator.

4. The semiconductor memory device according to claim 1, wherein a doping concentration of the channel region is lower than a doping concentration of the floating body.

5. The semiconductor memory device according to claim 4, wherein the floating body is doped with quantum dots.

6. The semiconductor memory device according to claim 1, wherein a plurality of the memory cells are provided in a direction perpendicular to the stacking direction, a plurality of the memory cells are provided at intervals, each of the memory cells corresponds to at least one pair of the through holes, and the source electrode and the drain electrode.

7. The semiconductor memory device according to claim 1, wherein the memory cell has a plurality of layers in a stacking direction.

8. The semiconductor memory device according to claim 6, wherein in the case where the through holes have a plurality of pairs, one of the adjacent through holes is used to fill the source electrode, and the other is used to fill the drain electrode.

9. The semiconductor memory device according to any one of claims 1 to 8, wherein thicknesses of the floating body, the channel region, and the gate layer are the same in a stacking direction.

10. A method of manufacturing a semiconductor memory device, comprising:

providing a substrate;

etching a first through hole penetrating through the laminated structure;

sequentially depositing an annular gate oxide layer, a channel region and a floating body in the oxide layer groove, wherein the floating body is a hole storage unit;

etching a third through hole penetrating the rest laminated structure;

11. The method of manufacturing a semiconductor memory device according to claim 10, wherein sequentially depositing a ring-shaped gate oxide layer, a channel region, and a floating body in the oxide layer recess comprises:

12. The method for manufacturing a semiconductor memory device according to claim 11, further comprising:

13. The method of manufacturing a semiconductor memory device according to claim 10, wherein filling at least one pair of the second via holes with different materials to form a source electrode and a drain electrode connected to the channel region comprises:

depositing an insulating material in the second via;

14. The method of manufacturing a semiconductor memory device according to claim 10, wherein filling at least one pair of the second via holes with different materials to form a source electrode and a drain electrode connected to the channel region comprises:

15. The method of manufacturing a semiconductor memory device according to claim 10, wherein in the case of the pair of second vias Kong Youduo, different materials are deposited in adjacent ones of the second vias.

16. The method of manufacturing a semiconductor memory device according to any one of claims 10 to 15, wherein etching the first via through the stacked structure comprises: