CN113488469A - Semiconductor memory device and method of manufacturing the same - Google Patents
Semiconductor memory device and method of manufacturing the same Download PDFInfo
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- CN113488469A CN113488469A CN202110771803.7A CN202110771803A CN113488469A CN 113488469 A CN113488469 A CN 113488469A CN 202110771803 A CN202110771803 A CN 202110771803A CN 113488469 A CN113488469 A CN 113488469A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
The disclosure provides a semiconductor storage device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes: nitride layers and memory combination units which are alternately stacked; the outer layer of the storage combination unit is a grid layer, the inner side of the grid layer is an annular channel region, and the inner side of the channel region is an annular floating body; at least one pair of through holes respectively penetrating through the memory combination units to break the annular floating body and the channel region; in at least one pair of through holes, a source electrode is filled in one through hole and only contacts with the channel regions on two sides; the other through hole is filled with a drain electrode, and the drain electrode is only contacted with the channel regions on two sides. The present disclosure can improve the integration of a semiconductor memory device.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor memory device and a method for manufacturing the same.
Background
In order to satisfy consumer demands for superior performance and low price, high integration is a development direction of semiconductor memory devices. Generally, the degree of integration is determined by the area occupied by a unit cell.
In order to increase the integration level, a capacitor-less memory cell is proposed which can greatly reduce the area occupied by the memory cell, based on a conventional memory cell having one transistor and one capacitor.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcoming the above-mentioned deficiencies in the prior art and providing a semiconductor memory device and a method for fabricating the same, which can improve the integration of the semiconductor memory device.
According to an aspect of the present disclosure, there is provided a semiconductor memory device including:
nitride layers and memory combination units which are alternately stacked; the outer layer of the memory combination unit is a grid layer, the inner side of the grid layer is an annular channel region, and the inner side of the channel region is an annular floating body;
at least one pair of through holes respectively penetrating through the storage combination units so as to break the annular floating body and the channel region;
in the at least one pair of through holes, a source electrode is filled in one through hole and only contacts with the channel regions on two sides; and the other through hole is filled with a drain electrode, and the drain electrode is only contacted with the channel regions on two sides.
Optionally, the method further includes:
and the gate oxide layer is formed between the gate layer and the channel region and is annular.
Optionally, the floating body is filled with an insulator.
Optionally, the doping concentration of the channel region is lower than that of the floating body.
Optionally, the floating body is doped with quantum dots.
Optionally, in a direction perpendicular to the stacking direction, there are a plurality of the memory combination units, the plurality of memory combination units are arranged at intervals, and each memory combination unit corresponds to at least one pair of the through holes, the source and the drain.
Optionally, in the stacking direction, the memory combination unit has multiple layers.
Optionally, when there are multiple pairs of the through holes, one of the through holes is used to fill the source, and the other through hole is used to fill the drain.
Optionally, in the stacking direction, thicknesses of the floating body, the channel region, and the gate layer are the same.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor memory device, including:
providing a substrate;
depositing nitride layers and oxide layers on the substrate in sequence and alternately to form a laminated structure;
etching a first through hole penetrating through the laminated structure;
etching part of the oxide layer through the first through hole to form an oxide layer groove;
depositing an annular gate oxide layer, a channel region and a floating body in the oxide layer groove in sequence;
etching at least one pair of second vias through the stacked structure at different locations, the second vias breaking the annular channel region and the floating body;
filling different materials in at least one pair of the second through holes to form a source electrode and a drain electrode which are connected with the channel region;
etching a third through hole penetrating through the rest laminated structure;
and etching the rest of the oxide layer through the third through hole, and depositing a gate material layer to form a gate layer on the outer side of the gate oxide layer.
Optionally, depositing an annular gate oxide layer, a channel region and a floating body in the oxide layer groove in sequence includes:
depositing a gate oxide layer in the oxide layer groove, wherein the annular gate oxide layer is formed on the inner side of the rest oxide layer;
depositing a channel region material layer in the first through hole, wherein the channel region material layer is filled in the rest of the oxide layer groove;
etching part of the channel region material layer to form an annular channel region in contact with the gate oxide layer in the rest of the oxide layer groove;
depositing a floating body material layer in the first through hole, wherein the floating body material layer is filled in the rest oxide layer groove;
and etching part of the floating body material layer to form an annular floating body which is in contact with the channel region in the rest of the oxide layer groove.
Optionally, the method further includes:
and filling an insulating material layer in the first through hole to fill the first through hole and the rest of the oxide layer groove.
Optionally, filling different materials in at least one pair of the second through holes to form a source and a drain connected to the channel region includes:
depositing an insulating material within the second via;
etching the insulating material in the second through hole to form a fourth through hole exposing the channel region;
and depositing a source material in the fourth through hole to form the source, or depositing a drain material in the fourth through hole to form the drain.
Optionally, filling different materials in at least one pair of the second through holes to form a source and a drain connected to the channel region includes:
etching part of the floating body through the second through hole to form a groove of the floating body;
depositing an insulating material in the second through hole and filling the floating body groove;
etching the insulating material in the second through hole, and reserving the insulating material in the groove of the floating body;
depositing a source material within the second via to form the source, or depositing a drain material within the second via to form the drain.
Optionally, in a case where there are a plurality of pairs of the second through holes, different materials are deposited in adjacent second through holes.
Optionally, etching the first through hole penetrating through the stacked structure includes:
and etching a plurality of first through holes penetrating through the laminated structure, wherein the first through holes are arranged at intervals.
The semiconductor memory device according to the exemplary embodiment of the present disclosure includes a nitride layer and a memory combination unit alternately stacked, and the memory combination unit includes an annular floating body, a channel region, and a gate layer, and a source and a drain are filled in a pair of via holes breaking the annular floating body and the channel region. On one hand, the broken storage combination unit can form at least two storage units, and the two storage units can share one pair of source and drain, so that the occupied area of the storage unit can be reduced. On the other hand, a plurality of layers of memory combination units can be stacked in the stacking direction, and twice memory units formed by the plurality of layers of memory combination units can share the same pair of source and drain, so that the occupied area of the memory unit can be further reduced. On the other hand, a plurality of pairs of through holes can be arranged in the same storage combination unit, so that the annular floating body and the channel region can be broken into a plurality of sections, more storage units can be formed, and the integration level of the storage units in the semiconductor storage device is improved. On the other hand, since the floating body is disposed inside the channel region and does not directly contact with the source and the drain, there is no charge leakage, and thus, the data retention time of the floating body is enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 shows a cross-sectional view of a capacitorless dynamic random access memory.
Fig. 2a is a schematic structural diagram of a semiconductor memory device according to an exemplary embodiment of the present disclosure.
Fig. 2b shows a schematic cross-sectional view of the semiconductor memory device provided in fig. 2a in the direction a-a.
Fig. 3 is a schematic cross-sectional view of a semiconductor memory device provided with a plurality of memory combination units according to an exemplary embodiment of the present disclosure.
Fig. 4(a) -4 (l) are explanatory views of fabricating a semiconductor memory device according to an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," "at least one," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
Referring to FIG. 1, a cross-sectional view of a capacitorless Dynamic Random Access Memory (DRAM) is shown.
As shown in fig. 1, a gate 110 may be formed on a silicon substrate 120. The silicon substrate 120 is formed by sequentially stacking a first silicon layer 121, an oxide layer 123, and a second silicon layer 125. The gate electrode 110 is formed by sequentially stacking a gate insulating layer 111 and a gate conductive layer 113. Source 130 and drain 140 are formed in second silicon layer 125 on either side of gate 110. A floating channel body 150 electrically isolated from the first silicon layer 121 is formed in the second silicon layer 125 between the source 130 and the drain 140. The capacitorless dynamic random access memory stores a data value of "1" or "0" by accumulating holes or electrons within the floating channel body 150.
In further studies, the applicant has found that the occupied area of the memory cell in the above capacitor-less dram still has a reduced space.
Based on this, exemplary embodiments of the present disclosure provide a semiconductor memory device to further reduce a footprint of a memory cell in a capacitorless dynamic random access memory, thereby improving an integration level of the semiconductor memory device. Referring to fig. 2(a) and 2(b), the semiconductor memory device may include nitride layers 210 and memory combination units 230 alternately stacked, and at least one pair of vias 250, wherein:
in practice, the bottom nitride layer 210 may be deposited on the substrate 200, and then the nitride layer 210 and the memory combination unit 230 are alternately deposited on the substrate 200 in sequence. The nitride layer 210 may be deposited from a silicon nitride material, and the substrate 200 may be a silicon substrate, a silicon germanium substrate, or the like.
In practical applications, the number of the nitride layer 210 and the memory combination unit 230 can be determined according to practical requirements. When the memory cell 230 has only one layer, the nitride layer 210 may have two layers; when the memory cell 230 has a plurality of layers, the nitride layer 210 may be disposed one more layer than the memory cell 230. The exemplary embodiment of the present disclosure does not particularly limit the number of the storage combination units 230.
In the exemplary embodiment of the present disclosure, the memory combination unit 230 includes a gate layer 231, a gate oxide layer 232, a channel region 233 and a floating body 234, wherein the gate layer 231 is located at the outermost layer of the memory combination unit 230 in a direction perpendicular to the stacking direction, the channel region 233 is in an annular shape inside the gate layer 231, and the floating body 234 is in an annular shape inside the channel region 233.
From the viewpoint of data storage, the floating body 234 corresponds to a hole storage unit, the floating body 234 is a heavily doped semiconductor structure, for example, the semiconductor silicon is doped with more ions of cr, sb, al, ga, etc. to increase the conductivity of the floating body 234, and the doping concentration of the floating body 234 is higher than that of the channel region 233, so that the valence band of the floating body 234 is higher than that of the channel region 233, that is, more electrons are in the floating body 234.
In the exemplary embodiment of the present disclosure, in order to further increase the number of electrons stored in the floating body 234, quantum dots may be further doped in the floating body 234. Quantum dots are semiconductor nanostructures that confine excitons in three spatial directions. One quantum dot has a small number (1-100) of electrons, holes or electron-hole pairs, i.e., the charge is an integer multiple of the elementary charge. Therefore, the number of electrons in the floating body 234 can be increased by doping quantum dots in the floating body 234.
In the exemplary embodiment of the present disclosure, the channel region 233 is obtained by simultaneously doping n-type or p-type ions while depositing a semiconductor material. Wherein the doping concentration to the channel region 233 is lower than the doping concentration to the floating body 234 so that the valence band of the floating body 234 is higher than the valence band of the channel region 233.
The semiconductor memory device provided by the exemplary embodiment of the present disclosure further includes at least one pair of vias 250, and the pair of vias 250 respectively penetrate the memory combination unit 230 from different positions, as shown in fig. 2(b), in order to break the floating body 234 and the channel region 233 in a ring shape in the memory combination unit 230, so that one memory combination unit 230 is divided into two memory cells.
In addition, it is also necessary to form a source electrode 260 and a drain electrode 270 in the pair of via holes 250. One of the vias 250 is filled with a source 260, the source 260 contacts only the channel region 233 at both sides, and is spaced apart from the floating body 234 by an insulator; the other via 250 is filled with a drain 270, and the drain 270 is only in contact with the channel region 233 on both sides and is separated from the floating body 234 by an insulator. Thus, since the floating body 234 is not in direct contact with the source 260 and the drain 270, there is no charge leakage, and thus, the data retention time of the floating body 234 is enhanced.
In order to separate two memory cells formed by one memory combination cell 230, an insulator 235 may be filled inside the ring-shaped floating body 234 to prevent a conductive connection between the two memory cells.
As can be seen from the above structure, in the semiconductor memory device provided in the exemplary embodiment of the present disclosure, two memory cells formed by one memory combination cell 230 may share one pair of the source 260 and the drain 270, so that the occupied area of the memory cell may be reduced.
In addition, a plurality of layers of the memory combination units 230 may be stacked in the stacking direction, and twice as many memory units formed by the plurality of layers of the memory combination units 230 may share the same pair of the source 260 and the drain 270, so that the occupied area of the memory unit may be further reduced.
Furthermore, a plurality of pairs of through holes 250 can be arranged in the same memory combination unit 230, so that the annular floating body 234 and the channel region 233 can be broken into a plurality of sections, thereby forming more memory units and improving the integration level of the memory units in the semiconductor memory device.
In the case of multiple pairs of vias 250, one via 250 of adjacent vias 250 is used to fill the source 260, and the other via 250 is required to fill the drain 270.
Referring to fig. 3, in practical applications, a plurality of memory combination units 230 may be further disposed in a direction perpendicular to the stacking direction to increase the integration of the memory units in the semiconductor memory device. Wherein these plurality of memory combination units 230 need to be arranged at intervals.
In practical applications, floating body 234, channel region 233 and gate layer 231 have the same thickness in the stacking direction for ease of processing, and floating body 234 and gate layer 231 are located on both sides of channel region 233, separated by channel region 233. The present exemplary embodiment is not particularly limited with respect to specific thicknesses of floating body 234, channel region 233, and gate layer 231.
The semiconductor memory device according to the exemplary embodiment of the present disclosure includes a nitride layer and a memory combination unit alternately stacked, and the memory combination unit includes an annular floating body, a channel region, and a gate layer, and a source and a drain are filled in a pair of via holes breaking the annular floating body and the channel region. On one hand, the broken storage combination unit can form at least two storage units, and the two storage units can share one pair of source and drain, so that the occupied area of the storage unit can be reduced. On the other hand, a plurality of layers of memory combination units can be stacked in the stacking direction, and twice memory units formed by the plurality of layers of memory combination units can share the same pair of source and drain, so that the occupied area of the memory unit can be further reduced. On the other hand, a plurality of pairs of through holes can be arranged in the same storage combination unit, so that the annular floating body and the channel region can be broken into a plurality of sections, more storage units can be formed, and the integration level of the storage units in the semiconductor storage device is improved. On the other hand, since the floating body is disposed inside the channel region and does not directly contact with the source and the drain, there is no charge leakage, and thus, the data retention time of the floating body is enhanced.
A method of fabricating a semiconductor memory device in exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
It is to be understood that the drawings are not to scale of actual device structures in order to illustrate process effects.
In the exemplary embodiment of the present disclosure, the main manufacturing process steps of the semiconductor memory device are as follows:
step 20, depositing a nitride layer and an oxide layer on the substrate in sequence and alternately to form a laminated structure;
step 30, etching a first through hole penetrating through the laminated structure;
step 40, etching part of the oxide layer through the first through hole to form an oxide layer groove;
step 50, depositing an annular gate oxide layer, a channel region and a floating body in the groove of the oxide layer in sequence;
step 60, etching at least one pair of second through holes penetrating through the laminated structure at different positions, wherein the second through holes break the annular channel region and the floating body;
step 70, filling different materials in at least one pair of second through holes to form a source electrode and a drain electrode which are connected with a channel region;
step 80, etching a third through hole penetrating through the rest laminated structure;
and step 90, etching the rest of the oxide layer through the third through hole, and depositing a gate material layer to form a gate layer on the outer side of the gate oxide layer.
The manufacturing process of the semiconductor memory device will be described below by way of a specific implementation method.
Specifically, the manufacturing process of the semiconductor memory device comprises the following steps:
as shown in fig. 4(a), a substrate 200 is provided, and a nitride layer 210 and an oxide layer 410 are sequentially and alternately deposited on the surface of the substrate 200 to form a stacked structure. The substrate 200 may be a silicon substrate, a silicon germanium substrate, a doped silicon substrate, or the like. The nitride layer 210 may be deposited from silicon nitride and the oxide layer 410 may be deposited from silicon oxide.
In practical applications, the cross-sectional shape of the substrate 200 may be circular, rectangular, square, or the like, and the exemplary embodiment of the present disclosure is not particularly limited in this regard.
As shown in fig. 4(b), a first via 420 is etched through the stacked structure, for example, by means of a patterned etch. The first via 420 needs to penetrate through at least all of the oxide layer 410, and may also penetrate through the entire stack structure to leak out of the substrate 200. In addition, a polishing layer 430 may also be disposed on top of the stacked structure in order to protect the stacked structure during etching. The shape of the first through hole 420 is determined by the shape of the patterned mask layer, and the specific shape of the patterned mask layer may be determined according to actual conditions, which is not described herein again.
It should be noted that the deposited stack structure needs to have the nitride layer 210 at the bottom and top to protect the oxide layer 410.
As shown in fig. 4(c), an etching material is determined according to the etching selection ratio of the nitride layer 210 and the oxide layer 410, and the etching material is introduced into the first via 420 to etch a portion of the oxide layer 410 through the first via 420, thereby forming an oxide layer recess 440.
As shown in fig. 4(d), atomic layer deposition or the like is used to deposit a gate oxide material in the oxide layer groove 440 to form a ring-shaped gate oxide layer 232 deposited on the inner side of the oxide layer 410.
As shown in fig. 4(e), a channel region material layer is deposited in the oxide layer recess 440 through the first via 420, and the channel region material layer fills the remaining oxide layer recess 440. The material for depositing the channel region material layer may be a semiconductor material, and when the semiconductor material is deposited, n-type or p-type ions may be added in situ at the same time to form a semiconductor conductive channel.
Next, a portion of the channel region material layer is etched through the first via 420 to form a ring-shaped channel region 233 in contact with the gate oxide layer 232 in the remaining oxide layer recess 440, wherein the channel region 233 is located at the inner side of the gate oxide layer 232. In the process of etching part of the channel region material layer, a dry etching process can be adopted, and a self-aligned etching process can also be adopted.
As shown in fig. 4(f), a floating body material layer is deposited in the oxide layer recess 440 through the first via 420, and the floating body material layer fills the oxide layer recess 440. The material for depositing the floating body material layer may be a semiconductor material, a metal material, or the like. In addition, quantum dots can be added into the material of the floating body material layer to store more electrons.
Next, a portion of the floating body material layer is etched through the first via 420 to form a ring-shaped floating body 234 inside the channel region 233 in the oxide layer recess 440. In the process of etching part of the floating body material layer, a dry etching process can be adopted, and a self-aligned etching process and the like can also be adopted.
Fig. 4(g) shows a cross-sectional view of the semiconductor memory device shown in fig. 4(f) in the B-B direction, and as can be seen from fig. 4(g), the gate oxide layer 232, the channel region 233, and the floating body 234 are formed in a ring shape.
In addition, it is also necessary to fill the first via 420 shown in fig. 4(g) with an insulating material layer to fill the first via 420 and the remaining oxide layer recess 440, so as to form the insulator 235 filled inside the ring-shaped floating body 234.
As shown in fig. 4(h), at least one pair of second vias 450 are etched through the stacked structure at different locations, the second vias 450 interrupting the annular channel region 233 and the floating body 234.
The process of filling different materials in at least one pair of second vias 450 to form the source 260 and drain 270 connecting the channel region 233 is described in two different ways:
the first mode is as follows: as shown in fig. 4(i), an insulating material is deposited in the second via 450, and the insulating material in the second via 450 is patterned to form a fourth via 460 exposing the channel region 233. A source material is deposited in the fourth via 460 to form the source 260 and a drain material is deposited in the other fourth via 460 to form the drain 270.
In another mode: as shown in fig. 4(j), based on the etching ratio, etching a portion of the floating body 234 through the second via 450 to form a floating body recess 470; an insulating material is deposited in the second via 450 and fills the floating body recess 470. Etching the insulating material in the second via 450, and reserving the insulating material in the floating body groove 470; a source material is then deposited in the second via 450 to form the source 260 and a drain material is deposited in the other second via 450 to form the drain 270.
Finally, the remaining oxide layer 410 in the stack is removed using a patterned etch, for example, as shown in fig. 4(k), a third via 480 may be etched through the remaining stack; through the third via 480, the remaining oxide layer 410 is etched, and a gate material layer is deposited to form a gate layer 231 outside the gate oxide layer 232, wherein the gate layer 231 may be a metal, a polysilicon, or the like. The number and position of the third through holes 480 may be set according to actual needs, and are not particularly limited herein.
In practical applications, as shown in fig. 4(l), there may be multiple pairs of the second through holes 450, and the multiple second through holes 450 may be arranged at intervals on a circumference centered on the first through hole 420. Different materials are deposited in two adjacent second vias 450 to form the source 260 and drain 270.
For a semiconductor memory device, a plurality of first vias 420 may be etched through the stacked structure to form a structure including a plurality of memory cells as shown in fig. 3.
It should be noted that the method for manufacturing a semiconductor memory device according to the exemplary embodiment of the present disclosure is merely an exemplary illustration, and the manufacturing process of each component in the present disclosure is not limited thereto.
It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not imply the order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the exemplary embodiments of the present disclosure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (16)
1. A semiconductor memory device, comprising:
nitride layers and memory combination units which are alternately stacked; the outer layer of the memory combination unit is a grid layer, the inner side of the grid layer is an annular channel region, and the inner side of the channel region is an annular floating body;
at least one pair of through holes respectively penetrating through the storage combination units so as to break the annular floating body and the channel region;
in the at least one pair of through holes, a source electrode is filled in one through hole and only contacts with the channel regions on two sides; and the other through hole is filled with a drain electrode, and the drain electrode is only contacted with the channel regions on two sides.
2. The semiconductor storage device according to claim 1, further comprising:
and the gate oxide layer is formed between the gate layer and the channel region and is annular.
3. The semiconductor memory device according to claim 2, wherein an inside of the floating body is filled with an insulator.
4. The semiconductor memory device according to claim 1, wherein a doping concentration of the channel region is lower than a doping concentration of the floating body.
5. The semiconductor memory device according to claim 4, wherein the floating body is doped with quantum dots.
6. The semiconductor memory device according to claim 1, wherein a plurality of the memory combination cells are arranged at intervals in a direction perpendicular to the stacking direction, each of the memory combination cells corresponds to at least one pair of the through holes, and the source and the drain.
7. The semiconductor memory device according to claim 1, wherein the memory combination unit has a plurality of layers in a stacking direction.
8. The semiconductor memory device according to claim 6, wherein in the case where there are a plurality of pairs of the vias, one of the vias adjacent to each other is used to fill the source electrode, and the other via is used to fill the drain electrode.
9. The semiconductor memory device according to any one of claims 1 to 8, wherein thicknesses of the floating body, the channel region, and the gate layer are the same in a stacking direction.
10. A method of fabricating a semiconductor memory device, comprising:
providing a substrate;
depositing nitride layers and oxide layers on the substrate in sequence and alternately to form a laminated structure;
etching a first through hole penetrating through the laminated structure;
etching part of the oxide layer through the first through hole to form an oxide layer groove;
depositing an annular gate oxide layer, a channel region and a floating body in the oxide layer groove in sequence;
etching at least one pair of second vias through the stacked structure at different locations, the second vias breaking the annular channel region and the floating body;
filling different materials in at least one pair of the second through holes to form a source electrode and a drain electrode which are connected with the channel region;
etching a third through hole penetrating through the rest laminated structure;
and etching the rest of the oxide layer through the third through hole, and depositing a gate material layer to form a gate layer on the outer side of the gate oxide layer.
11. The method of claim 10, wherein sequentially depositing a gate oxide layer, a channel region and a floating body in a ring shape in the oxide layer recess comprises:
depositing a gate oxide layer in the oxide layer groove, wherein the annular gate oxide layer is formed on the inner side of the rest oxide layer;
depositing a channel region material layer in the first through hole, wherein the channel region material layer is filled in the rest of the oxide layer groove;
etching part of the channel region material layer to form an annular channel region in contact with the gate oxide layer in the rest of the oxide layer groove;
depositing a floating body material layer in the first through hole, wherein the floating body material layer is filled in the rest oxide layer groove;
and etching part of the floating body material layer to form an annular floating body which is in contact with the channel region in the rest of the oxide layer groove.
12. The method for manufacturing a semiconductor memory device according to claim 11, further comprising:
and filling an insulating material layer in the first through hole to fill the first through hole and the rest of the oxide layer groove.
13. The method of claim 10, wherein filling at least one pair of the second vias with different materials to form a source and a drain connecting the channel region comprises:
depositing an insulating material within the second via;
etching the insulating material in the second through hole to form a fourth through hole exposing the channel region;
and depositing a source material in the fourth through hole to form the source, or depositing a drain material in the fourth through hole to form the drain.
14. The method of claim 10, wherein filling at least one pair of the second vias with different materials to form a source and a drain connecting the channel region comprises:
etching part of the floating body through the second through hole to form a groove of the floating body;
depositing an insulating material in the second through hole and filling the floating body groove;
etching the insulating material in the second through hole, and reserving the insulating material in the groove of the floating body;
depositing a source material within the second via to form the source, or depositing a drain material within the second via to form the drain.
15. The method of manufacturing a semiconductor memory device according to claim 10, wherein different materials are deposited in adjacent second through holes in the case where there are a plurality of pairs of the second through holes.
16. The method of manufacturing a semiconductor memory device according to any one of claims 10 to 15, wherein etching a first via hole penetrating the stacked structure includes:
and etching a plurality of first through holes penetrating through the laminated structure, wherein the first through holes are arranged at intervals.
Priority Applications (1)
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