CN113484737A - Signal adjusting unit, signal adjusting module and testing machine - Google Patents
Signal adjusting unit, signal adjusting module and testing machine Download PDFInfo
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- CN113484737A CN113484737A CN202111048233.5A CN202111048233A CN113484737A CN 113484737 A CN113484737 A CN 113484737A CN 202111048233 A CN202111048233 A CN 202111048233A CN 113484737 A CN113484737 A CN 113484737A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a signal adjusting unit, a signal adjusting module and a testing machine, wherein the signal adjusting unit comprises a control end which comprises an analog linkage switch; the signal adjusting circuit comprises a field effect transistor and an SRD diode; the node is connected with the output end; when the output signal is a rising edge pulse signal or a falling edge pulse signal, a control instruction is given to the analog linkage switch, so that the analog linkage switch is switched to a working state from an initial standby state, the field effect tube is conducted, the SRD diode is in a state that positive bias is converted into negative bias and strong reverse current is formed, and after all minority carriers of the SRD diode are extracted, the reverse current of the SRD diode is instantly cut off, and the rising edge step pulse signal or the falling edge step pulse signal of the high-voltage slew rate is realized on a node. The invention utilizes the SRD diode and the field effect transistor to adjust the slew rate of the output signal of the test channel, so that the slew rate is higher.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a signal adjusting unit, a signal adjusting module and a testing machine.
Background
In an automatic testing machine of an integrated circuit, an output end of a testing channel in the prior art is usually a push-pull output driving circuit of an amplifier, and due to internal resistance and parasitic capacitance of the circuit, the slew rate of an output signal is not high enough, namely the voltage conversion rate is low and is usually in the order of 1V/mus or less, but in some cases, a corresponding situation of a chip to be tested to a higher voltage change needs to be tested, and a signal excitation with a higher slew rate needs to be provided, so that a technology for improving the slew rate is necessary.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the deficiencies in the prior art, and to provide a signal adjusting unit, a signal adjusting module and a testing machine, which can provide signal excitation with a higher slew rate.
In order to solve the above technical problem, the present invention provides a signal adjusting unit for adjusting a slew rate of an output signal of a test channel, comprising:
a control terminal including a plurality of analog interlock switches;
the signal adjusting circuit comprises a field effect transistor and an SRD diode, the field effect transistor is connected with the SRD diode in series, the field effect transistor is connected with one of the analog linkage switches, the SRD diode is connected with the other analog linkage switch, and the output signal of the test channel is adjusted into a step pulse signal by using the SRD diode;
a node connected to an output of the test channel;
when the output signal is a rising edge pulse signal or a falling edge pulse signal, a control instruction is given to the analog gang switch, so that the analog gang switch is switched from an initial standby state to a working state, the field effect tube is conducted, the SRD diode is in a state of converting positive bias into negative bias and forming strong reverse current, and after all minority carriers of the SRD diode are extracted, the reverse current of the SRD diode is cut off instantly, and the rising edge step pulse signal or the falling edge step pulse signal with high voltage swing rate is realized on the node.
In an embodiment of the present invention, after the rising edge step pulse signal or the falling edge step pulse signal of the high voltage slew rate is implemented on the node, a control instruction is given to the analog ganged switch, so that the analog ganged switch is switched from the working state to the initial standby state, so as to turn off the field-effect transistor, and thus the SRD diode is in a state of forward bias and storing minority carrier charges.
In an embodiment of the present invention, a gate of the field effect transistor is connected to a moving terminal of one of the analog ganged switches, a series connection point of the SRD diode and the field effect transistor is connected to a moving terminal of another one of the analog ganged switches, and fixed terminals of the analog ganged switches are respectively connected to different dc bias voltages or are suspended.
In one embodiment of the present invention, the signal conditioning circuit further comprises a current limiting resistor disposed between the analog ganged switch and the SRD diode.
In an embodiment of the present invention, when the output signal is a rising edge pulse signal, the anode of the SRD diode is connected to a voltage source corresponding to a low level of the output signal, and the cathode of the SRD diode is connected to the field effect transistor.
In an embodiment of the present invention, when the output signal is a rising edge pulse signal, the field effect transistor is an NMOS transistor.
In an embodiment of the present invention, when the output signal of the test channel needs to output a rising edge pulse signal, the analog ganged switch connected to the SRD diode is switched to an off state, or the moving end of the analog ganged switch is switched to a lower contact, which is suspended to disconnect the SRD diode from a dc bias voltage, the moving end of the analog ganged switch connected to the NMOS transistor is switched to the lower contact, and the dc bias voltage introduced from the lower contact turns on the NMOS transistor, so that the SRD diode is in a state where a positive bias is converted into a negative bias and a strong reverse current is formed, and then when the reverse current is momentarily turned off, a rising edge step pulse signal is obtained at the node and is immediately switched to a standby state.
In an embodiment of the present invention, when the output signal is a falling edge pulse signal, a negative electrode of the SRD diode is connected to a voltage source corresponding to a high level of the output signal, and a positive electrode of the SRD diode is connected to the field effect transistor.
In one embodiment of the present invention, when the output signal is a falling edge pulse signal, the field effect transistor is a PMOS transistor.
In an embodiment of the present invention, when the output signal of the test channel needs to output a falling edge pulse signal, the analog ganged switch connected to the SRD diode is switched to an off state, or the moving end of the analog ganged switch is switched to a lower contact which is suspended to disconnect the SRD diode from a dc bias voltage, the moving end of the analog ganged switch connected to the PMOS transistor is switched to the lower contact, and the dc bias voltage introduced from the lower contact turns on the PMOS transistor, so that the SRD diode is in a state where a positive bias is converted into a negative bias and a strong reverse current is formed, and then when the reverse current is momentarily turned off, a falling edge step pulse signal is obtained at the node and is immediately switched to a standby state.
In addition, the present invention further provides a signal adjusting module, which is used for adjusting the slew rate of the output signal of the test channel, and includes the signal adjusting unit described above, where the signal adjusting unit includes a signal adjusting unit a and a signal adjusting unit B, the signal adjusting unit a and the signal adjusting unit B are cascaded at the output end of the test channel, when the output signal is a rising edge pulse signal, the signal adjusting unit a adjusts the rising edge pulse signal through a control instruction, and when the output signal is a falling edge pulse signal, the signal adjusting unit B adjusts the falling edge pulse signal through a control instruction.
In an embodiment of the present invention, the number of the signal adjusting units a and the number of the signal adjusting units B are multiple, and multiple signal adjusting units a and multiple signal adjusting units B are sequentially cascaded at the output end of the test channel.
In an embodiment of the present invention, all signal adjusting units are coordinated to work in turn through a control instruction, when an output signal of the test channel needs to continuously output a plurality of alternating rising edge pulses and falling edge pulses, the plurality of signal adjusting units a sequentially adjust each rising edge pulse in turn through the control instruction, and the plurality of signal adjusting units B sequentially adjust each falling edge pulse in turn through the control instruction.
In an embodiment of the present invention, when the signal adjusting unit a is in a standby state, the analog interlock switch connected to the SRD diode is switched to a conducting state, or a moving end of the analog interlock switch is switched to an upper contact, so that a negative electrode of the SRD diode is connected to a dc bias voltage, the voltage is lower than a voltage connected to a positive electrode of the SRD diode, and a voltage difference is greater than or equal to a forward conduction voltage of the SRD diode, so that the SRD diode is in a forward bias state, the moving end of the analog interlock switch connected to the NMOS transistor is switched to the upper contact, and the dc bias voltage connected to the upper contact turns off the NMOS transistor, so that the signal adjusting unit a and the output pulse signal are not affected by each other.
In an embodiment of the present invention, when the signal adjusting unit B is in the standby state, the analog ganged switch connected to the SRD diode is switched to the on state, or the moving end of the analog ganged switch is switched to the upper contact, so that the anode of the SRD diode is connected to a dc bias voltage, the voltage is higher than the voltage connected to the cathode of the SRD diode, and the voltage difference is greater than or equal to the forward conduction voltage of the SRD diode, so that the SRD diode is in the forward bias state, the moving end of the analog ganged switch connected to the PMOS transistor is switched to the upper contact, and the dc bias voltage connected to the upper contact is used to turn off the PMOS transistor, so that the signal adjusting unit B and the output pulse signal are not affected by each other.
Moreover, the invention also provides a testing machine, which comprises the signal adjusting unit.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention utilizes the SRD diode and the field effect transistor to adjust the slew rate of the output signal of the test channel so as to output a step voltage when the rising edge pulse signal rises to the highest point or the falling edge pulse signal falls to the lowest point, so that the step voltage has higher slew rate, thereby providing signal excitation with higher slew rate and meeting different test requirements.
Drawings
Fig. 1 is a schematic diagram of an SRD diode.
Fig. 2 is a waveform diagram of input and output signals.
Fig. 3 is a schematic circuit diagram of a signal conditioning unit according to a first embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of a signal conditioning unit according to a second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a signal adjustment module according to a third embodiment of the present invention.
The reference numbers in the figures illustrate: 10. a control end; 21. a field effect transistor; 22. an SRD diode; 30. and (4) nodes.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
The main features of the SRD diode according to the present invention will be explained first.
The main feature of the SRD diode 22 is that the fall time of the SRD diode 22 when turned off is almost 0(ps order), i.e. the reverse current tail when turned off is eliminated, as shown in fig. 1, ts is the reverse storage time, tf is the fall time, trr = ts + tf represents the reverse recovery time of the SRD diode 22, and the SRD diode 22 has not only a very short fall time but also a very good forward conduction performance. Because of the good forward conductivity, it will store a large amount of minority carrier charges at the forward voltage, when the forward bias is switched to the negative bias, the stored minority carrier will flow in the opposite direction to the injection, thus forming a strong reverse current, and the off-state storage time is also long, when all the minority carriers are extracted, the reverse current suddenly drops to a very low level, the SRD diode 22 is switched off, forming a steep step voltage.
Example one
Referring to fig. 3, an embodiment of the present invention provides a signal adjusting unit for adjusting a slew rate of an output signal of a test channel, including:
a control terminal 10 including a plurality of analog interlock switches;
the signal adjusting circuit comprises a field effect transistor 21 and an SRD diode 22, wherein the field effect transistor 21 and the SRD diode 22 are connected in series, the field effect transistor 21 is connected with one of the analog linkage switches S1, the SRD diode 22 is connected with the other analog linkage switch S2, and the SRD diode 22 is used for adjusting an output signal of a test channel into a step pulse signal;
a node 30 connected to an output of the test channel;
when the output signal is a rising edge pulse signal, a control instruction is given to the analog linkage switch, so that the analog linkage switch is switched from an initial standby state to a working state, the field effect transistor 21 is turned on, the SRD diode 22 is switched from a positive bias to a negative bias and forms a strong reverse current state, and after all minority carriers of the SRD diode 22 are extracted, the reverse current of the SRD diode 22 is instantly turned off, so that a rising edge step pulse signal with a high slew rate is realized on the node 30.
The analog linkage switch is configured as a double-pole double-throw switch, or a single-pole double-throw switch and a single-pole single-throw switch are added and linked.
The grid of the field effect transistor 21 is connected with the moving end of one analog linkage switch S1, the series connection point of the SRD diode 22 and the field effect transistor 21 is connected with the moving end of the other analog linkage switch S2, wherein the upper contact of the analog linkage switch S1 is connected with a direct current bias voltage of 0V, the lower contact of the analog linkage switch S1 is connected with a direct current bias voltage of 10V, the upper contact of the analog linkage switch S2 is connected with a direct current bias voltage slightly lower than-VT, VT is the forward conduction voltage of the SRD diode, and the lower contact of the analog linkage switch S2 is suspended.
The signal adjusting circuit further comprises a current limiting resistor R, wherein the current limiting resistor R is arranged between the analog linkage switch S2 and the SRD diode, and the current limiting resistor R is used for adjusting the forward current of the SRD diode.
The principle is as follows: the anode of the SRD diode 22 is connected to a voltage source corresponding to the low level of the output signal, the cathode of the SRD diode 22 is connected to the field effect transistor 21, the field effect transistor 21 is an NMOS transistor, the input signal Vin is input to the amplifier a, and the input signal Vin is amplified by the amplifier a and then output as a pulse signal. Referring to fig. 2, when the rising edge pulse signal starts to rise (i.e. phase 2), the moving terminal of the analog ganged switch S2 connected to the SRD diode 22 is switched to the lower contact, which is floated to make the SRD diode 22 lose the forward bias voltage, the moving terminal of the analog ganged switch S1 connected to the NMOS transistor is switched to the lower contact, which is connected to the voltage V2=10V to make the NMOS transistor conduct, so that the Vo output is forced to the low level, the SRD diode 22 is in the state of being converted from the forward bias voltage to the negative bias voltage and forming a strong reverse current, the current outputted from the amplifier a flows to the SRD diode 22, and the reverse current of the SRD diode 22 is momentarily turned off after all the minority carriers of the SRD diode 22 are extracted, and the amplifier a continues to output the current, so as to realize the rising edge pulse signal with high slew rate at the node 30, after a rising edge step pulse signal of the high-voltage slew rate is realized on the node 30 (i.e., the stage 3), a control instruction is given to the analog ganged switch, so that the analog ganged switch is switched from the working state to the initial standby state, that is, the moving end of the analog ganged switch S1 connected with the field-effect tube 21 is switched to the upper contact, so that the field-effect tube 21 is cut off, and the moving end of the analog ganged switch S2 connected with the SRD diode 22 is switched to the upper contact, so that the SRD diode 22 is in a state of forward bias and storing minority carrier charges. In this way, the adjustment of the rising edge pulse signal to obtain the high voltage slew rate is the working principle.
The invention utilizes the SRD diode 22 and the NMOS tube to adjust the voltage conversion rate of the output signal of the amplifier in the test channel so as to output a step voltage when the rising edge pulse signal rises to the highest point, thereby leading the voltage to have higher slew rate.
Example two
Referring to fig. 4, an embodiment of the present invention provides a signal adjusting unit for adjusting a slew rate of an output signal of a test channel, including:
a control terminal 10 including a plurality of analog interlock switches;
the signal adjusting circuit comprises a field effect transistor 21 and an SRD diode 22, wherein the field effect transistor 21 and the SRD diode 22 are connected in series, the field effect transistor 21 is connected with one of the analog linkage switches S4, the SRD diode 22 is connected with the other analog linkage switch S3, and the SRD diode 22 is used for adjusting an output signal of a test channel into a step pulse signal;
a node 30 connected to an output of the test channel;
when the output signal is a falling edge pulse signal, a control instruction is given to the analog linkage switch, so that the analog linkage switch is switched from an initial standby state to a working state, the field effect transistor 21 is turned on, the SRD diode 22 is switched from a positive bias to a negative bias and forms a strong reverse current state, and after all minority carriers of the SRD diode 22 are extracted, the reverse current of the SRD diode 22 is instantly turned off, so that a falling edge step pulse signal with a high slew rate is realized on the node 30.
The analog linkage switch is configured as a double-pole double-throw switch, or a single-pole double-throw switch and a single-pole single-throw switch are added and linked.
The gate of the fet 21 is connected to the active terminal of one of the analog ganged switches S4, the series connection point of the SRD diode 22 and the fet 21 is connected to the active terminal of the other analog ganged switch S3, wherein the upper contact of the analog ganged switch S3 is connected to a dc bias voltage slightly higher than (VCC + VT), VCC =24V is a voltage corresponding to the high level of the output signal, VT is the forward conduction voltage of the SRD diode 22, the lower contact of the analog ganged switch S3 is floating, the upper contact of the analog ganged switch S4 is connected to a dc bias voltage V5=24V, and the lower contact of the analog ganged switch S4 is connected to a dc bias voltage V6= 14V.
The signal adjusting circuit further comprises a current limiting resistor R, wherein the current limiting resistor R is arranged between the analog linkage switch S3 and the SRD diode, and the current limiting resistor R is used for adjusting the forward current of the SRD diode.
The principle is as follows: the negative electrode of the SRD diode 22 is connected to a voltage source corresponding to the high level of the output signal, the positive electrode of the SRD diode 22 is connected to the field effect transistor 21, the field effect transistor 21 is a PMOS transistor, and the input signal Vin is input to the amplifier a and is amplified by the amplifier a and then output as a pulse signal. Referring to fig. 2, when the falling edge pulse signal starts to fall (i.e. phase 4), the moving terminal of the analog ganged switch S3 connected to the SRD diode 22 is switched to the lower contact, which is floated to make the SRD diode 22 lose the forward bias voltage, the moving terminal of the analog ganged switch S4 connected to the PMOS transistor is switched to the lower contact, which is connected with the voltage V6=14V to make the PMOS transistor turn on, so that the output of the V0 is forced to the high level, and the SRD diode 22 is in the state of being converted from the positive bias voltage to the negative bias voltage and forming a strong reverse current, and the reverse sink current outputted from the amplifier a is from the SRD diode 22, and after all the minority carriers of the SRD diode 22 are extracted, the reverse current of the SRD diode 22 is momentarily cut off, and the amplifier a continues to output the reverse sink current, so as to realize the falling edge pulse signal with high slew rate at the node 30, after a falling edge step pulse signal of the high-voltage slew rate is realized on the node 30 (i.e., the stage 5), a control instruction is given to the analog ganged switch, so that the analog ganged switch is switched from the working state to the initial standby state, that is, the moving end of the analog ganged switch S4 connected with the field-effect tube 21 is switched to the upper contact, so that the field-effect tube 21 is cut off, and the moving end of the analog ganged switch S3 connected with the SRD diode 22 is switched to the upper contact, so that the SRD diode 22 is in a state of forward bias and storing minority carrier charges. In this way, the adjustment of the falling edge pulse signal to obtain the high voltage slew rate is the working principle.
The present invention utilizes the SRD diode 22 and the PMOS transistor to adjust the voltage slew rate of the output signal of the amplifier in the test channel to output a step voltage when the falling edge pulse signal falls to the lowest point, so that the voltage slew rate is high.
EXAMPLE III
Referring to fig. 5, an embodiment of the present invention provides a signal adjusting module, configured to adjust a slew rate of an output signal of a test channel, including a signal adjusting unit a according to the first embodiment and a signal adjusting unit B according to the second embodiment, where the signal adjusting unit a and the signal adjusting unit B are cascaded at an output end of the test channel, and when an output signal of the signal adjusting unit a is a rising edge pulse signal, the signal adjusting unit a adjusts the rising edge pulse signal through a control instruction, and when the output signal of the signal adjusting unit B is a falling edge pulse signal, the signal adjusting unit B adjusts the falling edge pulse signal through the control instruction.
As a preferable scheme, the number of the signal adjusting units a and the number of the signal adjusting units B are both multiple, and the multiple signal adjusting units a and the multiple signal adjusting units B are sequentially cascaded at the output end of the test channel. When the output signal of the test channel needs to continuously output a plurality of alternate rising edge pulses and falling edge pulses, the plurality of signal adjusting units A sequentially adjust each rising edge pulse in turn through the control instruction, and the plurality of signal adjusting units B sequentially adjust each falling edge pulse in turn through the control instruction. For example, when the 1 st rising edge comes, the 1 st signal adjusting unit A is used for adjusting the rising edge pulse signal so as to obtain a high-voltage slew rate, and when the 1 st falling edge comes, the 1 st signal adjusting unit B is used for adjusting the falling edge pulse signal so as to obtain the high-voltage slew rate; when the 2 nd rising edge comes, the 2 nd signal adjusting unit A is used for adjusting the rising edge pulse signal so as to obtain the high-voltage slew rate, when the 2 nd falling edge comes, the 2 nd signal adjusting unit B is used for adjusting the falling edge pulse signal so as to obtain the high-voltage slew rate, and the like.
Further, when one of the signal adjusting units a is in an operating state, the other signal adjusting units a are in a standby state, so that the use frequency of each signal adjusting unit a is reduced, and the problem of heat generation caused by long-time use of a single signal adjusting unit a is effectively solved.
When the signal adjusting unit a is in the standby state, the moving end of the analog ganged switch S2 connected to the SRD diode 22 is switched to the upper contact, the upper contact is connected to a dc bias voltage lower than-VT to turn on the SRD diode 22, the moving end of the analog ganged switch S1 connected to the NMOS transistor is switched to the upper contact, and the upper contact is connected to a voltage of 0V to turn off the NMOS transistor, so that the signal adjusting unit a and the output pulse signal are not affected by each other.
It should be noted that the switching of the analog interlock switches S1 and S2 requires control command manipulation, and certainly at stage 3 in fig. 2, since the output pulse signal is always at a high level, at this time, the NMOS transistor is automatically turned off, that is, the signal adjusting unit a enters the standby state from the operating state.
Similarly, when one of the signal adjusting units B is in the working state, the other signal adjusting units B are in the standby state, so that the use frequency of each signal adjusting unit B is reduced, and the problem of heat generation caused by long-time use of a single signal adjusting unit B is effectively solved.
When the signal adjusting unit B is in the standby state, the moving end of the analog ganged switch S3 connected to the SRD diode 22 is switched to the upper contact, the upper contact is connected to the total voltage higher than the on-state voltage of the SRD diode 22 plus the high level of the output signal to turn on the SRD diode 22, the moving end of the analog ganged switch S4 connected to the PMOS transistor is switched to the upper contact, and the upper contact is connected to the power supply voltage VCC to turn off the PMOS transistor, so that the signal adjusting unit B and the output pulse signal are not affected by each other.
It should be noted that the switching of the analog interlock switches S3 and S4 requires control command manipulation, and certainly at stage 5 in fig. 2, since the output pulse signal is always at low level, at this time, the PMOS transistor is automatically turned off, that is, the signal adjusting unit B enters the standby state from the operating state.
Example four
An embodiment of the present invention further provides a testing machine, which includes the signal adjusting module, the specific content of which has been described above, and the details of which are not described herein again.
The above embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (16)
1. A signal conditioning unit for conditioning a slew rate of a test channel output signal, comprising:
a control terminal including a plurality of analog interlock switches;
the signal adjusting circuit comprises a field effect transistor and an SRD diode, the field effect transistor is connected with the SRD diode in series, the field effect transistor is connected with one of the analog linkage switches, the SRD diode is connected with the other analog linkage switch, and the output signal of the test channel is adjusted into a step pulse signal by using the SRD diode;
a node connected to an output of the test channel;
when the output signal is a rising edge pulse signal or a falling edge pulse signal, a control instruction is given to the analog gang switch, so that the analog gang switch is switched from an initial standby state to a working state, the field effect tube is conducted, the SRD diode is in a state of converting positive bias into negative bias and forming strong reverse current, and after all minority carriers of the SRD diode are extracted, the reverse current of the SRD diode is cut off instantly, and the rising edge step pulse signal or the falling edge step pulse signal with high voltage swing rate is realized on the node.
2. A signal conditioning unit as claimed in claim 1, characterized in that: and after the rising edge step pulse signal or the falling edge step pulse signal of the high-voltage slew rate is realized on the node, giving a control instruction to the analog linkage switch to enable the analog linkage switch to be switched from a working state to an initial standby state so as to cut off the field effect transistor, and thus enabling the SRD diode to be in a state of positive bias and storing minority carrier charges.
3. A signal conditioning unit as claimed in claim 2, characterized in that: the grid of the field effect transistor is connected with the movable end of one of the analog linkage switches, the series connection point of the SRD diode and the field effect transistor is connected with the movable end of the other analog linkage switch, and the fixed ends of the analog linkage switches are respectively connected with different direct current bias voltages or are suspended.
4. A signal conditioning unit as claimed in claim 3, characterized in that: the signal adjusting circuit further comprises a current limiting resistor, and the current limiting resistor is arranged between the analog linkage switch and the SRD diode.
5. A signal conditioning unit as claimed in claim 4, characterized in that: when the output signal is a rising edge pulse signal, the anode of the SRD diode is connected with a voltage source corresponding to the low level of the output signal, and the cathode of the SRD diode is connected with the field effect transistor.
6. A signal conditioning unit as claimed in claim 5, characterized in that: and when the output signal is a rising edge pulse signal, the field effect transistor is an NMOS transistor.
7. A signal conditioning unit according to claim 6, characterized in that: when the output signal of the test channel needs to output a rising edge pulse signal, the analog linkage switch connected with the SRD diode is switched to a disconnected state, or the movable end of the analog linkage switch is switched to a lower contact which is suspended to disconnect the SRD diode from a direct current bias voltage, the movable end of the analog linkage switch connected with the NMOS tube is switched to the lower contact, the direct current bias voltage led from the lower contact enables the NMOS tube to be conducted, so that the SRD diode is in a state that the positive bias is converted into the negative bias and a strong reverse current is formed, and then when the reverse current is cut off instantly, a rising edge step pulse signal is obtained at the node and is switched to a standby state immediately.
8. A signal conditioning unit as claimed in claim 4, characterized in that: when the output signal is a falling edge pulse signal, the cathode of the SRD diode is connected with a voltage source corresponding to the high level of the output signal, and the anode of the SRD diode is connected with the field effect transistor.
9. A signal conditioning unit as claimed in claim 8, characterized in that: and when the output signal is a falling edge pulse signal, the field effect transistor is a PMOS transistor.
10. A signal conditioning unit according to claim 9, characterized in that: when the output signal of the test channel needs to output a falling edge pulse signal, the analog linkage switch connected with the SRD diode is switched to a disconnected state, or the movable end of the analog linkage switch is switched to a lower contact which is suspended to disconnect the SRD diode from a direct current bias voltage, the movable end of the analog linkage switch connected with the PMOS tube is switched to the lower contact, the PMOS tube is conducted by the direct current bias voltage led from the lower contact, so that the SRD diode is in a state of converting a positive bias into a negative bias and forming a strong reverse current, and then when the reverse current is cut off instantly, a falling edge step pulse signal is obtained at the node and is switched to a standby state immediately.
11. A signal adjusting module, configured to adjust a slew rate of an output signal of a test channel, comprising the signal adjusting unit according to any one of claims 1 to 10, where the signal adjusting unit includes a signal adjusting unit a and a signal adjusting unit B, the signal adjusting unit a and the signal adjusting unit B are cascaded at an output end of the test channel, and when the output signal is a rising edge pulse signal, the signal adjusting unit a adjusts the rising edge pulse signal through a control instruction, and when the output signal is a falling edge pulse signal, the signal adjusting unit B adjusts the falling edge pulse signal through a control instruction.
12. A signal conditioning module according to claim 11, wherein: the number of the signal adjusting units A and the number of the signal adjusting units B are multiple, and the multiple signal adjusting units A and the multiple signal adjusting units B are sequentially cascaded at the output end of the test channel.
13. A signal conditioning module according to claim 12, wherein: all the signal adjusting units are coordinated to work in turn through a control instruction, when the output signal of the test channel needs to continuously output a plurality of alternate rising edge pulses and falling edge pulses, the signal adjusting units A sequentially adjust each rising edge pulse in turn through the control instruction, and the signal adjusting units B sequentially adjust each falling edge pulse in turn through the control instruction.
14. A signal conditioning module according to claim 11, wherein: when the signal adjusting unit A is in a standby state, the analog linkage switch connected with the SRD diode is switched to a conducting state, or the moving end of the analog linkage switch is switched to an upper contact, so that the negative electrode of the SRD diode is connected with a direct current bias voltage, the voltage is lower than the voltage connected with the positive electrode of the SRD diode, the moving end of the analog linkage switch connected with the NMOS tube is switched to the upper contact, and the direct current bias voltage connected with the upper contact cuts off the NMOS tube, so that the signal adjusting unit A and the output pulse signal are not influenced by each other.
15. A signal conditioning module according to claim 11, wherein: when the signal adjusting unit B is in a standby state, the analog linkage switch connected with the SRD diode is switched to a conducting state, or the moving end of the analog linkage switch is switched to an upper contact, so that the anode of the SRD diode is connected with a direct current bias voltage, the voltage is higher than the voltage connected with the cathode of the SRD diode, the moving end of the analog linkage switch connected with the PMOS tube is switched to the upper contact, and the direct current bias voltage connected with the upper contact is used for stopping the PMOS tube, so that the signal adjusting unit B and the output pulse signal are not influenced by each other.
16. A testing machine, characterized by: comprising a signal conditioning unit as claimed in any one of claims 1 to 10.
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