CN113473748A - Manufacturing method of multilayer connecting plate - Google Patents
Manufacturing method of multilayer connecting plate Download PDFInfo
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- CN113473748A CN113473748A CN202010236927.0A CN202010236927A CN113473748A CN 113473748 A CN113473748 A CN 113473748A CN 202010236927 A CN202010236927 A CN 202010236927A CN 113473748 A CN113473748 A CN 113473748A
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- substrate
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- conductive
- hole
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 13
- 239000003292 glue Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims abstract description 7
- 238000000608 laser ablation Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000008569 process Effects 0.000 claims description 20
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 18
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 10
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 claims description 8
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 239000003365 glass fiber Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000012286 potassium permanganate Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 2
- 238000005429 filling process Methods 0.000 abstract description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a method for manufacturing a multilayer connecting plate, and relates to the field of connecting plate manufacturing. The method comprises the following steps: providing a first substrate, wherein the first substrate comprises a first dielectric layer and a first conductive layer; forming at least one first hole in the first dielectric layer by laser ablation; removing the glue residues on the first substrate; microetching the first substrate; after each first hole is plated by a deposition method, first conductive holes with the copper plating thickness of more than 0.0065mm are formed; patterning all the first conductive layers to form a first circuit layer; the upper end and the lower end of each first conductive hole are respectively and electrically connected with the adjacent first circuit layer; and according to the required layer number, performing layer addition on the outer side of the first circuit layer to form other substrates so as to form the multilayer high-density connecting plate. The invention can ensure that the filling holes of each layer of connecting plate are filled, optimize the alignment system of each workshop section according to the alignment requirement and improve the alignment requirement of the finished product; by improving the capability and the alignment degree of the hole filling process, the interconnection requirement of any layer is met.
Description
Technical Field
The invention relates to the field of manufacturing of connecting plates, in particular to a method for manufacturing a multilayer connecting plate.
Background
With the rapid development of technologies such as artificial intelligence image recognition in recent years, the size of printed circuit boards has been further reduced in response to the development of high-density multifunction miniaturization. Among them, the packaging method of the mother-daughter board by using the board edge metallized half-hole is very common.
Due to the product function and the requirement of pasting devices, the daughter board has the characteristics of arbitrary interconnection fine lines and the like, and the production difficulty and the cost of the printed circuit board are undoubtedly increased. However, the alignment of the blind holes between layers of the printed circuit board is low, which is not favorable for the development of high-density multi-functional miniaturization.
Therefore, how to improve the alignment of the blind holes between layers of the printed circuit board is a difficult problem to be overcome in the industry.
Disclosure of Invention
Aiming at the defects in the prior art, the invention solves the technical problems that: how to improve the alignment of blind holes between layers of a printed circuit board.
In order to achieve the above object, the present invention provides a method for manufacturing a multilayer high-density connection plate, comprising the steps of:
s101: providing a first substrate, wherein the first substrate comprises a first dielectric layer and two first conductive layers which are respectively positioned at two opposite sides of the first dielectric layer;
s102: forming at least one first hole in the first dielectric layer by laser ablation, wherein the first hole is a blind hole relative to the first substrate;
s103: removing glue residue generated by laser drilling on the first substrate;
s104: microetching the first substrate from which the glue residue is removed;
s105: after each first hole is plated by a deposition method, first conductive holes with the copper plating thickness of more than 0.0065mm are formed;
s106: patterning all the first conductive layers to form a first circuit layer; the upper end and the lower end of each first conductive hole are respectively and electrically connected with the adjacent first circuit layer;
s107: adding layers on the outer side of the first circuit layer according to the required number of layers to form other substrates, wherein one circuit layer is shared between adjacent substrates; and forming the conductive holes of other substrates of each layer according to the operation processes from S102 to S106 and electrically connecting the conductive holes with the adjacent circuit layers, thereby forming the multilayer high-density connecting plate.
On the basis of the above technical solution, in S101, the material of the first dielectric layer includes resin and glass fiber.
On the basis of the technical scheme, the mode for removing the glue residues in the step S103 comprises the following steps: sulfuric acid process, plasma process, chromic acid process or potassium permanganate process.
On the basis of the above technical solution, the specific process of S104 includes: immersing the first substrate in a microetching tank to carry out microetching by using microetching liquid; the microetching solution comprises the following components: at least one of ammonia water, hydrogen peroxide, sulfuric acid and chromic acid.
On the basis of the above technical solution, the specific process of S105 includes: and carrying out chemical copper deposition and electroplating copper on each first hole to form a first conductive hole in each first hole.
On the basis of the technical scheme, the thickness of the copper plating of the first conductive hole in S105 is 0.0065-0.01 mm.
On the basis of the above technical solution, the other substrates in S107 are:
the second substrate is positioned on the first substrate and comprises a second dielectric layer covering the first dielectric layer and the first circuit layer, a second circuit layer positioned on the upper surface of the second dielectric layer and a second conductive hole formed in the second dielectric layer; two ends of at least one second conductive hole are respectively and electrically connected with the second circuit layer and the first circuit layer of the adjacent second substrate;
a third substrate located below the first substrate, including a third dielectric layer covering the first dielectric layer and the first circuit layer, a third circuit layer located on the upper surface of the third dielectric layer, and a third conductive hole formed in the third dielectric layer; two ends of at least one third conductive hole are respectively and electrically connected with the third circuit layer and the first circuit layer of the adjacent third substrate.
On the basis of the above technical solution, the method further includes the following steps after S107: s108: when the substrate has more than two layers, the substrates of each layer are physically fixed.
Compared with the prior art, the invention has the advantages that:
the invention can ensure that the filling holes of each layer of connecting plate are filled, optimize the alignment system of each workshop section according to the alignment requirement and improve the alignment requirement of the finished product; by improving the capability and the alignment degree of the hole filling process, the interconnection requirement of any layer is met.
Drawings
FIG. 1 is a flow chart of a method of manufacturing a multi-layer high-density connector board in an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a substrate according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a substrate with a first hole formed therein according to an embodiment of the invention;
fig. 4 to 6 are schematic cross-sectional views of multilayer connection boards with different layers according to an embodiment of the present invention.
In the figure: 110-a first substrate, 111-a first dielectric layer, 112-a first conductive layer, 1121-a first circuit layer, 113-a first hole, 1131-a first conductive hole, 120-a second substrate, 121-a second dielectric layer, 122-a second circuit layer, 123-a second conductive hole, 130-a third substrate, 131-a third dielectric layer, 132-a third circuit layer, 133-a third conductive hole.
Detailed Description
In order to make the invention more complete and complete, the following description is given by way of illustrative example, but this is not intended to be the only form in which the invention may be practiced or carried out. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description. In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, the invention may be practiced without these specific details.
Spatially relative terms, such as "lower," "upper," and the like, may be used for convenience in describing an element or feature as being related to other elements or features in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although the present invention is illustrated and described herein as a series of acts or steps, the order in which the acts or steps are presented should not be construed as a limitation. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Moreover, not all illustrated operations, steps and/or features may be required to implement an embodiment of the present invention. Further, each operation or step described herein may comprise several sub-steps or actions.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, a method for manufacturing a multilayer high-density connection board according to an embodiment of the present invention includes the steps of:
s101: a first substrate 110 is provided, as shown in fig. 2, the first substrate 110 includes a first dielectric layer 111, and two first conductive layers 112 respectively located on two opposite sides of the first dielectric layer 111 (for example, the two first conductive layers 112 are respectively located on the upper surface and the lower surface of the first dielectric layer 111). In some embodiments, the material of the first dielectric layer 111 may include resin and glass fiber. For example, the resin may be a phenolic resin, an epoxy resin, a polyimide resin, or polytetrafluoroethylene.
S102: referring to fig. 3, at least one first hole 113 is formed in the first dielectric layer 111 by Laser ablation (Laser ablation), the first hole 113 is a blind hole with respect to the first substrate 110, and due to the high Temperature caused by Laser drilling, the resin exceeds Tg (Transition Temperature value) to form a molten state, so that scum is generated near the first hole 113.
S103: removing the glue residue remaining on the first substrate 110, wherein the manner of removing the glue residue comprises: sulfuric Acid process (sulfuric Acid), Plasma process (Plasma), chromic Acid process (chromic Acid) or potassium Permanganate process (Permanganate).
S104: the first substrate 110 from which the scum has been removed is micro-etched. Specifically, after the glue residue is removed, the first substrate 110 is further immersed in a microetching tank to be microetched by using a microetching solution; the microetching solution comprises the following components: at least one of ammonia water, hydrogen peroxide, sulfuric acid and chromic acid. Ammonia water and hydrogen peroxide are adopted in the embodiment; in some embodiments, the microetching solution is sulfuric acid, and in some embodiments, the microetching solution is ammonia, hydrogen peroxide, sulfuric acid, and chromic acid.
S105: after each first hole 113 is plated, a first conductive hole 1131 is formed; the method comprises the following specific steps: first, a chemical copper deposition and then an electroplating copper deposition are performed on each first via 113, so that a first conductive via 1131 is formed in the first via 113. In some embodiments, the first conductive via 1131 has a copper plating thickness of 0.0065mm or greater; in some embodiments, the copper plating thickness is 0.0065-0.01 mm, such as 0.0007mm, 0.0075mm, 0.008mm, 0.0085mm, 0.009mm, 0.0095mm, or any value between any two of these equivalents.
S106: referring to fig. 3, all the first conductive layers 112 are patterned to form first circuit layers 1121; the upper and lower ends of each first conductive via 1131 are electrically connected to the adjacent first circuit layer 1121 respectively.
S107: and (3) adding layers on the outer side of the first circuit layer 1121 according to the required number of layers to form other substrates (one circuit layer is shared between adjacent substrates), forming conductive holes of each layer of other substrates according to the operation processes from S102 to S106, and electrically connecting the conductive holes with the adjacent circuit layers, thereby forming the multilayer high-density connecting plate.
Referring to fig. 4, other substrates in this embodiment are:
the second substrate 120 is disposed on the first substrate 110 and includes a second dielectric layer 121 covering the first dielectric layer 111 and the first circuit layer 1121, a second circuit layer 122 disposed on an upper surface of the second dielectric layer 121, and a second conductive via 123 formed in the second dielectric layer 121. Two ends of the at least one second conductive via 123 are electrically connected to the second circuit layer 122 and the first circuit layer 1121 of the adjacent second substrate 120, respectively.
The third substrate 130, which is located under the first substrate 110, includes a third dielectric layer 131 covering the first dielectric layer 111 and the first circuit layer 1121, a third circuit layer 132 located on the upper surface of the third dielectric layer 131, and a third conductive hole 133 formed in the third dielectric layer 131. Two ends of the at least one third conductive via 133 are electrically connected to the third circuit layer 132 and the first circuit layer 1121 of the adjacent third substrate 130, respectively.
Referring to fig. 5 and 6, one to two second substrates 120 are added on the second substrate 120 and one to two third substrates 130 are added on the third substrate 130 to form 5-layer or 7-layer substrates according to the required number of layers. Each layer of the substrate is formed as in steps S102 to S106.
In addition, in some embodiments, referring to fig. 1, S108 may be further added after S107, specifically: when the substrate has more than two layers, each layer of substrate is physically fixed. In some embodiments, the physical attachment is performed by riveting the layers, for example, four corners of 7 layers of substrates are riveted first to prevent the displacement of the layers during the bonding process.
In some embodiments, one of the first conductive vias 1131, one of the second conductive vias 123 and one of the third conductive vias 133 are disposed opposite to each other to form a via. In some embodiments, any layer of high density connector plates has greater than 250 through holes per square centimeter per face. In one embodiment, the diameter of the conductive hole (laser blind hole) of each layer is less than or equal to 0.15mm, and any layers are interconnected. In order to meet the reliability requirement specified by IPC (International Process control) specifications, a microetching step is added after the step of removing the glue residues on each layer plate; aiming at the requirement of the alignment degree of each layer, each layer is physically fixed, so that the alignment degree error between two adjacent layers of conductive holes is less than or equal to 3 mils.
The filling hole parameters are used for manufacturing, filling of each layer of filling holes is guaranteed, alignment systems of all the working sections are optimized according to the alignment requirements, and the alignment requirements of finished products are improved. By improving the capability and the alignment degree of the hole filling process, the interconnection requirement of any layer is met.
Further, the present invention is not limited to the above-mentioned embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.
Claims (8)
1. A method of manufacturing a multilayer high density connector board, comprising the steps of:
s101: providing a first substrate (110), wherein the first substrate (110) comprises a first dielectric layer (111) and two first conductive layers (112) respectively positioned at two opposite sides of the first dielectric layer (111);
s102: forming at least one first hole (113) in the first dielectric layer (111) by laser ablation, the first hole (113) being blind with respect to the first substrate (110);
s103: removing the glue residue generated by laser drilling on the first substrate (110);
s104: microetching the first substrate (110) from which the smear has been removed;
s105: after each first hole (113) is plated by deposition, a first conductive hole (1131) with the copper plating thickness of more than 0.0065mm is formed;
s106: patterning all the first conductive layers (112) to form first circuit layers (1121); the upper end and the lower end of each first conductive hole (1131) are respectively and electrically connected with the adjacent first circuit layer (1121);
s107: adding layers on the outer side of the first circuit layer (1121) according to the required number of layers to form other substrates, wherein one circuit layer is shared between adjacent substrates; and forming the conductive holes of other substrates of each layer according to the operation processes from S102 to S106 and electrically connecting the conductive holes with the adjacent circuit layers, thereby forming the multilayer high-density connecting plate.
2. The method of manufacturing a multilayer high-density connector board according to claim 1, characterized in that: in S101, the material of the first dielectric layer (111) includes resin and glass fiber.
3. The method for manufacturing a multilayer high-density connector board according to claim 1, wherein the removing of the smear in S103 includes: sulfuric acid process, plasma process, chromic acid process or potassium permanganate process.
4. The method for manufacturing a multilayer high-density connector board according to claim 1, wherein the specific process of S104 includes: immersing the first substrate (110) in a microetching tank to carry out microetching by using microetching liquid; the microetching solution comprises the following components: at least one of ammonia water, hydrogen peroxide, sulfuric acid and chromic acid.
5. The method for manufacturing a multilayer high-density connector board according to claim 1, wherein the specific process of S105 includes: and performing chemical copper deposition and electroplating copper on each first hole (113) to form a first conductive hole (1131) in the first hole (113).
6. The method of manufacturing a multilayer high-density connector board according to claim 1, characterized in that: in S105, the thickness of the copper plating of the first conductive hole (1131) is 0.0065-0.01 mm.
7. The method for producing a multilayer high-density connecting plate according to any one of claims 1 to 6, wherein the other substrates in S107 are:
a second substrate (120) disposed on the first substrate (110), and including a second dielectric layer (121) covering the first dielectric layer (111) and the first circuit layer (1121), a second circuit layer (122) disposed on the upper surface of the second dielectric layer (121), and a second conductive via (123) formed in the second dielectric layer (121); two ends of the at least one second conductive via (123) are electrically connected to the second circuit layer (122) and the first circuit layer (1121) of the adjacent second substrate (120), respectively;
a third substrate (130) disposed under the first substrate (110), and including a third dielectric layer (131) covering the first dielectric layer (111) and the first circuit layer (1121), a third circuit layer (132) disposed on the upper surface of the third dielectric layer (131), and a third conductive via (133) formed in the third dielectric layer (131); two ends of the at least one third conductive via (133) are electrically connected to the third circuit layer (132) and the first circuit layer (1121) of the adjacent third substrate (130), respectively.
8. The method for manufacturing a multilayer high-density connector board according to any one of claims 1 to 6, further comprising the following step after S107: s108: when the substrate has more than two layers, the substrates of each layer are physically fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010236927.0A CN113473748A (en) | 2020-03-30 | 2020-03-30 | Manufacturing method of multilayer connecting plate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010236927.0A CN113473748A (en) | 2020-03-30 | 2020-03-30 | Manufacturing method of multilayer connecting plate |
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| CN113473748A true CN113473748A (en) | 2021-10-01 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080308304A1 (en) * | 2005-04-28 | 2008-12-18 | Tadashi Nakamura | Multilayer Wiring Board and Its Manufacturing Method |
| CN103687339A (en) * | 2012-09-26 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
| CN104105337A (en) * | 2013-04-11 | 2014-10-15 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with high-density circuits and method for manufacturing the circuit board |
| TW201743671A (en) * | 2016-06-13 | 2017-12-16 | 健鼎科技股份有限公司 | Manufacturing method of high-density multilayer board |
| US20190380210A1 (en) * | 2018-06-08 | 2019-12-12 | Unimicron Technology Corp. | Circuit carrier board structure and manufacturing method thereof |
-
2020
- 2020-03-30 CN CN202010236927.0A patent/CN113473748A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080308304A1 (en) * | 2005-04-28 | 2008-12-18 | Tadashi Nakamura | Multilayer Wiring Board and Its Manufacturing Method |
| CN103687339A (en) * | 2012-09-26 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
| CN104105337A (en) * | 2013-04-11 | 2014-10-15 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with high-density circuits and method for manufacturing the circuit board |
| TW201743671A (en) * | 2016-06-13 | 2017-12-16 | 健鼎科技股份有限公司 | Manufacturing method of high-density multilayer board |
| US20190380210A1 (en) * | 2018-06-08 | 2019-12-12 | Unimicron Technology Corp. | Circuit carrier board structure and manufacturing method thereof |
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Application publication date: 20211001 |