CN113472708A

CN113472708A - Eye monitor for parallel digital equalizer

Info

Publication number: CN113472708A
Application number: CN202110097769.XA
Authority: CN
Inventors: 孙俊清; 钱浩立
Original assignee: Credo Technology Group Ltd
Current assignee: Credo Technology Group Ltd
Priority date: 2020-03-31
Filing date: 2021-01-25
Publication date: 2021-10-01
Anticipated expiration: 2041-01-25
Also published as: CN113472708B; US10992501B1

Abstract

The invention relates to an eye monitor for a parallel digital equalizer. An illustrative integrated receiver circuit embodiment comprises: a set of analog-to-digital converters that sample a received signal in response to an interleaved clock signal to provide a set of parallel sampled received signals; an equalizer that converts the set of parallel sampled received signals into a set of parallel equalized signals; one or more quantizers that derive symbol decisions from the set of parallel equalized signals; a digital timing circuit that generates an interleaved clock signal based on the set of parallel equalized signals; and a clock skew adjustment circuit that provides controllable skew of at least one of the staggered clock signals relative to at least one other of the staggered clock signals. Comprises a monitoring circuit for providing a reliability indicator of the symbol decision; and a controller that determines a dependency of the reliability indicator on the controllable skew.

Description

Eye monitor for parallel digital equalizer

Background

Digital communication occurs between a sending device and a receiving device over an intermediate communication medium (e.g., fiber optic cable or insulated copper wire) having one or more designated communication channels (e.g., carrier wavelengths or frequency bands). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects a possibly corrupted sequence of symbols and attempts to reconstruct the transmitted data.

A "symbol" is a state or effective condition of a channel that lasts for a fixed period of time, referred to as a "symbol interval". The symbol may be, for example, a voltage or current level, an optical power level, a phase value, or a particular frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol may represent (i.e., encode) one or more binary bits of data. Alternatively, the data may be represented by symbol transitions or by a sequence of two or more symbols. The simplest digital communication links use only one bit per symbol; a binary "0" is represented by one symbol (e.g., a voltage or current signal in a first range) and a binary "1" is represented by another symbol (e.g., a voltage or current signal in a second range).

Channel non-idealities can cause each symbol to disturb the dispersion of its neighboring symbols, causing inter-symbol interference (ISI). As the symbol rate increases, ISI may make it difficult for a receiving device to determine which symbols to transmit at each interval (especially when such ISI is combined with additive noise). The published literature discloses a number of equalization and demodulation techniques to recover digital data from a degraded received signal even in the presence of ISI.

One technique for estimating the channel and equalization techniques is an "eye diagram," i.e., a representation of all possible paths that a signal may follow within a given symbol interval, typically obtained via superposition of many symbol intervals. Typically, the optimal sampling instant is near the midpoint of the symbol interval, where it is desired to find the opening between signal paths representing different symbol values. If such an opening is present, the transmitted symbol may be detected by a comparator that compares the sampled value to a decision threshold at the center of the opening. The reliability of such decisions depends on the amount of noise associated with deciding the distance between the threshold and the edge of the opening.

Typically, the eye pattern of the received signal has little or no opening, in which case an equalizer may be employed to create or increase the opening size relative to the average noise level. In order to evaluate receiver performance in such cases, it is often desirable to monitor the eye diagram of the equalized signal (i.e., the signal present at the input of the symbol decision element). Such monitoring can be challenging for digital communication receivers operating in the tens of gigahertz range, in which case the integrated circuit implementation approaches the physical limits of silicon-based device design.

Disclosure of Invention

Accordingly, an eye monitor is disclosed herein that utilizes the structure of a parallel digital equalizer to achieve monitoring without significantly increasing hardware requirements or complexity. An illustrative integrated receiver circuit embodiment comprises: a set of analog-to-digital converters that sample the received signals in response to the staggered clock signals to provide a set of parallel sampled received signals; an equalizer that converts the set of parallel sampled received signals into a set of parallel equalized signals; one or more quantizers that derive symbol decisions from the set of parallel equalized signals; a digital timing circuit that generates an interleaved clock signal based on the set of parallel equalized signals; and a clock skew adjustment circuit that provides controllable skew of at least one of the staggered clock signals relative to at least one other of the staggered clock signals. Comprises a monitoring circuit for providing a reliability indicator of the symbol decision; and a controller that determines a dependency of the reliability indicator on the controllable skew.

An illustrative method of fabricating an integrated receiver circuit includes patterning an integrated circuit substrate to provide the foregoing components.

An illustrative eye monitoring method comprises: (a) operating a set of digital-to-analog converters in response to an interleaved clock signal to provide a set of parallel sampled received signals; (b) filtering the set of parallel sampled received signals to obtain a set of parallel equalized signals; (c) quantizing the set of parallel equalized signals to derive symbol decisions; (d) generating an interleaved clock signal based on the set of parallel equalized signals; (e) controlling skew of at least one of the staggered clock signals relative to at least one other of the staggered clock signals; (f) monitoring a reliability indicator of the symbol decision; and (g) determining a dependency of the reliability indicator on the skew.

Each of the foregoing embodiments may be implemented separately or in combination, and may be implemented with any one or more of the following features in any suitable combination: 1. the reliability indicator is a signal margin measurement. 2. The reliability indicator is the bit error rate. 3. The clock skew adjustment circuit provides controllable skew of each of the staggered clock signals relative to at least one other of the staggered clock signals. 4. The controller sets a controllable skew of each of the staggered clock signals to optimize the reliability indicator. 5. The controller systematically sets a controllable skew to map the reliability indicator across the entire width of the decision eye. 6. As part of generating the staggered clock signal, the digital timing circuit aligns transitions in the staggered clock signal with optimal sampling instants in the received signal by iteratively correcting estimated timing errors estimated by combining sets of parallel equalized signals with symbol decisions. 7. As part of the iterative correction, the digital timing circuit excludes those estimated timing errors that are dominated by controllable skew. 8. The clock skew adjustment circuit controls a programmable delay line for at least one of the staggered clock signals. 9. The clock skew adjustment circuit controls at least one phase offset of the phase interpolator that controls a phase of at least one of the staggered clock signals.

Drawings

Fig. 1 is a perspective view of an illustrative active ethernet cable ("AEC").

FIG. 2 is a block diagram of an illustrative AEC.

Fig. 3 is a block diagram of an illustrative digital communication receiver.

Fig. 4 is a block diagram of an illustrative decision feedback equalizer ("DFE").

Fig. 5 is a diagram of an illustrative staggered clock signal.

Fig. 6 is a block diagram of an illustrative parallel DFE.

Fig. 7 is an illustrative eye diagram.

Fig. 8 is a diagram of an illustrative clock signal with skew adjustment.

Fig. 9 is a block diagram of an illustrative clock skew adjustment circuit.

Fig. 10 is a flow chart of an illustrative eye monitoring method.

Detailed Description

While specific embodiments are set forth in the drawings and the following description, it should be borne in mind that they do not limit the disclosure. On the contrary, they provide the basis for the ordinary skilled person to discern the alternatives, equivalents and modifications that are included within the scope of the appended claims.

Fig. 1 is a perspective view of an illustrative active ethernet cable ("AEC") that may be used to provide high bandwidth communication links between devices in a routing network, such as that used for data centers, server farms, and interconnect switching. The routing network may be part of or may include, for example, the internet, a wide area network, a local area network, or a storage area network. The linked devices may be computers, switches, routers, and the like. The cable comprises a first connector 100 and a second connector 101 connected via electrical conductors 106 in an electrical cord. The electrical conductors 106 may be arranged in pairs (such as with a twinaxial conductor). (twinaxial conductors may be likened to coaxial conductors, but have two inner conductors instead of one) the inner conductors may be driven with differential signals, and their shared shield may operate to reduce crosstalk with other twinaxial conductors in the cable. Other paired conductor or single ended conductor implementations may be employed depending on performance criteria.

According to the ethernet standard, each conductor pair may provide unidirectional transmission of differential signals. To achieve robust performance even over extended cable lengths (e.g., greater than 3, 6, or 9 meters), each connector 102, 104 may include a powered transceiver that performs clock and data recovery ("CDR") and re-modulation of the data stream in each direction. Such powered transceivers are also known as data recovery and remodulation ("DRR") devices. It is noted that the transceiver will not only CDR and remodulate the outgoing data stream as it leaves the cable, but will also CDR and remodulate the incoming data stream as it enters the cable.

The

connectors

100, 101 may be pluggable modules that are compatible with any of the pluggable module standards (e.g., SFP-DD, QSFP-DD, OSFP). In at least one contemplated embodiment, the

cable connectors

100, 101 are quad small form factor pluggable ("QSFP") transceiver modules, and more particularly QSFP28 transceiver modules that exchange CAUI-4 data streams with a host. In other contemplated embodiments, the cable connector is a dual small form factor pluggable ("DSFP") or small form factor pluggable dual density ("SFP-DD") transceiver module that exchanges 100GBASE-KR2 data streams with the host. In yet other contemplated embodiments, the cable connectors are different, such as QSFP28 to SFP-DD cables, QSFP28 to DSFP cables, or SFP-DD to DSFP cables.

FIG. 2 is a block diagram of an illustrative AEC. The connector 100 includes a plug 200, the plug 200 adapted to fit a standard compatible ethernet port in a first host device to receive input electrical signals carrying data streams from the host device and to provide output electrical signals carrying data streams to the host device. Similarly, the connector 101 comprises a plug 201 that fits into the ethernet port of the second host device. The connector 100 includes a first DRR device 202, the first DRR device 101 for performing CDR and remodulation of data streams entering and leaving the cable at the connector 100, and the connector 204 includes a second DRR device 101, the second DRR device 304 for performing CDR and remodulation of data streams entering and leaving the cable at the connector 301. The

DRR devices

202, 204 can be integrated circuits mounted on a printed circuit board and connected to edge connector contacts via circuit board traces. The electrical conductors 106 and the shield can be soldered to corresponding pads on the printed circuit board that are electrically connected to the DRR device.

In at least some contemplated embodiments, the printed circuit boards also each support a microcontroller unit ("MCU") 206. Each

DRR device

202, 204 is coupled via a first two-wire bus to a respective MCU device 206 that configures the operation of the DRR device. At power up, the MCU device 206 loads equalization parameters and/or other operating parameters from the flash memory 207 into the configuration registers 208 of the DRR device. The host device may access the MCU device 206 via a second two-wire bus that operates according to the I2C bus protocol and/or the faster MDIO protocol. With such access to the MCU device 206, the host device can adjust operating parameters of the cable and monitor the performance of the cable.

Each

DRR device

202, 204 includes a set of Transmitters (TX) and Receivers (RX) 220 for communicating with a host device and a set of transmitters and receivers 222 for transmitting and receiving via pairs of conductors along the length of the cable. The cable-facing transceivers 222 preferably transmit and receive using differential NRZ at 26.5625GBd in each direction on each channel, or differential PAM4 at 26.5625GBd in each direction on half of the channel. To provide the desired range, it may be necessary to use a larger cross section of copper wire for differential PAM4 signaling.

The illustrated host-facing transceiver 220 supports eight lanes LN0-LN7 for bidirectional communication with host devices, each bidirectional lane being formed by two unidirectional connections utilizing differential PAM4 signaling under 26.5625GBd, such as may be implemented with 400GBASE-KR 8. In other contemplated embodiments, the host-facing transceiver 220 supports four lanes using differential NRZ signaling according to the CAUI-4 specification. The DRR device includes a memory 224 for providing a first-in-first-out (FIFO) buffer between the transmitter and receiver sets 220, 222. The embedded controller 228 coordinates the operation of the transmitter and receiver by, for example, setting initial equalization parameters and ensuring that a training phase is completed across all channels and links before the transmitter and receiver are enabled to enter a data transmission phase. Embedded controller 228 employs register set 208 to receive commands and parameter values and provide responses that potentially include state information and performance data.

In at least some contemplated embodiments, the host-facing set of transmitters and receivers 220 employ fixed equalization parameters that are cable-independent (i.e., they are not customized on a cable-by-cable basis). The center-facing transmitter and receiver set 222 preferably employs cable-dependent equalization parameters that are customized on a cable-by-cable basis. The equalization parameters that depend on the cable may be adaptive or fixed, and the initial values of these parameters may be determined during manufacturer testing of the cable. The equalization parameters may include filter coefficient values of a pre-equalizer filter in the transmitter, and gain and filter coefficient values of the receiver.

Before describing a parallel digital equalizer design that may be preferred for each of the high-rate digital communication receivers of the

DRR devices

202, 204, it may be helpful to describe a non-parallel receiver design such as that shown in fig. 3 and 4.

As shown in fig. 3, the illustrative digital receiver includes an analog-to-digital converter ("ADC") 304 that samples an analog receive signal 302 at sample times corresponding to transitions in a sampling clock signal 305 to provide a digital receive signal to a demodulator 306. Demodulator 306 applies equalization and symbol detection using, for example, a matched filter, a decision feedback equalizer, or any other suitable demodulation technique. The resulting demodulated symbol stream 308 can be processed in accordance with a correlation protocol to extract correlation information from the data stream, including, for example, alignment, deinterleaving, error correction, and descrambling operations.

The illustrative receiver includes digital timing circuitry for generating a suitable sampling clock signal 305. In fig. 3, the digital timing circuit includes a timing error estimator 310, which timing error estimator 310 combines the symbol decisions with the sampled signal (or more preferably, with the equalized signal) to generate a timing error estimate. Is suitably aThe Timing error estimation formula can be found, for example, in Mueller-Muller, "Timing Recovery in Digital synchronization Data Receivers," IEEE communications journal, 5.1976, volume 24, No. 5. The timing loop filter 312 filters the estimated timing error signal to obtain a timing control signal for the phase interpolator 320. In the embodiment of fig. 3, timing loop filter 312 is a second order proportional-integral (PI) filter having a summer 314 that receives a proportion of the timing error signal along the first path (i.e., by a constant coefficient k)_PScaling) the component, and receiving the integral of the timing error signal along the second path (i.e., by a constant coefficient k)₁Scaled and integrated by integrator 316). The received components are summed and provided to a second integrator 318, and the second integrator 318 integrates the sum to provide a timing control signal to a phase interpolator 320.

Phase interpolator 320 also receives a clock signal from a Phase Locked Loop (PLL) 322. The timing control signal causes phase interpolator 320 to generate the sampling signal by adjusting the phase of the clock signal in a manner that minimizes the expected value of the timing error. In other words, the timing control signal compensates for both the frequency offset and the phase error of the clock signal relative to the analog data signal 302, thereby phase aligning the sampling clock 305 with the data symbols in the analog received signal.

The clock signal generated by PLL 322 is a multiplied version of the reference clock signal from reference oscillator 324. A voltage controlled oscillator ("VCO") 326 supplies a clock signal to both the phase interpolator 320 and a counter 328, the counter 328 dividing the frequency of the clock signal by a constant or variable modulus N. The counter supplies a divided clock signal to a phase frequency detector ("PFD") 330. The PFD 330 may use a charge pump ("CP") as part of determining which input (i.e., the divided clock signal or the reference clock signal) has earlier or more frequent transitions than the other. The low pass filter 332 filters the output of the PFD 330 to provide a control voltage to the VCO 326. The filter coefficients are selected so that the divided clock is phase aligned with the reference oscillator.

It should be noted that for at least some intended uses, the reference clock used by the receiver will typically drift relative to the reference clock used by the transmitter, and may differ by hundreds of ppm. In the embodiment of fig. 3, the resulting frequency offset between the clock signal output of the PLL and the analog data signal will need to be corrected by a continuous phase rotation in phase interpolator 320. Other digital timing circuit implementations are available in the open literature and will also be suitable for use in the disclosed embodiments.

Fig. 4 shows an illustrative embodiment of demodulator 306. Prior to sampling, the analog channel signal 302 is filtered by a continuous-time linear equalizer ("CTLE") 400 to attenuate out-of-band noise and optionally provide some spectral shaping to improve the response to high frequency components of the received signal. An ADC 304 is provided to digitize the received signal and a digital filter (also referred to as a feed-forward equalizer or "FFE") 402 performs further equalization to further shape the overall channel response of the system and minimize the effect of preamble ISI on the current symbol. FFE402 may also be designed to shorten the channel response of the filtered signal while minimizing any attendant noise enhancement as part of the shaping of the overall channel response.

Adder 405 subtracts an optional feedback signal from the output of FFE402 to minimize the effect of tracking ISI on the current symbol, producing an equalized signal that is coupled to decision element ("slicer") 406. The decision element includes one or more comparators that compare the equalized signal to corresponding decision thresholds to determine which constellation symbol the value of the signal most closely corresponds to for each symbol interval. Herein, the equalized signal may also be referred to herein as a "combined signal".

The decision element 406 accordingly generates a symbol decision sequence (denoted Ak, where k is the time index). In some contemplated embodiments, the signal constellation is a bipolar (non-return-to-zero) constellation representing-1 and +1, requiring the use of only one comparator with a decision threshold of zero. In some other contemplated embodiments, the signal constellation is PAM4(-3, -1, +3), requiring three comparators that employ respective decision thresholds-2, 0, and + 2. (for the sake of generality, the units used to express the symbols and thresholds are omitted, but for purposes of explanation may be assumed to be volts. The comparator outputs may be collectively viewed as a thermometer-coded digital representation of the output symbol decisions, e.g., where 000 represents-3, 100 represents-1, 110 represents +1, and 111 represents + 3. Alternatively, the comparator output may be converted to a binary or gray coded representation.

Feedback filter ("FBF") 407 uses a stored recent output symbol decision (A)_k-1、A_k-1、……、A_k-NWhere N is the filter coefficient f_iNumber of flip-flops, or registers) to derive the feedback signal. Associating each stored symbol with a corresponding filter coefficient f_iMultiplies and combines the products to obtain the feedback signal.

In addition, we note here that the receiver also comprises a filter coefficient adaptation unit, but such considerations are dealt with in the literature and are well known to the person skilled in the art. However, we note here that at least some contemplated embodiments include one or more additional comparators in decision element 406 to be used to compare the combined signal with one or more of the symbol values, thereby providing an error signal that may be used for timing recovery and/or coefficient adaptation.

As the symbol rate increases to the gigahertz range, it becomes increasingly difficult for the ADC 304 and demodulator 306 components to fully perform their required operations within each symbol interval, at which point it becomes advantageous to parallelize their operations. Parallelization generally involves the use of multiple components that share the workload by taking turns and thereby provide more time for each of the various components to complete their operations. Such parallel components are driven by a set of staggered clock signals, such as those shown in FIG. 5. Quad parallelization employs a set of four clock signals, each having a frequency of one quarter of the symbol rate, such that in the set of interleaved clock signals, each symbol interval contains only one upward transition. Although four-fold parallelization is used here for purposes of discussion, the actual degree of parallelization can be higher, e.g., 8-fold, 16-fold, 32-fold, or 64-fold. Furthermore, the degree of parallelization is not limited to powers of 2.

Fig. 6 shows an illustrative receiver with a parallel equalizer implementation, including an optional feedback filter for the DFE. As with the implementation of fig. 4, CTLE 400 filters the channel signals to provide received signals that are provided in parallel to an array of analog-to-digital converters (ADC0-ADC 3). Each of the ADC elements is supplied with a respective one of the staggered clock signals from fig. 5. The clock signals have different phases that cause the ADC elements to sample and digitize the received signal in turn so that only one of the ADC element outputs is transitioning at any given time.

An array of FFEs (FFE0 through FFE3), each FFE forming a weighted sum of the ADC element outputs. The weighted sum employs filter coefficients that are cyclically shifted with respect to each other. FFE0 operates on hold signals from ADC3 (elements operating before CLK 0), ADC0 (elements responsive to CLK 0), and ADC1 (elements operating after CLK 0) such that during assertion of CLK2, the weighted sum produced by FFE0 corresponds to the output of FFE402 (fig. 4). FFE1 operates on hold signals from ADC0 (elements operating before CLK 1), ADC1 (elements responsive to CLK 1), and ADC2 (elements operating after CLK 1) such that the weighted sum corresponds to the weighted sum of FFE402 during assertion of CLK 3. And the operation of the remaining FFEs in the array follow the same pattern as the associated phase shifts. In practice, the number of filter taps may be smaller, or the number of elements in the array may be larger, in order to provide a longer effective output window.

As with the receiver of fig. 4, an adder may combine the output of each FFE with a feedback signal to provide an equalized signal to the corresponding decision element. Fig. 6 shows an array of decision elements (slicer 0 to slicer 3), each operating on an equalized signal derived from a respective FFE output. As with the decision element of fig. 4, the illustrated decision element employs a comparator to determine the symbol most likely represented by the equalized signal. A decision is made when the corresponding FFE output is active (e.g., slicer 0 operates when CLK2 is asserted, slicer 1 operates when CLK3 is asserted, etc.). Preferably, decisions are provided in parallel on the output bus to enable a lower clock rate to be used for subsequent operations.

An array of feedback filters (FBF0 through FBF3) operates on the previous symbol decisions to provide a feedback signal for the summer. Like the FFE, the input to the FBF is cyclically shifted and provides a valid output only when the input corresponds to the contents of FBF 407 (fig. 4), consistent with the time window of the corresponding FFE. In practice, the number of feedback filter taps may be smaller than shown, or the number of array elements may be larger, in order to provide a longer effective output window.

As with the decision elements of fig. 4, the decision elements in fig. 6 may each employ additional comparators to provide timing recovery information, coefficient training information, and/or pre-calculations to develop one or more taps of the feedback filter. In the embodiment of fig. 6, the digital timing circuits are also in parallel, and the timing error estimator 610 accepts the symbol decisions and equalized signal in parallel to determine the timing error estimate to be produced by the estimator 310 (fig. 3). Timing loop filter 612 generates a timing control signal to be produced by filter 312, and phase interpolator 620 operates similarly to phase interpolator 320 to convert the PLL clock signal to a set of interleaved clock signals having uniformly spaced phases and symbol-aligned transitions. A set of delay lines (DL0-DL3) is provided for fine-tuning the individual clock phases relative to each other as needed, for example, to compensate for different propagation delays of the individual ADC elements.

The delay lines may be individually adjusted by the clock skew adjustment circuit 644 based on parameters from the controller 642. The controller 642 may optimize the clock skew adjustment settings based on the reliability indicator from the monitoring circuit. In fig. 6, the monitoring circuit calculates the minimum difference between the equalized signal and the decision threshold (or equivalentlyCalculating the maximum error between the equalized signal and the nominal symbol value) of the received signal. As shown in fig. 7, the margin depends on the sampling instant. If the sampling occurs at the optimal sampling time T_OThen the equalized signal margin 702 is maximized. (margin 702 is shown as a rectangle to account for timing jitter.) if the clock skew Δ is delayed by the sample time, the equalized signal margin 704 decreases (or equivalently increases the equalized signal error).

To effect monitoring of the change in margin, the margin calculator 640 may separately re-determine the minimum difference for each of a series of time windows, optionally determining a weighted average to smooth the margin measurements. And to further enable clock skew optimization for each of the staggered clocks, the margin calculator may track the minimum difference for each ADC element within each time window separately.

One suitable technique for a clock skew adjustment circuit 644 for measuring and controlling skew between staggered clocks is illustrated in FIG. 8. Fig. 8 shows CLK1 skewed from its normal phase delay by Δ relative to CLK0, and further shows the combined signals derived from the two clocks as an exclusive or (or, alternatively, as a logical or) function. The duty cycle of the combined signal is a linear function of the skew delta.

Fig. 9 is an illustrative embodiment of a clock skew adjustment circuit 644 that uses this skew measurement technique. The exclusive or gate derives a combined clock signal, and a low pass filter ("LPF") measures a duty cycle of the combined clock signal. The comparator compares the duty cycle with a reference voltage ('V') provided by the controller_{Reference to}") to generate an error signal. The loop filter converts the error signal to a control signal for delay line DL1 to adjust the skew as needed to drive the error signal to zero.

The clock adjustment circuit 644 includes additional skew measurement and control loops for controlling the relative skew between each pair of adjacent staggered clock signals. An alternate embodiment of the clock skew adjustment circuit controls the phase interpolator to adjust the relative phases of the interleaved clock signals.

During normal operation, the digital timing loop aligns the sampling clock signal with the optimal sampling instant of the analog received signal. Optionally, the controller 642 may fine-tune the relative skew of the staggered clock signals by determining a dependence of the signal margin (or another signal quality indicator) on the relative skew. In one implementation, the controller may perform a small skew adjustment with a given symbol, and if the signal quality degrades, the controller may invert the symbol for subsequent skew adjustments.

However, the signal quality at other sampling instants is valuable for diagnosing performance problems, evaluating the channel, and characterizing jitter tolerance. Eye monitoring involves measuring signal quality over a range of sampling phases within a channel symbol interval. Ideally, this range spans the width of the eye opening in the eye diagram, but a smaller range can generally be sufficient to characterize the channel performance as a function of jitter. Conversely, jitter tolerance may be determined for a given channel performance, whether specified in terms of signal-to-noise ratio, signal margin, or bit error rate.

Since it is impractical to operate the ADC elements of a high-rate receiver quickly to obtain multiple samples in a given symbol interval, and providing additional ADC elements is undesirably expensive, it is proposed herein to deliberately vary the relative skew of at least one of the interleaved clock signals to sample at different phases in every nth channel symbol interval, where n is the number of ADC elements. To prevent samples acquired with a skewed clock signal from corrupting the performance of the digital timing loop, the timing error estimator 610 may be configured to exclude or suppress timing error estimates derived from these samples. More than one of the clock signals may be skewed to enable faster measurement of the open eye opening, as long as there are enough timing error estimates in each cycle.

Note that samples acquired with a skewed clock signal will degrade the performance of FFE elements operating on those samples, but this degradation is expected to be a "graceful degradation," i.e., a gradual, controlled degradation. However, a potential problem for decision feedback equalizers is error propagation through the FBF element, which makes degradation likely to be bursty and unpredictable. This problem can be avoided by minimizing the amplitude of the FBF taps associated with the symbol decisions, which strongly depend on the skewed clock samples. In some implementations, the FBF element can be completely disabled.

Fig. 10 shows an illustrative eye monitoring method that may be implemented by the receiver of fig. 6. Initially, in block 1002, the receiver operates normally to digitize and demodulate a received signal, wherein a digital timing loop operates to synchronize an interleaved clock signal with an optimal sampling instant of a symbol interval in the received signal. After the digital timing loop has locked to the optimal timing, the controller selects which of the interleaved clock signals or clock signals will be skewed to map the eye opening in block 1004 and by implication which of the interleaved clock signals will remain at the optimal sampling phase and continue to be employed to maintain timing lock. In at least some embodiments, the controller iterates through each of the staggered clock signals, performing eye monitoring and phase optimization on each of the clock signals in turn.

In block 1006, the controller configures the timing error estimator to exclude or suppress estimates that rely on samples acquired using the skewed clock signal, maintaining timing lock using only the non-skewed clock signal.

In block 1008, the controller systematically changes the skew of the selected clock signal to determine a signal margin and/or other indicator of symbol decision reliability as a function of the amount of skew. In some embodiments, the deflection range spans the entire eye opening. In other contemplated embodiments, the skew range is limited to whatever extent is necessary to reduce the signal margin (or signal-to-noise ratio or another reliability indicator) below a predetermined value.

In block 1010, the controller analyzes the dependency of the reliability indicator on the skew to determine an optimal skew value for the selected clock signal(s). In block 1012, the controller determines whether each of the clock signals has been selected and optimized, and if not, the method repeats blocks 1004-1012. Once each of the clock signal skews has been optimized, the method is complete.

Numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the claims be interpreted to embrace all such alternatives, equivalents and modifications as fall within the scope of the appended claims.

Claims

1. An integrated receiver circuit, comprising:

a set of analog-to-digital converters sampling a received signal in response to an interleaved clock signal to provide a set of parallel sampled received signals;

an equalizer that converts the set of parallel sampled received signals to a set of parallel equalized signals;

one or more quantizers that derive symbol decisions from the set of parallel equalized signals;

a digital timing circuit that generates the staggered clock signal based on the set of parallel equalized signals;

a clock skew adjustment circuit that provides a controllable skew of at least one of the staggered clock signals relative to at least one other of the staggered clock signals;

a monitoring circuit that provides a reliability indicator of the symbol decisions; and

a controller that determines a dependency of the reliability indicator on the controllable skew.

2. The integrated receiver circuit of claim 1, wherein the reliability indicator is a signal margin measurement.

3. The integrated receiver circuit of claim 1, wherein the reliability indicator is a bit error rate.

4. The integrated receiver circuit of claim 1, wherein the controller sets the controllable skew to optimize the reliability indicator.

5. The integrated receiver circuit of claim 4, wherein the clock skew adjustment circuit provides a controllable skew of each of the staggered clock signals relative to at least one other of the staggered clock signals, and wherein the controller sets the controllable skew of each of the staggered clock signals to optimize the reliability indicator.

6. The integrated receiver circuit of claim 1, wherein the controller systematically sets the controllable skew to map the reliability indicator across an entire width of a decision eye diagram.

7. The integrated receiver circuit of claim 1, wherein as part of generating the staggered clock signal, the digital timing circuit aligns transitions in the staggered clock signal with optimal sampling instants in the received signal by iteratively correcting estimated timing errors estimated by combining the parallel sets of equalized signals with the symbol decisions.

8. The integrated receiver circuit of claim 7, wherein the digital timing circuit excludes, as part of the iterative correction, those estimated timing errors that are dominated by the controllable skew.

9. The integrated receiver circuit of claim 1, wherein the clock skew adjustment circuit controls a programmable delay line for the at least one of the staggered clock signals.

10. The integrated receiver circuit of claim 1, wherein the clock skew adjustment circuit controls at least one phase offset of a phase interpolator, the at least one phase offset controlling a phase of the at least one of the staggered clock signals.

11. A method of fabricating an integrated receiver circuit, the method comprising patterning an integrated circuit substrate to provide:

12. The method of claim 11, further comprising: configuring the controller to set the controllable skew to optimize the reliability indicator.

13. The method of claim 12, wherein the clock skew adjustment circuit is configured to provide a controllable skew of each of the staggered clock signals relative to at least one other of the staggered clock signals, and wherein the controller is configured to set the controllable skew of each of the staggered clock signals to optimize the reliability indicator.

14. A method, the method comprising:

operating a set of digital-to-analog converters in response to an interleaved clock signal to provide a set of parallel sampled received signals;

filtering the set of parallel sampled received signals to obtain a set of parallel equalized signals;

quantizing the set of parallel equalized signals to derive symbol decisions;

generating the staggered clock signal based on the set of parallel equalized signals;

controlling skew of at least one of the staggered clock signals relative to at least one other of the staggered clock signals;

monitoring a reliability indicator of the symbol decision; and

determining a dependency of the reliability indicator on the skew.

15. The method of claim 14, wherein the reliability indicator is a signal margin measurement.

16. The method of claim 14, wherein the reliability indicator is a bit error rate.

17. The method of claim 14, further comprising: setting the skew to optimize the reliability indicator.

18. The method of claim 14, wherein the determining comprises mapping the dependency of the reliability indicator across an entire width of a decision eye diagram.

19. The method of claim 14, wherein the generating the staggered clock signal comprises aligning transitions in the staggered clock signal with optimal sampling instants in the received signal by iteratively correcting the estimated timing errors, the timing errors estimated by combining the parallel sets of equalized signals with the symbol decisions.

20. The method of claim 19, wherein the iterative correction employs only those estimated timing errors that are not dominated by the skew.