CN113471288A - Fully-depleted silicon-on-insulator substrate, transistor, preparation method and application thereof - Google Patents

Fully-depleted silicon-on-insulator substrate, transistor, preparation method and application thereof Download PDF

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Publication number
CN113471288A
CN113471288A CN202110548134.7A CN202110548134A CN113471288A CN 113471288 A CN113471288 A CN 113471288A CN 202110548134 A CN202110548134 A CN 202110548134A CN 113471288 A CN113471288 A CN 113471288A
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silicon
layer
silicon oxide
lines
top layer
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CN113471288B (en
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亨利·H·阿达姆松
王桂磊
戚璇
王云
叶甜春
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Guangdong Greater Bay Area Institute of Integrated Circuit and System
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Guangdong Greater Bay Area Institute of Integrated Circuit and System
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention relates to a fully depleted silicon-on-insulator substrate, a transistor, a preparation method and application thereof. The preparation method of the fully depleted silicon-on-insulator substrate comprises the following steps: forming a silicon oxide layer on the backing silicon layer; photoetching and etching are carried out, so that the silicon oxide forms a plurality of grooves, the grooves penetrate through the silicon oxide layer and penetrate into the backing silicon layer, the surface of the backing silicon layer is divided into a plurality of silicon lines, and the silicon oxide layer is divided into a plurality of silicon oxide lines; forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide lines; thinning the silicon top layer; coating photoresist on the surface of the silicon top layer, and patterning to expose the silicon top layer covering the silicon oxide lines and the adjacent silicon oxide line interval regions; performing oxygen injection; and then annealing to form a silicon oxide isolation layer. The substrate manufactured by the invention can reduce the parasitic capacitance and improve the running speed; the leakage can be reduced, and the power consumption is lower; latch-up effects can also be eliminated; the interference of substrate pulse current can be inhibited; while introducing strain.

Description

Fully-depleted silicon-on-insulator substrate, transistor, preparation method and application thereof
Technical Field
The invention relates to the field of semiconductor production processes, in particular to a fully-depleted silicon-on-insulator substrate, a transistor and a preparation method thereof.
Background
The non-planar Fin FET device structure serving as a core device of the non-planar Fin FET device structure has strong grid control capability and strong inhibition capability on short channel effect, but the process flow of the Fin FET device is complex; compared with the three-dimensional Fin FET process, the planar SOI device process has the advantages that the number of photoetching plates is much smaller, the process is relatively easier, and the process cost is greatly reduced. However, how to fabricate an SOI substrate with small parasitic capacitance and small leakage is still a difficulty.
The invention is therefore proposed.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a fully depleted silicon-on-insulator substrate, and the substrate prepared by the method can reduce parasitic capacitance and improve the running speed; the leakage can be reduced, and the power consumption is lower; latch-up effects can also be eliminated; the interference of substrate pulse current can be inhibited; while introducing strain.
In order to achieve the above object, the present invention provides the following technical solutions.
A method for preparing a fully depleted silicon-on-insulator substrate, comprising:
forming a silicon oxide layer on the backing silicon layer;
photoetching and etching are carried out, so that a plurality of grooves are formed in the silicon oxide, the grooves penetrate through the silicon oxide layer and penetrate into the backing silicon layer, the surface of the backing silicon layer is separated into a plurality of silicon lines, and the silicon oxide layer is separated into a plurality of silicon oxide lines;
forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide lines;
thinning the silicon top layer;
coating photoresist on the surface of the silicon top layer, and patterning to expose the silicon top layer covering the silicon oxide lines and the adjacent silicon oxide line interval regions;
performing oxygen implantation on the exposed area, wherein the depth of the oxygen implantation is deep into the position of the silicon oxide line and is not higher than the top of the silicon oxide line;
and then annealing to form a silicon oxide isolation layer.
A preparation method of a fully depleted transistor comprises the following steps:
the silicon-on-insulator substrate obtained by the preparation method;
and manufacturing a transistor on the silicon top layer region above the silicon oxide isolation layer.
Compared with the prior art, the invention achieves the following technical effects:
(1) compared with a non-planar Fin FET device structure, the FDSOI (fully depleted silicon on insulator) substrate is simpler in device manufacturing process and lower in cost;
(2) the isolation layer between the top silicon and the back silicon is manufactured through the processes of forming the groove, filling silicon, injecting oxygen and annealing, so that the effects of reducing parasitic capacitance, improving the running speed, reducing electric leakage, eliminating latch-up effect, inhibiting substrate pulse current interference and the like can be achieved; meanwhile, strain is introduced, so that the mobility of the device is improved;
(3) the fully depleted transistor manufactured by the invention has the advantages of excellent grid control capability, lower electric leakage and the like.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1-6 are topographical views of an FDSOI substrate and various steps in the transistor fabrication process provided by the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Although the existing FDSOI substrate has the advantages of small parasitic capacitance, high integration density, high speed and the like compared with the common substrate, the existing FDSOI substrate still cannot meet the requirements of increasingly developed precise devices.
Therefore, the invention provides a novel FDSOI manufacturing process for further reducing the parasitic capacitance, improving the operation speed, reducing the electric leakage, eliminating the latch-up effect, inhibiting the substrate pulse current interference and the like, and the specific process is as follows.
First, a silicon plate was selected as a backing layer, and a silicon oxide layer was formed thereon. The growth method includes but is not limited to APCVD, UHVCVD, LPCVD, RTCVD, PECVD or oxidation growth, etc., preferably thermal oxidation, dry or wet oxidation can be used.
Patterning and etching are then carried out, typically with the aid of a photoresist, which may be combined with CMP, wet etching, dry etching, Atomic Layer Etching (ALE) (dry or wet), gas oxidation + wet etching, etc. Etching to form multiple trenches in the silicon oxide layerAnd the grooves penetrate through the silicon oxide layer and penetrate into the backing silicon layer, so that the surface of the backing silicon layer is divided into a plurality of silicon lines, and the silicon oxide layer is divided into a plurality of silicon oxide lines. Since this step etches the two materials (the masking layer and the backing silicon) which are chemically different, it is necessary to select different etchants for the step etching. Taking silicon oxide as an example, suitable etchants for wet etching include, but are not limited to, buffered hydrofluoric acid (BHF), Buffered Oxide Etchant (BOE), and the like. The silicon can be HF-HNO3Corrosive agents, alkaline corrosive liquids, and the like. The silicon lines and the silicon oxide lines formed in the step have important influence on the performance of the substrate, the width of 10 nm-100 nm is preferably adopted, the depth-to-width ratio of the groove is controlled to be more than 2:1, and the height of the silicon lines defines the thickness of the insulating layer in the finally obtained FDSOI. The thickness of the silicon oxide layer can be determined appropriately according to the above requirements.
The silicon layer is next formed as single crystal silicon, preferably by selective epitaxial growth. The silicon top layer fills the trench and covers the silicon oxide layer.
The top silicon layer is thinned, typically by CMP.
And then coating photoresist on the surface of the silicon top layer, and patterning to expose the silicon top layer covering the silicon oxide lines and the adjacent silicon oxide line spacing regions, wherein the silicon in the spaces between the silicon oxide lines in the partial region is oxidized in the next step.
And then carrying out oxygen implantation on the exposed area, wherein the depth of the oxygen implantation is deep into the position of the silicon oxide line and is not higher than the top of the silicon oxide line. And then combining with annealing treatment, wherein the implanted oxygen consumes silicon at intervals among the silicon oxide lines and converts the silicon into silicon oxide, so that a continuous silicon oxide layer is formed, the back lining silicon and the top layer silicon of the partial area are completely isolated, namely, a silicon oxide isolation layer is formed in the step, and a semiconductor device is manufactured above the silicon oxide isolation layer.
Taking the above FDSOI fabrication transistor as an example, the transistor is fabricated on the silicon top layer region above the silicon oxide isolation layer.
The present invention also provides a specific embodiment, which is described below with reference to the drawings.
Examples
In a first step, a silicon oxide layer 2 is formed on a backing silicon layer 1 to obtain the topography shown in fig. 1.
In the second step, photolithography and etching are performed to form a plurality of trenches 3 in the silicon oxide layer 2, thereby obtaining the topography shown in fig. 2. Wherein the trench 3 penetrates through the silicon oxide layer 2 and penetrates into the backing silicon layer 1, so that the surface of the backing silicon layer 1 is divided into a plurality of silicon lines 1a, the silicon oxide layer 2 is divided into a plurality of silicon oxide lines 2a, the depth-to-width ratio of the trench 3 is more than 2:1, and the width of each of the silicon lines 1a and the silicon oxide lines 2a is 10 nm-100 nm.
Thirdly, a silicon top layer 3 is formed by selective epitaxial growth, resulting in the topography shown in fig. 3.
Fourthly, the top silicon layer 3 is thinned to obtain the morphology shown in fig. 4.
And fifthly, coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the interval regions of the adjacent silicon oxide lines.
And sixthly, performing oxygen implantation on the area exposed in the fifth step, wherein the depth of the oxygen implantation is deep into the position where the silicon oxide line 2a is located and is not higher than the top of the silicon oxide line 2 a.
And seventhly, annealing to form the silicon oxide isolation layer 5, so as to obtain the SOI substrate with small parasitic capacitance, high running speed, small leakage and no latch-up effect, as shown in FIG. 5.
In an eighth step, a transistor structure 6 is fabricated on said top silicon layer region above the silicon oxide isolation layer 5 (the box in the figure is only schematic and no specific structure is shown), as shown in fig. 6.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A method for preparing a fully depleted silicon-on-insulator substrate, comprising:
forming a silicon oxide layer on the backing silicon layer;
photoetching and etching are carried out, so that a plurality of grooves are formed in the silicon oxide, the grooves penetrate through the silicon oxide layer and penetrate into the backing silicon layer, the surface of the backing silicon layer is separated into a plurality of silicon lines, and the silicon oxide layer is separated into a plurality of silicon oxide lines;
forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide lines;
thinning the silicon top layer;
coating photoresist on the surface of the silicon top layer, and patterning to expose the silicon top layer covering the silicon oxide lines and the adjacent silicon oxide line interval regions;
performing oxygen implantation on the exposed area, wherein the depth of the oxygen implantation is deep into the position of the silicon oxide line and is not higher than the top of the silicon oxide line;
and then annealing to form a silicon oxide isolation layer.
2. The method of claim 1, wherein the trench has an aspect ratio of 2:1 or more.
3. The method of claim 1, wherein the top silicon layer is formed by selective epitaxial growth.
4. The method of claim 1, wherein the thinning is performed by chemical mechanical polishing.
5. The production method according to claim 1, wherein the silicon oxide layer is formed by a thermal oxidation method.
6. The production method according to any one of claims 1 to 5, wherein the width of the silicon line and the silicon oxide line is 10nm to 100 nm.
7. A silicon-on-insulator substrate obtained by the production method according to any one of claims 1 to 6.
8. Use of a silicon-on-insulator substrate as claimed in claim 7 in a semiconductor device.
9. A method for preparing a fully depleted transistor, comprising:
a silicon-on-insulator substrate obtained by the production method according to any one of claims 1 to 6;
and manufacturing a transistor on the silicon top layer region above the silicon oxide isolation layer.
10. A silicon-on-insulator substrate obtained by the production method according to claim 9.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998015011A1 (en) * 1996-09-30 1998-04-09 Siemens Aktiengesellschaft Power mos component
CN1431717A (en) * 2003-02-14 2003-07-23 中国科学院上海微系统与信息技术研究所 Structure for lowering series resistor between source and drain in silicon transistors on insulator as well as implement method
KR20060004079A (en) * 2004-07-08 2006-01-12 삼성전자주식회사 Mos transistor with local soi and method thereof
CN101459052A (en) * 2007-12-11 2009-06-17 茂德科技股份有限公司 Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer
US20170005112A1 (en) * 2015-06-30 2017-01-05 International Business Machines Corporation Implementing a hybrid finfet device and nanowire device utilizing selective sgoi
US20180040697A1 (en) * 2015-06-22 2018-02-08 International Business Machines Corporation Fully depleted silicon-on-insulator device formation
CN110941046A (en) * 2019-11-22 2020-03-31 中国科学院微电子研究所 Method for manufacturing SOI silicon grating
CN112635492A (en) * 2020-12-02 2021-04-09 广东省大湾区集成电路与系统应用研究院 Strain GeSiOI substrate and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998015011A1 (en) * 1996-09-30 1998-04-09 Siemens Aktiengesellschaft Power mos component
CN1431717A (en) * 2003-02-14 2003-07-23 中国科学院上海微系统与信息技术研究所 Structure for lowering series resistor between source and drain in silicon transistors on insulator as well as implement method
KR20060004079A (en) * 2004-07-08 2006-01-12 삼성전자주식회사 Mos transistor with local soi and method thereof
CN101459052A (en) * 2007-12-11 2009-06-17 茂德科技股份有限公司 Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer
US20180040697A1 (en) * 2015-06-22 2018-02-08 International Business Machines Corporation Fully depleted silicon-on-insulator device formation
US20170005112A1 (en) * 2015-06-30 2017-01-05 International Business Machines Corporation Implementing a hybrid finfet device and nanowire device utilizing selective sgoi
CN110941046A (en) * 2019-11-22 2020-03-31 中国科学院微电子研究所 Method for manufacturing SOI silicon grating
CN112635492A (en) * 2020-12-02 2021-04-09 广东省大湾区集成电路与系统应用研究院 Strain GeSiOI substrate and manufacturing method thereof

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