CN113471224A - SOI structure and manufacturing method thereof, MEMS device and manufacturing method thereof - Google Patents
SOI structure and manufacturing method thereof, MEMS device and manufacturing method thereof Download PDFInfo
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- CN113471224A CN113471224A CN202111019284.5A CN202111019284A CN113471224A CN 113471224 A CN113471224 A CN 113471224A CN 202111019284 A CN202111019284 A CN 202111019284A CN 113471224 A CN113471224 A CN 113471224A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00563—Avoid or control over-etching
- B81C1/00571—Avoid or control under-cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Abstract
The invention relates to an SOI structure and a manufacturing method, and also relates to a MEMS device manufactured by utilizing the SOI structure and a method for manufacturing the MEMS device; the insulating layer of the SOI structure is mainly designed into a silicon oxide-silicon nitride-silicon oxide multilayer structure, and a raised retaining wall structure is formed on a silicon nitride layer, when an MEMS device is manufactured, an upper silicon dioxide layer is used as a stop layer for deep silicon etching of an isolation groove, so that an enough process window for the deep silicon etching is ensured, and the fatal problem of short circuit caused by insufficient etching of the isolation groove is avoided; when the mask layer for etching the comb-tooth electrode and the isolation groove is removed, the VHF gas phase etching technology in the prior art is replaced by a wet etching process, the silicon nitride layer is used as a stop layer for wet etching, and the silicon nitride retaining wall structures on two sides of the bottom of the isolation groove can effectively prevent the lateral corrosion to the insulating layer in the wet etching process, so that the insulating effect of the isolation groove and the reliability of a device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an SOI structure and a manufacturing method thereof, and also relates to an MEMS device manufactured by the SOI structure and a method for manufacturing the MEMS device.
Background
SOI (Silicon-On-Insulator), i.e., Silicon On Insulator, is a multi-layer structure formed by introducing a buried oxide layer between the top Silicon and the back substrate Silicon. Due to the unique superiority of the SOI structure, the device based on the structure can essentially reduce junction capacitance and leakage current, improve switching speed, reduce power consumption, realize high-speed and low-power-consumption operation, and has performance obviously superior to that of bulk silicon devices and circuits. At present, devices manufactured by adopting SOI structures are widely applied to most fields of microelectronics, and are also applied to other fields such as photoelectronics, MEMS and the like.
In MEMS device fabrication processes, SOI technology is one of the most widely used technologies, and many devices often require electrical isolation. In order to realize the purpose of electric isolation, a comb-tooth electrode structure and an isolation groove can be etched on the top silicon of the SOI structure wafer through deep silicon, an oxygen buried layer is not etched when the comb-tooth electrode is etched, and the bottom of the isolation groove is exposed out of the oxygen buried layer, so that the electrodes on two sides of the isolation groove can realize the insulation between the electrodes through the oxygen buried layer. Since the buried oxide layer of the SOI wafer used in the conventional MEMS device fabrication is a layer structure and is a silicon dioxide layer, the thickness of the silicon dioxide layer remained at the isolation trench is sufficient and less than 1.5 μm to ensure good insulation effect of the MEMS device under the operating voltage. In the prior art, when an SOI structure is manufactured, a silicon dioxide layer with a thickness of about 1 micron is formed on the surface of a back substrate silicon, and another silicon wafer with low resistivity is bonded with the surface of the silicon dioxide to form the SOI structure. When the SOI structure is used for manufacturing an MEMS device, a silicon dioxide mask layer is usually formed on the top silicon surface of the SOI structure, then comb-teeth electrodes and isolation grooves are formed through patterning and deep silicon etching technologies, and finally the silicon dioxide mask layer remained on the surfaces of the comb-teeth electrodes is removed through a VHF (very high frequency) gas phase etching technology. When the isolation groove is etched, the silicon dioxide layer in the middle of the SOI structure is used as a stop layer, but due to the influence of isotropy of a deep silicon etching process and a VHF (very high frequency) gas phase etching process, the silicon dioxide buried oxide layer reserved at the isolation groove can be etched with a certain thickness when the two etching processes are carried out, so that the silicon dioxide layer which is finally reserved at the isolation groove and plays an isolation and insulation role becomes thin and uneven in thickness, the breakdown conduction problem under the working voltage is caused, particularly for a device with higher working voltage, the isolation defective rate is up to more than 50% according to the process of the structure at present, the process stability cannot be guaranteed, and the difficulty in mass production is large.
In order to solve the isolation insulation problem, even if the buried oxide layer in the SOI structure is thickened, the thickness of the silicon dioxide layer left in the isolation trench is not uniform, and the lateral etching of the silicon dioxide at the bottoms of the two sides of the isolation trench occurs during the etching process, which may affect the reliability of the device. The invention patent with publication number CN110085550A discloses an insulating layer structure for semiconductor products, which improves the buried oxide layer in the above conventional SOI structure, and in the technical solution disclosed in the patent, there is a solution in which the buried oxide layer originally composed of a layer of silicon dioxide is replaced by one of silicon oxynitride, silicon nitride, polysilicon and amorphous silicon, and there is a solution in which the entire buried oxide layer is composed of multiple layers of different materials, and the purpose of the solution is to improve the radio frequency characteristics of the insulating layer structure. If the insulating layer structure shown in fig. 1 in the patent is used for solving the problem of poor insulation of the isolation trench of the MEMS device, the problem of lateral corrosion of the oxide layers at the bottoms of the two sides of the isolation trench in the etching process cannot be avoided, and the reliability of the device cannot be effectively improved. In view of the above, the inventor has made an improvement on the structure shown in fig. 1, and proposed a multi-layer insulating layer structure with a retaining wall, and disclosed a method for manufacturing the multi-layer insulating layer structure, and also disclosed a MEMS device manufactured by using the multi-layer insulating layer structure and a method for manufacturing the MEMS device.
Disclosure of Invention
The invention firstly discloses an improved SOI structure based on a traditional SOI structure, wherein a buried oxide layer is mainly designed into a multilayer structure, and a retaining wall structure is designed in the buried oxide layer, so that the condition of lateral corrosion when a groove is engraved on top silicon to the buried oxide layer can be effectively avoided by utilizing the retaining wall structure, for example, when the buried oxide layer of the SOI structure is utilized to realize the isolation and insulation effect, the improvement of the isolation and insulation effect and the improvement of the reliability are facilitated. In order to realize the purpose of the invention, the technical scheme adopted by the invention is as follows:
an SOI structure, comprising at least a first silicon layer, an insulating layer on the surface of the first silicon layer, and a second silicon layer bonded with the upper surface of the insulating layer, wherein the insulating layer comprises at least a lower silicon dioxide layer formed on the upper surface of the first silicon layer, and a silicon nitride layer formed on the upper surface of the lower silicon dioxide layer, characterized in that: protruding barricade structure and depressed part are formed to the upper surface of silicon nitride layer, and silicon dioxide layer is filled to the depressed part, goes up the upper surface on silicon dioxide layer and barricade structure's upper surface parallel and level.
The retaining wall structure in the insulating layer is formed in two ways, one way is that the upper surface of the lower silicon dioxide layer keeps a plane structure, namely after the lower silicon dioxide layer with the thickness of about 1-2 microns is deposited, a silicon nitride layer is directly deposited on the upper surface of the lower silicon dioxide layer, then a raised retaining wall structure is formed on the upper surface of the silicon nitride layer in a photoetching way, and the thickness of the thinnest part of the silicon nitride layer is between 450-550 nanometers; the other mode is as follows: after the lower silicon dioxide layer with the thickness of about 1-2 microns is deposited, a convex part is formed on the upper surface of the lower silicon dioxide layer through a photoetching mode, then a silicon nitride layer is deposited on the surface of the lower silicon dioxide layer, and due to the existence of the convex part, the silicon nitride deposited on the convex part naturally forms a retaining wall structure.
The upper silicon dioxide layer on the upper surface of the retaining wall structure is removed during planarization treatment through CMP after deposition, the thickness of the upper silicon dioxide layer existing in the concave part between the adjacent retaining wall structures is 1-1.5 micrometers, and the resistivity of the adopted first silicon layer and the second silicon layer is 0.1-10000 ohm-cm.
According to the different forming modes of the retaining wall structure, the manufacturing method of the SOI structure is divided into the following two types:
the method comprises the following steps:
(1) providing a first silicon wafer, and forming a lower silicon dioxide layer on the upper surface of the first silicon wafer;
(2) forming a convex part on the upper surface of the lower silicon dioxide layer by etching;
(3) depositing a silicon nitride layer on the upper surface of the lower silicon dioxide layer, wherein the silicon nitride layer on the lower silicon dioxide layer forms a retaining wall structure and a concave part along with the shape;
(4) forming an upper silicon dioxide layer on the upper surface of the silicon nitride layer;
(5) carrying out planarization treatment on the surface of the upper silicon dioxide, wherein the planarized surface of the upper silicon dioxide is a plane and the upper silicon dioxide layer positioned on the upper surface of the retaining wall structure is removed;
(6) and preparing a second silicon wafer, and bonding and connecting one surface of the second silicon wafer with the surface of the planarized upper silicon dioxide layer.
The method 2 comprises the following steps:
(1) providing a first silicon wafer, and forming a lower silicon dioxide layer on the upper surface of the first silicon wafer;
(2) depositing a silicon nitride layer on the upper surface of the lower silicon dioxide layer;
(3) forming a raised retaining wall structure and a concave part on the upper surface of the silicon nitride layer by etching;
(4) forming an upper silicon dioxide layer on the upper surface of the silicon nitride layer;
(5) carrying out planarization treatment on the surface of the upper silicon dioxide, wherein the planarized surface of the upper silicon dioxide is a plane and the upper silicon dioxide layer positioned on the upper surface of the retaining wall structure is removed;
(6) and preparing a second silicon wafer, and bonding and connecting one surface of the second silicon wafer with the surface of the planarized upper silicon dioxide layer.
The insulating layer in the SOI structure is formed by a plurality of layers of insulating films made of different materials, the total thickness of the insulating layers of the multilayer structure is larger than that of a layer of structure generally adopted in the prior art, when the improved SOI structure is used for achieving the insulating purpose through the isolation groove, the process window can be ensured to be sufficient when the isolation groove is etched by deep silicon, the thickness of the insulating layer reserved at the isolation groove after etching is also sufficient, and the problem of breakdown conduction caused by poor insulativity at the position of the isolation groove can be avoided.
In addition, the upper silicon dioxide layer and the lower silicon dioxide layer are connected at intervals by the silicon nitride layer, which is beneficial to being compatible with a wet etching process, especially when the SOI structure is used for manufacturing an MEMS device with an isolation groove, the upper silicon dioxide layer is used as a stop layer of a deep silicon etching isolation groove, because silicon dioxide is usually used as a mask layer when a comb electrode and the isolation groove are etched, the mask layer needs to be removed after the comb electrode and the isolation groove are etched, the conventional process is usually realized by a VHF (very high frequency) vapor phase etching process, if an insulating layer structure is adopted, the silicon dioxide layer at the bottom of the isolation groove can be etched in different degrees in the etching process, the problem of uneven thickness can be presented, and the isolation insulativity of the device can be influenced. In the invention, because the bottom of the upper silicon dioxide layer is the silicon nitride layer, the silicon nitride has better insulation property, more compact structure and more corrosion resistance compared with the silicon dioxide, when the mask layer is removed, the current VHF gas phase etching process can be replaced by wet etching, the concave part of the silicon nitride layer is used as a reaction stopping layer for protecting the lower silicon dioxide layer during the wet etching, and the retaining wall structure of the silicon nitride layer is used as a reaction stopping layer for preventing the side etching corrosion during the wet etching, thereby not only improving the insulation effect of the device, but also being beneficial to improving the reliability of the device.
In the structure of the invention, because the raised retaining wall structures are formed on the surface of the silicon nitride layer, when the SOI structure is used for manufacturing an MEMS device with an isolation groove, the isolation groove is arranged between the two retaining wall structures, so that when the mask layer is removed by wet etching, the upper silicon dioxide layer between the two retaining wall structures is etched due to the existence of the silicon nitride retaining wall structures, but lateral corrosion cannot be formed.
The invention also discloses an MEMS device manufactured by utilizing the SOI structure, which is realized by adopting the following technical scheme:
a MEMS device comprises the SOI structure, grooves are formed in a second silicon layer of the SOI structure, the surface of an insulating layer at the bottom of the groove is exposed, and retaining wall structures are located on the side portions of the bottom of the groove.
And further, grooving on the second silicon layer to form a comb tooth electrode and an isolation groove, wherein the etching depth of the comb tooth electrode does not expose the upper surface of the insulating layer, the upper surface of the insulating layer at the bottom of the isolation groove is exposed, and two sides of the bottom of the isolation groove are respectively provided with a retaining wall structure.
Furthermore, the width of the isolation groove is less than or equal to the gap between two adjacent retaining wall structures.
Furthermore, the bottom of the isolation groove is exposed out of the upper surface of the silicon nitride layer.
The MEMS device with the structure has good insulating and isolating effect because the thickness of the insulating layer reserved at the bottom of the isolation groove is enough, and the problem of breakdown and conduction under working voltage can not occur. And because the silicon nitride retaining wall structures are arranged on the two sides of the bottom of the isolation groove, the problem of reliability reduction caused by transverse corrosion on the two sides of the isolation groove in the process of etching the mask layer is effectively solved.
The invention also discloses a manufacturing method of the MEMS device, which is realized by the following technical scheme:
a manufacturing method of MEMS device is based on the manufacturing method of SOI structure, and the following steps are executed continuously:
(7) forming a patterned mask layer on the upper surface of the second silicon wafer, wherein the mask layer is silicon dioxide;
(8) taking the mask layer as a mask and the silicon dioxide layer as an etching stop layer, and etching the groove on the second silicon wafer to enable the retaining wall structure to be positioned at the side part of the groove bottom;
(9) and removing the mask layer and the upper silicon dioxide layer exposed at the bottom of the groove by using the retaining wall structure and the recessed part of the silicon nitride layer as reaction stop layers through a wet etching process.
Furthermore, the groove etched by using the silicon dioxide layer as the etching stop layer is an isolation groove, and two sides of the bottom of the isolation groove are respectively provided with a retaining wall structure.
Furthermore, the etching width of the isolation groove is less than or equal to the gap between two adjacent retaining wall structures.
Furthermore, the groove etched on the second silicon wafer also comprises a comb tooth electrode, and the etching depth of the comb tooth electrode needs to ensure that the insulating layer at the bottom of the second silicon wafer is not exposed.
The buried oxide layer structure of the existing SOI structure is improved, the problem of lateral corrosion is solved when the SOI structure is used for deep groove etching, when the buried oxide layer structure is used for realizing a good insulation effect of an isolation groove, the buried oxide layer of the existing single-layer silicon dioxide structure is designed into a multilayer structure, an upper silicon dioxide layer is used as a stop layer for deep silicon etching of the isolation groove, a sufficient process window of a deep silicon etching process is ensured, and the fatal avoidance problem of short circuit caused by insufficient etching of the isolation groove is solved; when the mask layer of the etched comb electrode and the isolation groove is removed, the VHF gas phase etching technology in the prior art is not adopted, lateral corrosion can be caused to insulating layers on two sides of the bottom of the isolation groove due to the isotropic characteristic of the VHF gas phase etching technology, the problem of overlarge side digging amount can be caused, byproducts generated by the VHF gas phase etching are more, and the residues are difficult to remove on the side wall of the isolation groove. In view of the above consideration, the invention replaces the VHF vapor phase etching technology with the wet etching, when the mask layer is removed by the wet etching, the silicon nitride can be used as a reaction stop layer of the wet etching due to the characteristic of excellent corrosion resistance, so that the mask layer can be completely removed, the lower silicon dioxide layer below the silicon nitride layer is protected, the insulating layer at the bottom of the isolation groove is enough in thickness, the problem of uneven thickness cannot occur, and the insulating isolation effect is favorably improved. The defect of more byproducts in the VHF gas phase etching technology can be avoided by wet etching, and residues on the side wall of the isolation groove can be effectively reduced. The silicon nitride retaining wall structures on two sides of the bottom of the isolation groove can effectively prevent lateral corrosion to the insulating layer in the wet etching process, can avoid the problem of overlarge lateral digging amount, and further contributes to improving the reliability of devices.
Drawings
FIGS. 1-6 are schematic cross-sectional views of various stages in the fabrication of an SOI structure in accordance with an embodiment of the present invention;
fig. 7-9 are schematic cross-sectional views illustrating different stages in fabricating a MEMS device using the SOI structure of fig. 6 according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The following examples of the present embodiment are developed by taking an SOI structure as an example for realizing an isolation insulation application, and first, an SOI structure and a method for manufacturing the SOI structure are disclosed, in which the SOI structure includes at least a first silicon layer 100, an insulating layer, and a second silicon layer 500 from bottom to top as shown in fig. 6. The SOI structure (silicon on insulator) is commonly used in the fabrication of MEMS devices, primarily using an intermediate buried oxide layer to achieve insulating isolation between electrodes. Unlike the conventional SOI structure in which a single silicon dioxide layer is used to form a buried oxide layer, the insulating layer in this embodiment is formed by combining multiple layers of insulating materials of different materials, where the multiple layers have at least a three-layer structure, i.e., at least a lower silicon dioxide layer 200, a silicon nitride layer 300, and an upper silicon dioxide layer 400 from bottom to top. Unlike the structure shown in fig. 1 of the patent publication No. CN110085550A, the present invention forms at least two raised retaining wall structures on the upper surface of the silicon nitride layer 300, and mainly utilizes the retaining wall structures to prevent the insulating layer at the bottom of the two sides of the isolation trench from being laterally etched during the process of etching the mask layer.
The retaining wall structure in the structure has two forming modes: after the upper surface of the lower silicon dioxide layer 200 is kept in a planar structure, namely, the lower silicon dioxide layer 200 with the thickness of about 1-2 micrometers (preferably 1.5 micrometers) is deposited, a silicon nitride layer 300 is directly deposited on the upper surface of the lower silicon dioxide layer, and then a raised retaining wall structure is formed on the upper surface of the silicon nitride layer 300 through a photoetching mode. In this way, the deposited silicon nitride layer 300 is relatively thick, and more silicon nitride needs to be etched, and the thickness of the remaining silicon nitride except the retaining wall structure needs to be maintained between 450 nm and 550 nm, preferably 500 nm. Another approach is shown in fig. 1-6: after the lower silicon dioxide layer 200 with the thickness of 1-2 microns (preferably 1.5 microns) is deposited, at least two convex parts 201 are formed on the upper surface of the lower silicon dioxide layer 200 through a photoetching mode, then a silicon nitride layer 300 is deposited on the surface of the lower silicon dioxide layer 200, and due to the existence of the convex parts 201, the silicon nitride layer 300 forms a retaining wall structure and a concave part along with the shape, so that the invention recommends to form the lower silicon dioxide layer by adopting a second mode from the aspects of process realization difficulty and cost.
The surface of the upper silicon dioxide layer 400 on the upper surface of the retaining wall structure after deposition is convex, planarization treatment needs to be performed in a CMP mode, the upper silicon dioxide layer 400 on the upper surface of the retaining wall structure is removed during CMP, and the thickness of the upper silicon dioxide layer 400 remaining in the concave part between adjacent retaining wall structures is 1-1.5 micrometers, preferably 1 micrometer. The first silicon layer 100 and the second silicon layer 500 have a resistivity of 0.1 to 10000 ohm-cm.
According to the different formation methods of the retaining wall structure, the manufacturing method of the SOI structure can be divided into the following two methods:
wherein method 1 is as shown in fig. 1 to 6:
(1) preparing a first silicon wafer 100 with low resistivity, and forming a lower silicon dioxide layer 200 with a thickness of about 1-2 microns on the upper surface of the first silicon wafer 100;
(2) at least two convex parts 201 are formed on the upper surface of the lower silicon dioxide layer 200 in a photoetching and etching mode, and a plurality of groups of two convex parts 201 which are close to each other are formed as a group;
(3) then depositing a silicon nitride layer 300 with a thickness of about 450-550 nm on the surface of the lower silicon dioxide layer 200, wherein the silicon nitride layer 300 deposited on the protrusion 201 forms a raised retaining wall structure, and a recess is formed between the retaining wall structures;
(4) forming an upper silicon dioxide layer 400 on the surface of the silicon nitride layer 300;
(5) planarizing the upper silicon dioxide surface, wherein the planarized upper silicon dioxide surface is a plane and the upper silicon dioxide layer on the upper surfaces of the retaining wall structures is removed, and the thickness of the upper silicon dioxide layer 400 in the concave part between the adjacent retaining wall structures is about 1-1.5 microns;
(6) a second silicon wafer 500 is prepared and one of the surfaces of the second silicon wafer 500 is bonded to the planarized surface of the upper silicon dioxide layer 400.
The method 2 comprises the following steps: the difference of the method from the method 1 is mainly embodied in the step (2) and the step (3), and the rest steps are the same as the corresponding steps of the method 1. In the present invention, when depositing silicon nitride, the surface of the lower silicon dioxide layer 200 is a plane, the step (2) is to directly deposit the silicon nitride layer 300 on the surface of the lower silicon dioxide layer 200 with a planar structure, the step (3) is to form at least two convex retaining wall structures on the upper surface of the silicon nitride layer 300 by photolithography and etching, a recess is formed between adjacent retaining wall structures, and the retaining wall structures are completely composed of silicon nitride.
The MEMS device manufactured by using the SOI structure as described above can help to improve the insulation effect of the isolation trench, and the MEMS device structure as shown in fig. 9 includes the SOI structure as described above, where the comb-teeth electrode 501 and the isolation trench 502 are etched on the second silicon layer 500 of the SOI structure, where the comb-teeth electrode 501 is etched to a depth that does not expose the upper surface of the insulating layer, the bottom of the isolation trench 502 exposes the upper surface of the insulating layer to realize the insulation between the electrodes on both sides, and the isolation trench 502 is located at the gap between each set of two retaining wall structures. When etching the isolation trench 502, the width of the isolation trench 502 is not more than the gap between each two retaining wall structures, preferably the same as the gap between the retaining wall structures, and the bottom of the isolation trench 502 is exposed out of the upper surface of the silicon nitride layer 300.
The MEMS device with the structure has good insulating and isolating effects because the thickness of the insulating layer reserved at the bottom of the isolating groove 502 is enough, and the problem of breakdown and conduction under working voltage can not occur. Moreover, because the silicon nitride retaining wall structures exist on the two sides of the bottom of the isolation groove 502, the problem of reliability reduction caused by transverse corrosion on the two sides of the isolation groove 502 in the process of etching the mask layer is effectively solved.
The manufacturing method of the MEMS device is a continuation of the SOI structure manufacturing method given above, i.e., on the basis of the SOI structure manufacturing method, the following steps are continuously performed, as shown in fig. 7 to 9:
(7) generally, the second silicon wafer 500 (i.e., a second silicon layer corresponding to the present invention) is used as a patterning layer of an MEMS device structure, before patterning, the upper surface of the second silicon wafer 500 needs to be ground and trimmed to a certain thickness, a silicon dioxide mask layer 600 is formed on the upper surface of the processed second silicon wafer 500, and the mask layer 600 is used for a mask for etching a groove on the second silicon wafer 500, for example, the mask is used for masking an etching comb-tooth electrode 501 and an isolation groove 502; in order to simplify the drawings, the mask layer 600 in fig. 7 and 8 is only labeled by one layer, and actually, the comb-teeth electrode 501 and the isolation trench 502 may be performed step by step, and the actual mask layer is not limited to the layer labeled in the drawings;
(8) patterning the mask layer 600 and respectively forming a comb tooth electrode 501 and an isolation groove 502 through a deep silicon etching process, wherein the etching depth of the comb tooth electrode 501 needs to ensure that the surface of the insulating layer at the bottom of the second silicon wafer 500 is not exposed; etching an isolation groove 502 above the gap of each group of two retaining wall structures, wherein the isolation groove 502 needs to be etched until the surface of the upper silicon dioxide layer 400 is exposed, namely the upper silicon dioxide layer 400 is used as a stop layer for deep silicon etching of the isolation groove 502;
(9) the barrier structures and the recessed portions of the silicon nitride layer 300 are used as reaction stop layers, and the mask layer is removed by a wet etching process, in the wet etching process, the upper silicon dioxide layer 400 exposed at the bottom of the isolation trench 502 is also etched, but the lower silicon dioxide layer 200 is not corroded due to the excellent corrosion resistance of the silicon nitride layer 300, and the occurrence of lateral corrosion is also prevented due to the presence of the barrier structures.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (18)
1. An SOI structure, comprising at least a first silicon layer, an insulating layer on the surface of the first silicon layer, and a second silicon layer bonded with the upper surface of the insulating layer, wherein the insulating layer comprises at least a lower silicon dioxide layer formed on the upper surface of the first silicon layer, and a silicon nitride layer formed on the upper surface of the lower silicon dioxide layer, characterized in that: protruding barricade structure and depressed part are formed to the upper surface of silicon nitride layer, and silicon dioxide layer is filled to the depressed part, goes up the upper surface on silicon dioxide layer and barricade structure's upper surface parallel and level.
2. An SOI structure as defined in claim 1 wherein: the thickness of the lower silicon dioxide layer is 1-2 microns.
3. An SOI structure as defined in claim 1 wherein: the upper surface of the lower silicon dioxide layer is a plane.
4. An SOI structure as defined in claim 3 wherein: the thickness of the thinnest part of the silicon nitride layer is 450-550 nanometers.
5. An SOI structure as defined in claim 1 wherein: and the upper surface of the lower silicon dioxide layer forms a convex part, and the silicon nitride layer deposited on the lower silicon dioxide layer forms a retaining wall structure and a concave part along with the shape.
6. An SOI structure as defined in claim 5 wherein: the deposition thickness of the silicon nitride layer is 450-550 nanometers.
7. An SOI structure as defined in claim 1 wherein: the thickness of the upper silicon dioxide layer is 1-1.5 micrometers.
8. An SOI structure as defined in claim 1 wherein: the resistivity of the first silicon layer and the second silicon layer is 0.1-10000 ohm-cm.
9. A method of fabricating an SOI structure comprising the steps of:
(1) providing a first silicon wafer, and forming a lower silicon dioxide layer on the upper surface of the first silicon wafer;
(2) forming a convex part on the upper surface of the lower silicon dioxide layer by etching;
(3) depositing a silicon nitride layer on the upper surface of the lower silicon dioxide layer, wherein the silicon nitride layer on the lower silicon dioxide layer forms a retaining wall structure and a concave part along with the shape;
(4) forming an upper silicon dioxide layer on the upper surface of the silicon nitride layer;
(5) carrying out planarization treatment on the surface of the upper silicon dioxide, wherein the planarized surface of the upper silicon dioxide is a plane and the upper silicon dioxide layer positioned on the upper surface of the retaining wall structure is removed;
(6) and preparing a second silicon wafer, and bonding and connecting one surface of the second silicon wafer with the surface of the planarized upper silicon dioxide layer.
10. A method for manufacturing an SOI structure, characterized in that: the method comprises the following steps:
(1) providing a first silicon wafer, and forming a lower silicon dioxide layer on the upper surface of the first silicon wafer;
(2) depositing a silicon nitride layer on the upper surface of the lower silicon dioxide layer;
(3) forming a raised retaining wall structure and a concave part on the upper surface of the silicon nitride layer by etching;
(4) forming an upper silicon dioxide layer on the upper surface of the silicon nitride layer;
(5) carrying out planarization treatment on the surface of the upper silicon dioxide, wherein the planarized surface of the upper silicon dioxide is a plane and the upper silicon dioxide layer positioned on the upper surface of the retaining wall structure is removed;
(6) and preparing a second silicon wafer, and bonding and connecting one surface of the second silicon wafer with the surface of the planarized upper silicon dioxide layer.
11. A MEMS device, characterized by: comprising an SOI structure as defined in any one of claims 1 to 8, a trench is etched in the second silicon layer of the SOI structure to expose the surface of the insulating layer at the bottom of the trench, and a retaining wall structure is provided at the side of the trench bottom.
12. A MEMS device according to claim 11, wherein: and grooving on the second silicon layer to form a comb tooth electrode and an isolation groove, wherein the etching depth of the comb tooth electrode does not expose the upper surface of the insulating layer, the upper surface of the insulating layer at the bottom of the isolation groove is exposed, and two sides of the bottom of the isolation groove are respectively provided with a retaining wall structure.
13. A MEMS device according to claim 12, wherein: the width of the isolation groove is less than or equal to the gap between two adjacent retaining wall structures.
14. A MEMS device according to claim 12, wherein: the bottom of the isolation groove is exposed out of the upper surface of the silicon nitride layer.
15. A method of manufacturing a MEMS device, comprising: method of manufacturing a SOI structure comprising the steps of claim 9 or 10, followed by the following steps after the execution of the method of manufacturing a SOI structure:
(7) forming a patterned mask layer on the upper surface of the second silicon wafer, wherein the mask layer is silicon dioxide;
(8) taking the mask layer as a mask and the silicon dioxide layer as an etching stop layer, and etching the groove on the second silicon wafer to enable the retaining wall structure to be positioned at the side part of the groove bottom;
(9) and removing the mask layer and the upper silicon dioxide layer exposed at the bottom of the groove by using the retaining wall structure and the recessed part of the silicon nitride layer as reaction stop layers through a wet etching process.
16. A method of manufacturing a MEMS device according to claim 15, wherein: the groove etched by the silicon dioxide layer as the etching stop layer is an isolation groove, and two sides of the bottom of the isolation groove are respectively provided with a retaining wall structure.
17. A method of manufacturing a MEMS device according to claim 16, wherein: the etching width of the isolation groove is less than or equal to the gap between two adjacent retaining wall structures.
18. A method of manufacturing a MEMS device according to claim 16, wherein: the etched groove on the second silicon wafer further comprises a comb tooth electrode, and the etching depth of the comb tooth electrode needs to ensure that the insulating layer at the bottom of the second silicon wafer is not exposed.
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