CN113471203B - Memory structure and manufacturing method thereof - Google Patents

Memory structure and manufacturing method thereof Download PDF

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Publication number
CN113471203B
CN113471203B CN202010244035.5A CN202010244035A CN113471203B CN 113471203 B CN113471203 B CN 113471203B CN 202010244035 A CN202010244035 A CN 202010244035A CN 113471203 B CN113471203 B CN 113471203B
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silicon layer
layer
floating gate
memory structure
grain size
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CN113471203A (en
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蔡文杰
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate

Abstract

The invention provides a memory structure and a manufacturing method thereof. The memory structure comprises a substrate, wherein the substrate comprises a plurality of active regions, and the active regions are separated by an isolation structure. The memory structure further comprises a plurality of stacked structures respectively located above the active regions, and each stacked structure comprises a tunneling dielectric layer located on the substrate and a floating gate located on the tunneling dielectric layer. The floating gate comprises a lower silicon layer and an upper silicon layer on the tunnel dielectric layer, wherein the lower silicon layer comprises a dopant of nitrogen, carbon, or a combination thereof.

Description

Memory structure and manufacturing method thereof
Technical Field
The present invention relates to a memory structure and a method for manufacturing the same, and more particularly to a nonvolatile memory structure and a method for manufacturing the same.
Background
In the nonvolatile memory, according to whether the data in the memory can be rewritten at any time when the computer is used, two kinds of products, namely a read-only memory (ROM) and a flash memory (flash memory), can be classified. Among them, flash memory is becoming the dominant technology of nonvolatile memory due to its low cost.
Generally, a flash memory includes two gates, a first gate being a floating gate storing data and a second gate being a control gate performing data input and output. The floating gate is located below the control gate and is in a "floating" state. By floating, it is meant surrounding and isolating the floating gate with an insulating material to prevent charge loss. The control gate is connected to the word line to control the device. One of the advantages of flash memory is that it can block-by-block erase data (block-by-block erase). Flash memory is widely used in enterprise servers, storage and networking technologies, as well as in a wide range of consumer electronics such as flash drives for flash drives, mobile phones, digital cameras, tablet computers, personal computer cards and embedded controllers for notebook computers, and the like.
Although existing methods of forming nonvolatile memories are adequate for their intended purpose, they are not yet fully satisfactory in all respects and thus the technology of nonvolatile memories is still a problem to be overcome.
Disclosure of Invention
The invention discloses a memory structure, which comprises a substrate, wherein the substrate comprises a plurality of active regions, and the active regions are separated by an isolation structure. The memory structure further comprises a plurality of stacked structures respectively located above the active regions, and each stacked structure comprises a tunneling dielectric layer located on the substrate and a floating gate located on the tunneling dielectric layer. The floating gate comprises a lower silicon layer and an upper silicon layer on the tunnel dielectric layer, wherein the lower silicon layer comprises a dopant of nitrogen, carbon, or a combination thereof.
The invention discloses a manufacturing method of a memory structure, which comprises the steps of providing a substrate comprising a plurality of active areas. The method also includes forming a plurality of stacked structures over each of the active regions, wherein each of the stacked structures includes a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The floating gate comprises a lower silicon layer and an upper silicon layer on the tunnel dielectric layer, wherein the lower silicon layer comprises a dopant of nitrogen, carbon, or a combination thereof. The method further includes forming a plurality of trenches between the active regions, and forming isolation structures in the trenches.
Drawings
Fig. 1A through 1O are schematic cross-sectional views corresponding to different intermediate stages in the fabrication of a memory structure according to an embodiment of the invention.
FIG. 2 is a schematic cross-sectional view of a memory structure according to another embodiment of the invention.
Symbol description
10 to a substrate;
11-tunneling dielectric material layer;
110-tunneling dielectric layer;
12. 13-silicon layer;
120-lower silicon layer;
130 to an upper silicon layer;
12M-implantation (implant) process;
14-an oxide layer;
140-patterning the oxide layer;
16. 17-mask layer;
160. 160', 170-patterning the mask layer;
18-patterning the photoresist;
19. 20-stacking structure;
210 to an opening;
130b to the bottom surface;
110a, 120a, 130a, 242a to top surface;
110c, 120c, 130 c-side walls;
220-grooves;
24. 240 to an isolation material layer;
242. 242-2 to isolation structures;
27-gate dielectric layer;
28 to a conductive layer;
HM-patterned mask stacking;
FG-floating gate;
w1 and W2 to the width;
A A an active region.
Detailed Description
The present invention will be described more fully with reference to the accompanying drawings in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar elements are denoted by the same or similar element numbers, and the following paragraphs will not be repeated. For simplicity of description, the drawings of embodiments are drawn with four stacked structures including floating gates on a substrate and control gates extending over the floating gates to illustrate a memory structure.
Fig. 1A through 1O are schematic cross-sectional views corresponding to different intermediate stages in the fabrication of a memory structure according to an embodiment of the invention. Referring to fig. 1A, a substrate 10 is provided, and the substrate 10 includes a source region and a drain region (not shown). The material of the substrate 10 may comprise silicon, gallium arsenide, gallium nitride, germanium silicide, silicon on insulator, other suitable materials, or combinations of the foregoing.
Next, a tunnel dielectric material layer 11 is formed on the substrate 10. The tunneling dielectric material layer 11 is, for example, silicon oxide or a high dielectric constant material (the dielectric constant is, for example, greater than 4). The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide. In one embodiment, the thickness of the tunnel dielectric material layer 11 may range from 3nm to 10nm.
Referring to fig. 1B, a silicon layer 12 is formed over the tunnel dielectric material layer 11. Silicon layer 12 is, for example, amorphous silicon and may be formed using a deposition process. In one embodiment, the thickness of the silicon layer 12 may range from 10nm to about 30nm, for example about 20nm.
Then, referring to fig. 1C, an implantation process 12M is performed to implant dopants within the silicon layer 12. For example, will contain nitrogen (N) 2 ) Dopants of carbon, or combinations of the foregoing are implanted into the silicon layer 12. In one embodiment, nitrogen is implanted into the silicon layer 12, for example, at a dose of 1×10 15 Atoms/cm 2 Up to 4X10 15 Atoms/cm 2 Within a range of (2). In one embodiment, the nitrogen injection energy is, for example, in the range of 2KJ to 5KJ, for example 3KJ. In addition, in other embodiments, an N-type dopant, such as phosphorus (P), may be implanted into the silicon layer 12, such that the floating gate is of an N-type conductivity type.
Then, referring to fig. 1D, a silicon layer 13 is formed over the silicon layer 12. Silicon layer 13 comprises polysilicon and may be formed using a deposition process. In one embodiment, the silicon layer 13 is an undoped polysilicon layer, for example. In one embodiment, the thickness of the silicon layer 13 may range from 40nm to 100nm, for example 60nm.
Then, referring to fig. 1E, an oxide layer 14, a mask layer 16, a mask layer 17, and a patterned photoresist 18 are sequentially formed on the silicon layer 13. The material of oxide layer 14 may include silicon oxide or silicon oxynitride, and may be formed by thermal oxidation, chemical vapor deposition, or a combination thereof. In one embodiment, the thickness of oxide layer 14 may range from 5nm to 15nm. The material of mask layer 16 may comprise silicon nitride or silicon oxynitride, the material of mask layer 17 may comprise silicon oxide, and mask layers 16 and 17 may be formed by chemical vapor deposition.
Referring to fig. 1F, the exposed portion of the mask layer 17 is removed according to the patterned photoresist 18 to form a patterned mask layer 170. An anisotropic etch, such as a dry etch, may be used to remove exposed portions of mask layer 17.
Referring to fig. 1G, the exposed mask layer 16 and oxide layer 14 are then removed using the patterned photoresist 18 and patterned mask layer 170 as a mask to form patterned mask layer 160 and patterned oxide layer 140. The removal may be performed using an anisotropic etch, such as a dry etch. To this end, a stack structure 19 is formed over the silicon layer 13. Further, the silicon layer 13 may be used as an etching stop layer when a part of the oxide layer 14 is removed. Although in this example, patterned masking layers 170 and 160 constitute a patterned mask stack (multi-layer structure) HM. In other examples, however, the patterned mask stack may be a single layer structure.
Referring to fig. 1H, after forming stack structure 19, in the same etching step, patterning of silicon layers 13 and 12 is continued to form upper silicon layer 130 and lower silicon layer 120 of floating gate FG, respectively, and openings 210 are formed between adjacent stack structures 19 and between adjacent floating gates FG. The opening 210 exposes a portion of the layer 11 of tunnel dielectric material. In one embodiment, silicon layers 13 and 12 are patterned in a dry etch such as reactive ion etching and/or a self-aligned double patterning process.
It should be noted that, since the silicon layer 12 contains nitrogen, carbon, phosphorus and other dopants, the etching rate of the silicon layer 12 is lower than that of the silicon layer 13, so that the width W1 of the lower silicon layer 120 formed after etching is greater than the width W2 of the upper silicon layer 130.
In one embodiment, the width W1 of the lower silicon layer 120 has a ratio (W1/W2) relative to the width W2 of the upper silicon layer 130, which is in the range of greater than 1 to 1.5, such as about 1.1. The amount of dopant comprising nitrogen, carbon, or a combination thereof in the silicon layer 12 may be adjusted to achieve a desired ratio according to practical application requirements. For example, when the content of the dopant is increased, the etching rate of the silicon layer 12 is slowed, and the width W1 of the lower silicon layer 120 is formed to be larger, so that the ratio of the width W1/the width W2 may be changed.
Next, referring to fig. 1I, the patterned photoresist 18 is removedThe exposed tunnel dielectric material layer 11 and the underlying substrate 10 are etched using the patterned mask stack HM, the patterned oxide layer 140 and the floating gate FG as a mask, and a trench 220 is formed in the substrate 10. As shown in fig. 1I, the region between adjacent trenches 220 may be an active area (active area) a of the memory structure A . Furthermore, the tunnel dielectric material layer 11 may be etched to form a dielectric pattern as a tunnel oxide layer 110 of the memory structure. In one embodiment, the sidewall 120c of the lower silicon layer 120 is substantially coplanar with the sidewall 110c of the tunnel dielectric layer 110. The floating gate FG and the tunnel oxide 110 above the substrate 10 form a stacked structure 20.
It should be noted that since the lower silicon layer 120 contains dopants, its etch rate is less than that of the underlying substrate 10. Therefore, the width W1 of the lower silicon layer 120 corresponds to the active region A A Width W of (2) A Substantially equal and smaller than the width W2 of the upper silicon layer 130.
Referring to fig. 1J, a spacer material layer 24 is deposited over the patterned mask stack HM, the patterned oxide layer 140 and the stacked structure 20, and the spacer material layer 24 fills the trench 220 and the opening 210. In one embodiment, the isolation material layer 24 may be formed to both sides of the patterned mask stack HM or beyond the top surface of the patterned mask stack HM (as shown in fig. 1J). The material of the isolation material layer 24 includes an insulating material, such as silicon oxide, silicon nitride, or a combination thereof, and the isolation material layer 24 may be formed by chemical vapor deposition.
Referring to fig. 1K, portions of the isolation material layer 24 and the patterned mask layer 170 are then removed. The remaining isolation material layer 240 is formed, for example, to both sides of the patterned mask layer 160, and the top surface of the isolation material layer 240 is substantially coplanar with the top surface of the patterned mask layer 160. In one embodiment, the removing step may be performed by a method such as Chemical Mechanical Polishing (CMP).
Thereafter, referring to fig. 1L, a first etching step is performed to remove a portion of the isolation material layer 240, so as to recess the isolation material layer 240. The remaining isolation material layer forms isolation structures 242 in openings 210 and trenches 220. In addition, when the first etching step is performed, a portion of the patterned mask layer 160 is also removed. The method of removing portions of the isolation material layer 240 includes an anisotropic etch, such as a dry etch. In one embodiment, the top surface 242a of the controllable isolation structure 242 is lower than the top surface 130a of the upper silicon layer 130, so that the Gate Coupling Ratio (GCR) of the floating Gate FG to a conductive layer subsequently formed as a control Gate can be improved. In addition, the top surface 242a of the controllable isolation structure 242 is higher than the top surface 110a of the tunnel dielectric layer 110, so that the tunnel dielectric layer 110 is prevented from being damaged during the formation of the isolation structure 242.
Thereafter, referring to fig. 1M, the patterned mask layer 160' remained after the first etching step is performed is removed.
Referring to fig. 1N, a second etching step is performed to further etch the isolation structure 242 and remove the patterned oxide layer 140, thereby forming an isolation structure 242-2. The isolation structure 242 may be etched and the patterned oxide layer 140 may be removed using a dry etch process.
It should be noted that by controlling the deposition thickness of the silicon layer 12, the lower silicon layer 120 of the different floating gates FG can have a uniform height, thereby controlling the uniformity (uniformity) of the depth of the recessed isolation material layer 240 between the floating gates FG as shown in fig. 1L, and thus the active area a A The top surface heights of the isolation structures (e.g., isolation structure 242 or isolation structure 242-2) therebetween are uniform.
Referring to fig. 1O, an inter-gate dielectric layer 27 is then conformally formed over the floating gate FG, and a conductive layer 28 is deposited over the inter-gate dielectric layer 27 to serve as a control gate for the memory structure. In one embodiment, the inter-gate dielectric layer 27 may have a single-layer structure or a multi-layer structure, and the material of the inter-gate dielectric layer 27 may include silicon oxide, silicon nitride, or a combination thereof. For example, the inter-gate dielectric layer 27 may be a silicon oxide/silicon nitride/silicon oxide structure (ONO structure), or a NONON structure. Furthermore, the conductive layer 28 may be a single-layer or multi-layer structure. The material of conductive layer 28 comprises polysilicon, metal silicide, or other conductor material. For example, the metal may include titanium, tantalum, tungsten, aluminum, or zirconium. The metal silicide may include nickel silicide, titanium silicide, or tungsten silicide. Thus, the fabrication of the memory structure of the present embodiment is completed.
It should be noted that in one embodiment of the nitrogen implantation into the silicon layer 12 (FIG. 1C), the bottom silicon layer 120 of the finally fabricated floating gate FG includes a dopant concentration of dopant nitrogen, for example, at 1×10 20 /cm 3 Up to 1X10 22 /cm 3 Is in the range of (2).
In one embodiment, the silicon layer 12, which is originally formed of an amorphous silicon material, is transformed into polysilicon after a thermal process during the fabrication of the memory structure. Thus, the lower silicon layer 120 and the upper silicon layer 130 of the floating gate FG of the memory structure shown in fig. 1O each comprise polysilicon. The inclusion of nitrogen, carbon, or a combination thereof in the silicon layer 12 also results in a later formed polysilicon having a smaller grain size than the polysilicon of the upper silicon layer 130 that does not include the above-described dopant.
Referring to fig. 2, a cross-sectional view of a memory structure according to another embodiment of the invention is shown. As shown, the lower silicon layer 120 of the floating gate FG has a first average grain size and the upper silicon layer 130 has a second average grain size, the first average grain size being smaller than the second average grain size. In one embodiment, the first average grain size is, for example, 5nm to 20nm, and the second average grain size is, for example, 50nm to 80nm. It is noted that the smaller the grain size, the more paths the electrons can flow through, and thus the more stable the current generated from the active region A during the writing operation of the memory structure A The channel of (a) is injected into the floating gate FG through the tunnel dielectric layer 110 and may spread the current path through the tunnel dielectric layer 110. Therefore, after a plurality of writing operations, the damage of the tunneling dielectric layer 110 can be reduced, so that the data stored in the floating gate is less likely to be lost (data loss).
According to the embodiment, the invention can stably control the morphology (topography) of the manufactured floating gate FG. In detail, by forming a silicon layer 12The additional implantation of nitrogen, carbon, phosphorus, etc. allows the bottom silicon layer 120 of the floating gate FG to have a larger width than the top silicon layer 130 and allows the active region A to be located under the floating gate FG A Is substantially equal to the width of the lower silicon layer 120. For adjacent floating gates FG, the distance between adjacent upper silicon layers 130 is greater than the distance between adjacent lower silicon layers 120, thus reducing the coupling (FG-FG coupling) between upper silicon layers 130 of adjacent floating gates FG. At the same time, since the floating gate FG has a lower silicon layer 120 wider than the upper silicon layer 130 and an active region A A Also increase the active area A A More operating current can flow through the channel to be injected into the floating gate FG, thereby reducing the operating voltage. Furthermore, since the lower silicon layer 120 of the present invention has smaller average grain size and more grain boundaries, the more stable the current can be injected into the floating gate FG, and the more stable the electrical performance.
In summary, the present invention provides a memory structure and a method for fabricating the same, in which a dopant including nitrogen, carbon, or a combination thereof is implanted into a lower silicon layer of a floating gate on a tunneling dielectric layer, and the lower silicon layer forms a lower portion of the floating gate in a subsequent process. The method for manufacturing the memory structure can stably control the morphology (morphology) of the manufactured floating gate FG, including controlling the width of the lower silicon layer, the width of the active region and the height of the isolation structure between the floating gates. The memory structure manufactured according to the invention has at least many benefits of speeding up writing, reducing writing voltage, having good data storage capability and stable electrical performance, and further improving the yield and reliability of the final product.
Although the present invention has been described with respect to several preferred embodiments, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.

Claims (10)

1. A memory structure, comprising:
the substrate comprises a plurality of active regions, and the adjacent active regions are separated by an isolation structure;
a plurality of stacked structures respectively located above the active region, wherein each stacked structure comprises a tunneling dielectric layer located on the substrate and a floating gate located on the tunneling dielectric layer, and the floating gate comprises:
a lower silicon layer on the tunneling dielectric layer, wherein the lower silicon layer comprises a dopant of a combination of both nitrogen and carbon; and
and an upper silicon layer on the lower silicon layer, the upper silicon layer being an undoped polysilicon layer, wherein the upper silicon layer and the lower silicon layer are formed in the same etching step such that the upper silicon layer exposes a portion of the upper surface of the lower silicon layer.
2. The memory structure of claim 1, wherein the lower silicon layer comprises a dopant concentration of 1x10 dopant nitrogen 20 /cm 3 Up to 1X10 22 /cm 3 Between the ranges.
3. The memory structure of claim 1 wherein the lower silicon layer of the floating gate has a first average grain size and the upper silicon layer has a second average grain size, the first average grain size being smaller than the second average grain size.
4. A method of manufacturing a memory structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of active areas;
forming a plurality of stacked structures respectively above the active region, wherein each stacked structure comprises a tunneling dielectric layer on the substrate and a floating gate on the tunneling dielectric layer, and the floating gate comprises:
a lower silicon layer on the tunneling dielectric layer, wherein the lower silicon layer comprises a dopant of a combination of both nitrogen and carbon; and
an upper silicon layer on the lower silicon layer, the upper silicon layer being an undoped polysilicon layer, wherein the upper silicon layer and the lower silicon layer are formed in the same etching step such that the upper silicon layer exposes a portion of the upper surface of the lower silicon layer;
forming a plurality of grooves which are respectively positioned between the active areas; and
and forming an isolation structure in the groove.
5. The method of claim 4, wherein the lower silicon layer comprises a dopant concentration of 1x10 dopant nitrogen 20 /cm 3 Up to 1X10 22 /cm 3 Between the ranges.
6. The method of manufacturing a memory structure of claim 4, wherein the lower silicon layer of the floating gate has a first average grain size and the upper silicon layer has a second average grain size, the first average grain size being smaller than the second average grain size.
7. The method of manufacturing a memory structure of claim 4, wherein forming the floating gate comprises:
depositing a first silicon layer on the tunneling dielectric layer;
implanting dopants comprising nitrogen, carbon, or a combination thereof into the first silicon layer; and
a second silicon layer is deposited over the first silicon layer.
8. The method of claim 7, wherein nitrogen is implanted into the first silicon layer at a dose of about 1x10 15 Atoms/cm 2 Up to about 4x10 15 Atoms/cm 2 Within a range of (2).
9. The method of claim 7, wherein after depositing the second silicon layer, the second silicon layer and the first silicon layer are patterned in a same etching step to form the upper silicon layer and the lower silicon layer, respectively.
10. The method of claim 9, wherein the first silicon layer has a lower etch rate than the second silicon layer.
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