CN113471084A - Bonding packaging body and preparation method thereof - Google Patents
Bonding packaging body and preparation method thereof Download PDFInfo
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- CN113471084A CN113471084A CN202111029065.5A CN202111029065A CN113471084A CN 113471084 A CN113471084 A CN 113471084A CN 202111029065 A CN202111029065 A CN 202111029065A CN 113471084 A CN113471084 A CN 113471084A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 127
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052763 palladium Inorganic materials 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000004033 plastic Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 10
- 238000007772 electroless plating Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a bonding packaging body and a preparation method thereof.A first bonding part, a second bonding part, a third bonding part and a fourth bonding part are respectively formed on the periphery of a first semiconductor tube core, a first groove is formed in the first semiconductor tube core, a silicon through hole is exposed out of the first groove, a plurality of convex columns are respectively formed on the corresponding bonding parts, then a fifth bonding part, a sixth bonding part, a seventh bonding part and an eighth bonding part are respectively formed on the periphery of a second semiconductor tube core, grooves are respectively formed on the corresponding bonding parts, then the second semiconductor tube core is bonded to the first semiconductor tube core, and a plurality of convex columns are respectively embedded into the corresponding grooves. The structure can improve the bonding strength of the first and second semiconductor dies, effectively prevent the first and second semiconductor dies from peeling and collapsing, provide mounting space for the electrical connection of the through silicon via, and further improve the stability of the electrical connection.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a bonding packaging body and a preparation method thereof.
Background
In the conventional semiconductor package structure, when a through-silicon via structure is formed in a semiconductor die, a chemical mechanical mask process is used to expose the top surface of the through-silicon via, and then a conductive pad of another semiconductor die is bonded to the through-silicon via structure of the semiconductor die by solder to complete the bonding of the semiconductor die. However, in the above bonding process, the bonding body of the semiconductor die has a gap, which leads to the bonding body being easily peeled and collapsed, and thus the bonding body is not functional. How to further improve the structure of the bond to prevent the bond from peel-off collapse has attracted a great deal of attention by those skilled in the art.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies of the prior art and to provide a bonded package and a method for manufacturing the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a preparation method of a bonding packaging body comprises the following steps:
step (1): a first semiconductor die is provided having through-silicon vias therein.
Step (2): the first semiconductor die is arranged on a first substrate, and then the first semiconductor die is etched to form a first bonding part, a second bonding part, a third bonding part and a fourth bonding part on the periphery of the first semiconductor die, wherein the first bonding part, the second bonding part, the third bonding part and the fourth bonding part respectively protrude out of the first side surface, the second side surface, the third side surface and the fourth side surface of the first semiconductor die.
And (3): and then etching the upper surface of the first semiconductor die to form a first groove in the first semiconductor die, wherein the first groove exposes the through silicon via, a plurality of first convex columns are formed on the first bonding part, a plurality of second convex columns are respectively formed on the second bonding part, a plurality of third convex columns are formed on the third bonding part, and a plurality of fourth convex columns are respectively formed on the fourth bonding part.
And (4): conductive bumps are then formed on the through silicon vias exposed in the first recess.
And (5): providing a second semiconductor die, wherein the upper surface of the second semiconductor die is provided with a conductive pad, the second semiconductor die is arranged on a second substrate, and then the second semiconductor die is etched to form a fifth bonding part, a sixth bonding part, a seventh bonding part and an eighth bonding part on the periphery of the second semiconductor die, wherein the fifth bonding part, the sixth bonding part, the seventh bonding part and the eighth bonding part respectively protrude out of the first side surface, the second side surface, the third side surface and the fourth side surface of the second semiconductor die.
And (6): and etching the upper surface of the second semiconductor die to form first, second, third and fourth grooves on the fifth, sixth, seventh and eighth bonding parts, respectively.
And (7): an annular conductive block is then formed on the conductive pad of the second semiconductor die.
And (8): a second semiconductor die is then bonded to the first semiconductor die such that a plurality of the first posts are embedded in the first trenches, a plurality of the second posts are embedded in the second trenches, a plurality of the third posts are embedded in the third trenches, a plurality of the fourth posts are embedded in the fourth trenches, and the conductive bumps are embedded in the annular conductive bumps, thereby electrically connecting the conductive pads to the through silicon vias.
And (9): then removing the second substrate, then forming a plastic packaging layer to wrap the first and second semiconductor dies, and then removing the first substrate.
Step (10): and then forming a rewiring layer on the plastic packaging layer, and forming a conductive solder ball on the rewiring layer.
In a more preferable technical solution, in the step (2), before the first semiconductor die is disposed on the first substrate, an adhesive layer is disposed on the first substrate, and then the first semiconductor die is bonded by using the adhesive layer, and the first semiconductor die is etched by a wet etching process or a dry etching process.
In a more preferred embodiment, in the step (3), a plurality of the first, second, third, and fourth bosses are formed by removing a part of the first, second, third, and fourth bonding portions, respectively.
In a more preferred embodiment, in the step (4), the conductive bump is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel, and gold, and is formed by electroplating, electroless plating, chemical vapor deposition, or physical vapor deposition.
In a more preferred embodiment, in the step (5), the fifth, sixth, seventh and eighth bonding portions correspond to the first, second, third and fourth bonding portions, respectively, one to one.
In a more preferred embodiment, in step (7), the annular conductive block is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel, and gold, and is formed by electroplating, electroless plating, chemical vapor deposition, or physical vapor deposition.
In a more preferable technical solution, in the step (8), an adhesion material is firstly disposed in the first, second, third, and fourth grooves, and then the adhesion material is used to bond the first, second, third, and fourth pillars, respectively, a conductive solder is disposed in the annular conductive block, and then the conductive bump is bonded by the conductive solder.
In a more preferable technical scheme, the invention further provides a bonding packaging body which is prepared and formed by adopting the preparation method.
Compared with the prior art, the bonding packaging body and the preparation method thereof have the following beneficial effects:
the first bonding part, the second bonding part, the third bonding part and the fourth bonding part are respectively formed on the periphery of the first semiconductor die, a first groove is formed in the first semiconductor die, the first groove exposes out of the silicon through hole, a plurality of first convex columns are formed on the first bonding part, a plurality of second convex columns are respectively formed on the second bonding part, a plurality of third convex columns are formed on the third bonding part, a plurality of fourth convex columns are respectively formed on the fourth bonding part, and then a conductive convex block is formed on the silicon through hole exposed in the first groove. And forming fifth, sixth, seventh and eighth bonding parts around the second semiconductor die, respectively, forming first, second, third and fourth grooves on the fifth, sixth, seventh and eighth bonding parts, respectively, forming an annular conductive block on the conductive pad of the second semiconductor die, and then bonding the second semiconductor die to the first semiconductor die such that the plurality of first pillars are embedded in the first grooves, the plurality of second pillars are embedded in the second grooves, the plurality of third pillars are embedded in the third grooves, the plurality of fourth pillars are embedded in the fourth grooves, and the conductive bumps are embedded in the annular conductive block, thereby electrically connecting the conductive pad to the through silicon via. The arrangement of the structure provides a bonding space for the electric connection of the silicon through hole and another semiconductor die through the arrangement of the first groove, and the first, second, third and fourth bonding parts are formed on the peripheral edge of the first semiconductor die and the fifth, sixth, seventh and eighth bonding parts are formed on the peripheral edge of the second semiconductor die, so that the bonding strength of the first and second semiconductor dies can be improved, the peeling and collapse of the first and second semiconductor dies can be effectively prevented, a mounting space is provided for the electric connection of the silicon through hole, and the stability of the electric connection can be improved.
Drawings
FIG. 1 is a schematic structural diagram of step (1) in the process of manufacturing a bonded package according to the present invention;
FIG. 2 is a schematic structural diagram of step (2) in the process of manufacturing the bonded package according to the present invention;
FIG. 3 is a schematic structural diagram of step (3) in the process of manufacturing the bonded package according to the present invention;
FIG. 4 is a schematic structural diagram of step (4) in the process of manufacturing the bonded package according to the present invention;
FIG. 5 is a schematic structural diagram of step (5) in the process of manufacturing the bonded package according to the present invention;
FIG. 6 is a schematic structural diagram of step (6) in the process of manufacturing the bonded package according to the present invention;
FIG. 7 is a schematic structural diagram of step (7) in the process of manufacturing a bonded package according to the present invention;
FIG. 8 is a schematic structural diagram of step (8) in the process of manufacturing a bonded package according to the present invention;
FIG. 9 is a schematic structural diagram of step (9) in the process of manufacturing a bonded package according to the present invention;
fig. 10 is a schematic structural diagram of step (10) in the process of manufacturing the bonded package according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a preparation method of a bonding packaging body, which comprises the following steps:
step (1): a first semiconductor die is provided having through-silicon vias therein.
Step (2): the first semiconductor die is arranged on a first substrate, and then the first semiconductor die is etched to form a first bonding part, a second bonding part, a third bonding part and a fourth bonding part on the periphery of the first semiconductor die, wherein the first bonding part, the second bonding part, the third bonding part and the fourth bonding part respectively protrude out of the first side surface, the second side surface, the third side surface and the fourth side surface of the first semiconductor die.
And (3): and then etching the upper surface of the first semiconductor die to form a first groove in the first semiconductor die, wherein the first groove exposes the through silicon via, a plurality of first convex columns are formed on the first bonding part, a plurality of second convex columns are respectively formed on the second bonding part, a plurality of third convex columns are formed on the third bonding part, and a plurality of fourth convex columns are respectively formed on the fourth bonding part.
And (4): conductive bumps are then formed on the through silicon vias exposed in the first recess.
And (5): providing a second semiconductor die, wherein the upper surface of the second semiconductor die is provided with a conductive pad, the second semiconductor die is arranged on a second substrate, and then the second semiconductor die is etched to form a fifth bonding part, a sixth bonding part, a seventh bonding part and an eighth bonding part on the periphery of the second semiconductor die, wherein the fifth bonding part, the sixth bonding part, the seventh bonding part and the eighth bonding part respectively protrude out of the first side surface, the second side surface, the third side surface and the fourth side surface of the second semiconductor die.
And (6): and etching the upper surface of the second semiconductor die to form first, second, third and fourth grooves on the fifth, sixth, seventh and eighth bonding parts, respectively.
And (7): an annular conductive block is then formed on the conductive pad of the second semiconductor die.
And (8): a second semiconductor die is then bonded to the first semiconductor die such that a plurality of the first posts are embedded in the first trenches, a plurality of the second posts are embedded in the second trenches, a plurality of the third posts are embedded in the third trenches, a plurality of the fourth posts are embedded in the fourth trenches, and the conductive bumps are embedded in the annular conductive bumps, thereby electrically connecting the conductive pads to the through silicon vias.
And (9): then removing the second substrate, then forming a plastic packaging layer to wrap the first and second semiconductor dies, and then removing the first substrate.
Step (10): and then forming a rewiring layer on the plastic packaging layer, and forming a conductive solder ball on the rewiring layer.
In the step (2), before the first semiconductor die is disposed on the first substrate, an adhesive layer is disposed on the first substrate, and then the first semiconductor die is bonded by the adhesive layer, and the first semiconductor die is etched by a wet etching process or a dry etching process.
Wherein, in the step (3), a plurality of the first, second, third and fourth convex columns are formed by removing a part of the first, second, third and fourth bonding parts, respectively.
In the step (4), the conductive bump is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel, and gold, and is formed by electroplating, chemical plating, chemical vapor deposition, or physical vapor deposition.
In the step (5), the fifth, sixth, seventh and eighth bonding portions correspond to the first, second, third and fourth bonding portions one to one, respectively.
In the step (7), the annular conductive block is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel, and gold, and is formed by electroplating, chemical plating, chemical vapor deposition, or physical vapor deposition.
In the step (8), an adhesion material is firstly arranged in the first, second, third and fourth grooves, and then the adhesion material is used for respectively bonding the first, second, third and fourth convex columns, a conductive solder is arranged in the annular conductive block, and then the conductive bump is bonded by the conductive solder.
The invention also provides a bonding packaging body which is prepared by the preparation method.
As shown in fig. 1 to 10, the present embodiment provides a method for manufacturing a bonded package, including the following steps:
as shown in fig. 1, in step (1), a first semiconductor die 100 is provided, the first semiconductor die 100 having a through-silicon via 101 therein.
As shown in fig. 2, in step (2): the first semiconductor die 100 is disposed on a first substrate 102, and then the first semiconductor die 100 is etched to form a first bonding portion 103, a second bonding portion 104, a third bonding portion 105, and a fourth bonding portion 106 around the first semiconductor die 100, wherein the first, second, third, and fourth bonding portions 103 and 106 respectively protrude from first, second, third, and fourth side surfaces of the first semiconductor die 100.
In a specific embodiment, in the step (2), before the first semiconductor die 100 is disposed on the first substrate 102, an adhesive layer (not shown) is disposed on the first substrate 102, and then the first semiconductor die 100 is bonded by using the adhesive layer, and the first semiconductor die 100 is etched by a wet etching process or a dry etching process.
In a specific embodiment, the first, second, third, and fourth bonding portions 103-.
As shown in fig. 3, in step (3): then, an etching process is performed on the upper surface of the first semiconductor die 100 to form a first groove 107 in the first semiconductor die 100, the first groove 107 exposes the through silicon via 101, a plurality of first pillars 1031 are formed on the first bonding portion 103, a plurality of second pillars 1041 are respectively formed on the second bonding portion 104, a plurality of third pillars 1051 are formed on the third bonding portion 105, and a plurality of fourth pillars 1061 are respectively formed on the fourth bonding portion 106.
In a specific embodiment, in the step (3), a plurality of the first, second, third and fourth protruding columns 1031 and 1061 are formed by removing a portion of the first, second, third and fourth bonding portions 103 and 106, respectively.
In a specific embodiment, the first groove 107 and the first, second, third, and fourth convex columns 1031-.
As shown in fig. 4, in step (4): a conductive bump 108 is then formed on the through-silicon via 101 exposed in the first recess 107.
In a specific embodiment, in the step (4), the material of the conductive bump 108 is one or more of copper, aluminum, titanium, palladium, silver, nickel, and gold, and the conductive bump 108 is formed by electroplating, electroless plating, chemical vapor deposition, or physical vapor deposition.
In a more specific embodiment, the conductive copper pillars are formed by an electro-coppering process.
As shown in fig. 5, in step (5): providing a second semiconductor die 200, wherein the upper surface of the second semiconductor die 200 has a conductive pad 201, disposing the second semiconductor die 200 on a second substrate 202, and then performing an etching process on the second semiconductor die 200 to form a fifth bonding portion 203, a sixth bonding portion 204, a seventh bonding portion 205, and an eighth bonding portion 206 around the second semiconductor die 200, wherein the fifth, sixth, seventh, and eighth bonding portions 203 and 206 respectively protrude from the first, second, third, and fourth side surfaces of the second semiconductor die 200.
In a specific embodiment, in the step (5), the fifth, sixth, seventh, and eighth bonding portions 203 and 206 are respectively in one-to-one correspondence with the first, second, third, and fourth bonding portions 103 and 106.
In a specific embodiment, in the step (5), before the second semiconductor die 200 is disposed on the second substrate 202, an adhesive layer (not shown) is disposed on the second substrate 202, and then the second semiconductor die 200 is bonded by using the adhesive layer, and the second semiconductor die 200 is etched by a wet etching process or a dry etching process.
In a specific embodiment, the second semiconductor die 200 is wet etched using a mask to simultaneously form the first, second, third, and fourth bonding portions 203 and 206.
As shown in fig. 6, in step (6): next, the upper surface of the second semiconductor die 200 is etched to form a first trench 2031, a second trench 2041, a third trench 2051 and a fourth trench 2061 in the fifth, sixth, seventh and eighth bonding portions 203-206, respectively.
In a specific embodiment, the first trench 2031, the second trench 2041, the third trench 2051, and the fourth trench 2061 are formed by wet etching or dry etching, respectively.
As shown in fig. 7, in step (7): an annular conductive block 207 is then formed on the conductive pad 201 of the second semiconductor die 200.
In a specific embodiment, in the step (7), the annular conductive block 207 is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel, and gold, and the annular conductive block 207 is formed by electroplating, electroless plating, chemical vapor deposition, or physical vapor deposition.
In a more specific embodiment, the annular conductive copper block is formed by an electrolytic copper plating process.
As shown in fig. 8, in step (8): a second semiconductor die 200 is then bonded to the first semiconductor die 100 such that a plurality of the first posts 1031 are embedded in the first trenches 2031, a plurality of the second posts 1041 are embedded in the second trenches 2041, a plurality of the third posts 1051 are embedded in the third trenches 2051, a plurality of the fourth posts 1061 are embedded in the fourth trenches 2061, and such that the conductive bumps 108 are embedded in the annular conductive bumps 207, thereby electrically connecting the conductive pads 201 to the through silicon vias 101.
In a specific embodiment, in the step (8), an adhesion material is firstly disposed in the first, second, third, and fourth grooves 2031 and 2061, and then the adhesion material is used to bond the first, second, third, and fourth pillars 1031 and 1061, respectively, a conductive solder is disposed in the annular conductive block 207, and then the conductive bump 108 is bonded by the conductive solder.
As shown in fig. 9, in step (9): the second substrate 202 is then removed, followed by forming a molding layer 300 to encapsulate the first and second semiconductor dies 100 and 200, followed by removing the first substrate 102.
In a specific embodiment, the molding layer 300 may be an epoxy resin.
As shown in fig. 10, in step (10): then, a redistribution layer 400 is formed on the molding compound layer 300, and a conductive solder ball 500 is formed on the redistribution layer 400.
In a specific embodiment, the first semiconductor die 100 directly contacts the redistribution layer 400.
As shown in fig. 10, the present invention further provides a bonded package prepared by the above preparation method.
Compared with the prior art, the bonding packaging body and the preparation method thereof have the following beneficial effects:
the first bonding part, the second bonding part, the third bonding part and the fourth bonding part are respectively formed on the periphery of the first semiconductor die, a first groove is formed in the first semiconductor die, the first groove exposes out of the silicon through hole, a plurality of first convex columns are formed on the first bonding part, a plurality of second convex columns are respectively formed on the second bonding part, a plurality of third convex columns are formed on the third bonding part, a plurality of fourth convex columns are respectively formed on the fourth bonding part, and then a conductive convex block is formed on the silicon through hole exposed in the first groove. And forming fifth, sixth, seventh and eighth bonding parts around the second semiconductor die, respectively, forming first, second, third and fourth grooves on the fifth, sixth, seventh and eighth bonding parts, respectively, forming an annular conductive block on the conductive pad of the second semiconductor die, and then bonding the second semiconductor die to the first semiconductor die such that the plurality of first pillars are embedded in the first grooves, the plurality of second pillars are embedded in the second grooves, the plurality of third pillars are embedded in the third grooves, the plurality of fourth pillars are embedded in the fourth grooves, and the conductive bumps are embedded in the annular conductive block, thereby electrically connecting the conductive pad to the through silicon via. The arrangement of the structure provides a bonding space for the electric connection of the silicon through hole and another semiconductor die through the arrangement of the first groove, and the first, second, third and fourth bonding parts are formed on the peripheral edge of the first semiconductor die and the fifth, sixth, seventh and eighth bonding parts are formed on the peripheral edge of the second semiconductor die, so that the bonding strength of the first and second semiconductor dies can be improved, the peeling and collapse of the first and second semiconductor dies can be effectively prevented, a mounting space is provided for the electric connection of the silicon through hole, and the stability of the electric connection can be improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for manufacturing a bonded package is characterized in that: the method comprises the following steps:
step (1): providing a first semiconductor die having through-silicon vias therein;
step (2): arranging the first semiconductor die on a first substrate, and then etching the first semiconductor die to form first, second, third and fourth bonding parts respectively on the periphery of the first semiconductor die, wherein the first, second, third and fourth bonding parts respectively protrude out of the first, second, third and fourth side surfaces of the first semiconductor die;
and (3): etching the upper surface of the first semiconductor die to form a first groove in the first semiconductor die, wherein the first groove exposes the through silicon via, a plurality of first convex columns are formed on the first bonding part, a plurality of second convex columns are respectively formed on the second bonding part, a plurality of third convex columns are formed on the third bonding part, and a plurality of fourth convex columns are respectively formed on the fourth bonding part;
and (4): forming a conductive bump on the exposed silicon through hole in the first groove;
and (5): providing a second semiconductor die, wherein the upper surface of the second semiconductor die is provided with a conductive pad, the second semiconductor die is arranged on a second substrate, and then the second semiconductor die is etched to form a fifth bonding part, a sixth bonding part, a seventh bonding part and an eighth bonding part on the periphery of the second semiconductor die, wherein the fifth bonding part, the sixth bonding part, the seventh bonding part and the eighth bonding part respectively protrude out of the first side surface, the second side surface, the third side surface and the fourth side surface of the second semiconductor die;
and (6): etching the upper surface of the second semiconductor die to form a first groove, a second groove, a third groove and a fourth groove on the fifth bonding part, the sixth bonding part, the seventh bonding part and the eighth bonding part respectively;
and (7): then forming an annular conductive block on the conductive pad of the second semiconductor die;
and (8): then bonding a second semiconductor die to the first semiconductor die such that a plurality of the first posts are embedded in the first trenches, a plurality of the second posts are embedded in the second trenches, a plurality of the third posts are embedded in the third trenches, a plurality of the fourth posts are embedded in the fourth trenches, and the conductive bumps are embedded in the annular conductive bumps, thereby electrically connecting the conductive pads to the through silicon vias;
and (9): removing the second substrate, forming a plastic packaging layer to wrap the first semiconductor tube core and the second semiconductor tube core, and removing the first substrate;
step (10): and then forming a rewiring layer on the plastic packaging layer, and forming a conductive solder ball on the rewiring layer.
2. The method of manufacturing a bonded package according to claim 1, wherein: in the step (2), before the first semiconductor die is disposed on the first substrate, an adhesive layer is disposed on the first substrate, and then the first semiconductor die is bonded by the adhesive layer, and the first semiconductor die is etched by a wet etching process or a dry etching process.
3. The method of manufacturing a bonded package according to claim 1, wherein: in the step (3), a plurality of first, second, third and fourth protruding columns are formed by removing a part of the first, second, third and fourth bonding parts.
4. The method of manufacturing a bonded package according to claim 1, wherein: in the step (4), the conductive bump is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel, and gold, and is formed by electroplating, chemical plating, chemical vapor deposition, or physical vapor deposition.
5. The method of manufacturing a bonded package according to claim 1, wherein: in the step (5), the fifth, sixth, seventh and eighth bonding portions correspond to the first, second, third and fourth bonding portions, respectively.
6. The method of manufacturing a bonded package according to claim 1, wherein: in the step (7), the annular conductive block is made of one or a combination of copper, aluminum, titanium, palladium, silver, nickel and gold, and is formed by electroplating, chemical plating, chemical vapor deposition or physical vapor deposition.
7. The method of manufacturing a bonded package according to claim 1, wherein: in the step (8), an adhesion material is firstly arranged in the first, second, third and fourth grooves, and then the adhesion material is used for respectively bonding the first, second, third and fourth convex columns, a conductive solder is arranged in the annular conductive block, and then the conductive bump is bonded by the conductive solder.
8. A bonded package formed by the method according to any one of claims 1 to 7.
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| US20030134450A1 (en) * | 2002-01-09 | 2003-07-17 | Lee Teck Kheng | Elimination of RDL using tape base flip chip on flex for die stacking |
| CN111370336A (en) * | 2020-03-12 | 2020-07-03 | 浙江大学 | Packaging method for placing groove chip |
| CN111554646A (en) * | 2020-05-19 | 2020-08-18 | 上海先方半导体有限公司 | Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method |
| CN113257685A (en) * | 2021-07-14 | 2021-08-13 | 江苏华昶熠电子科技有限公司 | Semiconductor packaging device and manufacturing method thereof |
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Patent Citations (4)
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|---|---|---|---|---|
| US20030134450A1 (en) * | 2002-01-09 | 2003-07-17 | Lee Teck Kheng | Elimination of RDL using tape base flip chip on flex for die stacking |
| CN111370336A (en) * | 2020-03-12 | 2020-07-03 | 浙江大学 | Packaging method for placing groove chip |
| CN111554646A (en) * | 2020-05-19 | 2020-08-18 | 上海先方半导体有限公司 | Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method |
| CN113257685A (en) * | 2021-07-14 | 2021-08-13 | 江苏华昶熠电子科技有限公司 | Semiconductor packaging device and manufacturing method thereof |
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