CN113467141A - Manufacturing method of array substrate and array substrate - Google Patents

Manufacturing method of array substrate and array substrate Download PDF

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Publication number
CN113467141A
CN113467141A CN202010247584.8A CN202010247584A CN113467141A CN 113467141 A CN113467141 A CN 113467141A CN 202010247584 A CN202010247584 A CN 202010247584A CN 113467141 A CN113467141 A CN 113467141A
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Prior art keywords
layer
array substrate
metal
copper
source
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孙学军
刘翔
杨松
李广圣
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Chengdu CEC Panda Display Technology Co Ltd
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Chengdu CEC Panda Display Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention provides a manufacturing method of an array substrate and the array substrate, wherein the manufacturing method comprises the following steps: depositing a gate metal layer on a substrate, and forming a gate and a scanning line on the gate metal layer by first photoetching; depositing a grid insulation layer, a semiconductor layer and a source drain metal layer in sequence, forming an active island on the semiconductor layer through second photoetching, forming a source electrode, a drain electrode and a data line on the source drain metal layer, and forming a channel region between the source electrode and the drain electrode; coating a color filter color resistance layer by a suspension coating process, and carrying out an exposure development process; depositing a protective layer, and forming a conductive through hole on the protective layer above the drain electrode and the color filter color resistance layer through third photoetching; and depositing a transparent conductive layer, and forming a pixel electrode on the transparent conductive layer through fourth photoetching, wherein the pixel electrode is communicated with the drain electrode through the conductive through hole. The array substrate and the manufacturing method thereof can prevent the oxidation of the silicon oxide protective layer to the metal copper.

Description

Manufacturing method of array substrate and array substrate
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a manufacturing method of an array substrate and the array substrate.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have the advantages of high image quality, power saving, thin body, and no radiation, and are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of Display devices. The liquid crystal display panel generally includes an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. The liquid crystal molecules can be controlled to rotate by applying a driving voltage between the array substrate and the color film substrate, so that light rays of the backlight module are refracted out to generate a picture.
In the manufacturing process of the array substrate provided by the prior art, the metal oxide semiconductor layer is used as an active layer, and the characteristics of a metal oxide TFT (thin film transistor) are sensitive to H and even the characteristics of the metal oxide TFT are lost, so that silicon oxide is generally used as a protective layer of the metal oxide TFT instead of silicon nitride.
However, the array substrate often uses metal copper as a source and drain metal layer, and when a protective layer of a metal oxide TFT containing silicon oxide is deposited, the metal copper is exposed to oxygen plasma, is severely oxidized, and even peels off.
Disclosure of Invention
The invention provides a manufacturing method of an array substrate and the array substrate, which can prevent a protective layer from oxidizing metal copper of a source electrode, a drain electrode and a data line.
One aspect of the present invention provides a method for manufacturing an array substrate, including:
depositing a gate metal layer on a substrate, and forming a gate and a scanning line on the gate metal layer through a first photoetching process;
sequentially depositing a grid insulation layer, a semiconductor layer and a source drain metal layer, forming an active island on the semiconductor layer through a second photoetching process, forming a source electrode, a drain electrode and a data line on the source drain metal layer, and forming a channel region between the source electrode and the drain electrode;
coating a color filter color resistance layer by a suspension coating process, and carrying out exposure development;
depositing a protective layer, and forming a conductive through hole on the protective layer above the drain electrode and the color filter color resistance layer through a third photoetching process;
and depositing a transparent conducting layer, and forming a pixel electrode on the transparent conducting layer through a fourth photoetching process, wherein the pixel electrode is communicated with the drain electrode through the conducting through hole.
According to the manufacturing method of the array substrate, the source and drain metal layer comprises the copper barrier layer and the metal copper layer covering the copper barrier layer.
In the manufacturing method of the array substrate, the source-drain metal layer further includes a copper protection layer covering the metal copper layer.
In the manufacturing method of the array substrate, the copper barrier layer and the copper protective layer both include chromium, tungsten, tantalum, molybdenum, or titanium.
In the method for manufacturing the array substrate, the thickness of the copper barrier layer is 1/20-1/10 of the metallic copper layer.
In the manufacturing method of the array substrate, the second photolithography process includes a gray-tone mask process or a halftone mask process.
In the manufacturing method of the array substrate, the second photolithography process specifically includes:
exposing and developing through a mask to form a completely transparent area, a partially transparent area and an opaque area, wherein the opaque area corresponds to the source electrode, the drain electrode and the data line, and the partially transparent area corresponds to the channel area;
etching the source drain metal layer and the semiconductor layer corresponding to the completely light-transmitting area for the first time;
carrying out a photoetching ashing process for one time, and removing the photoresist of the partial light-transmitting area; performing second etching to etch the source drain metal layer in the partial light-transmitting region to form the channel region;
and reserving the source drain metal layer corresponding to the light-tight region to form the source electrode, the drain electrode and the data line.
According to the manufacturing method of the array substrate, the gate metal layer comprises the adhesion layer and the metal copper layer covering the adhesion layer.
The manufacturing method of the array substrate comprises the steps that the semiconductor layer comprises a first metal oxide semiconductor layer and a second metal oxide semiconductor layer covering the first metal oxide semiconductor layer, and the electric conductivity of the first metal oxide semiconductor layer is lower than that of the second metal oxide semiconductor layer.
The array substrate is manufactured by the manufacturing method.
According to the manufacturing method of the array substrate and the array substrate, the metal oxide thin film transistor structure is adopted, the step of coating the color filter color resistance layer is added after the source electrode and the drain electrode are formed through the second photoetching process, so that the color filter color resistance layer at the position of the thin film transistor can absorb light, the illumination stability of the thin film transistor is improved, and meanwhile, the color filter color resistance layer above the data line can protect a metal copper layer in the data line from being oxidized when a protective layer is formed. In this embodiment, the data line, the source electrode and the drain electrode are both of a double-layer structure, the bottom layer is a barrier layer, the upper layer is a metal copper layer, and the barrier layer can prevent copper from diffusing into the semiconductor layer and increase the adhesion of the metal copper layer. In addition, a primary halftone or gray tone mask is used in the second photoetching process to simultaneously form a metal oxide semiconductor layer pattern, a source drain metal electrode, a data scanning line and a channel region between the source drain, so that 2 times of photoetching processes are saved, and the production efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 3 is a cross-sectional view along the AB direction after the first photolithography process is performed on the array substrate according to the embodiment of the present invention;
fig. 4 is a cross-sectional view along the direction AB after the exposure and development in the second photolithography process are completed on the array substrate according to the embodiment of the present invention;
fig. 5 is a cross-sectional view along the AB direction after the array substrate provided by the embodiment of the invention is subjected to the first etching in the second photolithography process;
FIG. 6 is a cross-sectional view along the AB direction after the ashing of the array substrate in the second photolithography process is completed according to the embodiment of the present invention;
fig. 7 is a cross-sectional view along the AB direction of the array substrate after the second photolithography process is performed;
fig. 8 is a cross-sectional view along the direction AB after the color filter color resist layer is coated on the array substrate according to the embodiment of the invention;
fig. 9 is a cross-sectional view of the array substrate at the data line after the color filter color resistance layer is coated;
fig. 10 is a cross-sectional view along the AB direction of the array substrate after the third photolithography process is performed;
FIG. 11 is a cross-sectional view taken along the direction AB after a fourth photolithography process is performed on the array substrate according to the embodiment of the present invention;
fig. 12 is a cross-sectional view of the array substrate provided in the embodiment of the invention at the data line after the fourth photolithography process is completed.
Reference numerals:
10-a substrate base plate; 11-a gate; 111-an adhesion layer; 12-a scan line; 13-a gate insulating layer; 14-a semiconductor layer; 15-source drain metal layer; 151-copper barrier layer; 152-a metallic copper layer; 17-a source electrode; 18-a drain electrode; 19-a data line; 20-a channel region; 21-color filter color resistance layer; 22-a protective layer; 23-a conductive via; 24-pixel electrodes; 25-photoresist; 251-a fully light transmitting region; 252-partially light transmitting areas; 253-opaque areas.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that, a conventional liquid crystal display panel is formed by attaching a Thin Film Transistor Array Substrate (TFT Array Substrate for short) to a Color Filter Substrate (CF Substrate for short), a pixel electrode and a common electrode are formed on the Array Substrate and the Color Filter Substrate, respectively, and liquid crystal is filled between the Array Substrate and the Color Filter Substrate.
A Mask (Mask), also called a Photo Mask (Photo Mask), is a pattern Mask used in a Photolithography process, in which a Mask pattern is formed on a transparent substrate by a light-opaque light-shielding film (chrome metal), and the pattern is transferred onto a film of a glass substrate by a Photolithography process (Photo lithography). The Exposure (Exposure) process is a process in which Ultraviolet (Ultraviolet) rays are irradiated on a photoresist (Photo Resist) through a reticle, and a pattern on the reticle is transferred onto the photoresist. In the array engineering, the photoresist plays a role of a mask, a photoresist pattern is formed through exposure, in an etching process, a thin film layer on a substrate corresponding to the photoresist pattern is reserved, other areas are etched, finally, the photoresist is removed, the pattern on the mask is transferred to the substrate, the process is called photoetching (Photolithography), and each photoetching process comprises the steps of thin film deposition, photoresist coating, exposure, development, etching and photoresist stripping.
It is understood that the number of photolithography steps affects both the yield and the manufacturing cost of the panel, and therefore, the fewer the photolithography steps, the better.
In the manufacturing process of the array substrate provided by the prior art, the metal oxide semiconductor layer is used as an active layer, and the characteristics of a metal oxide TFT (thin film transistor) are sensitive to H and even the characteristics of the metal oxide TFT are lost, so that silicon oxide is generally used as a protective layer of the metal oxide TFT instead of silicon nitride. However, the array substrate often uses metal copper as a source and drain metal layer, and when a protective layer of a metal oxide TFT containing silicon oxide is deposited, the metal copper is exposed to oxygen plasma, is severely oxidized, and even peels off.
In order to solve the above problem, in the embodiment, after the source electrode, the drain electrode and the data line are formed by etching, a color filter layer is additionally disposed to separate the metal copper and the protection layer containing silicon oxide to prevent the metal copper from being oxidized.
The following describes a manufacturing method of an array substrate and the array substrate provided by the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and referring to fig. 1, the array substrate according to the embodiment of the present invention includes a plurality of pixel regions, where scan lines 12 and data lines 19 are arranged crosswise and surround the pixel regions, a pixel electrode 24 is covered on a surface of the pixel region, a thin film transistor is disposed at an edge of the pixel region, and the thin film transistor includes a gate connected to the scan lines 12, a source 17 connected to the data lines 19, and a drain 18 connected to the pixel electrode 24 through a conductive via 23.
It should be noted that fig. 1 is a plan view of the array substrate, and a partial structure of the array substrate is not shown in fig. 1 due to a view angle, and thus is not described herein.
Fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention, and referring to fig. 2, the method for manufacturing an array substrate according to an embodiment of the present invention includes:
s101, depositing a gate metal layer on the substrate base plate 10, and forming a gate electrode 11 and a scanning line 12 on the gate metal layer through a first photoetching process.
Specifically, the thickness of the film is about the same as that of the film deposited on the substrate 10 by sputtering or thermal evaporation
Figure BDA0002434360320000051
The gate metal layer can be made of Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and the gate metal layer consisting of multiple layers of metals can also meet the requirement.
Fig. 3 is a cross-sectional view along the AB direction of the array substrate according to the embodiment of the invention after the first photolithography process is completed, and referring to fig. 3, after the first photolithography process, the gate metal layer finally forms a gate electrode 11, and a scan line 12 as shown in fig. 1. In one possible embodiment, the gate metal layer includes an adhesion layer 111 and a metal copper layer covering the adhesion layer 111. The adhesion layer 111 may be Cr, W, Ti alloy, Ta, Mo alloy, etc., and the thickness of the adhesion layer 111 is about
Figure BDA0002434360320000061
The thickness of the metallic copper layer is about
Figure BDA0002434360320000062
The adhesion layer 111 is provided mainly for increasing adhesion of a metal copper layer on the substrate base plate 10 to improve reliability of the gate electrode 11 and the scan line 12.
S102, depositing the gate insulating layer 13, the semiconductor layer 14 and the source-drain metal layer 15 in sequence, forming an active island on the semiconductor layer 14 through a second photoetching process, forming a source electrode 17, a drain electrode 18 and a data line 19 on the source-drain metal layer 15, and forming a channel region 20 between the source electrode 17 and the drain electrode 18.
Fig. 4 is a cross-sectional view along the AB direction after the exposure and development of the array substrate in the second photolithography process is completed, and referring to fig. 4, in S102, first, a continuous deposition is performed on the substrate 10 having completed S101 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a film having a thickness of
Figure BDA0002434360320000063
The gate insulating layer 13 may be an oxide, a nitride, or an oxynitride, and the corresponding reaction gas may be SiH4，NH3，N2Or SiH2Cl2，NH3，N2。
Then, the semiconductor layer 14 is deposited by a sputtering method. The semiconductor layer 14 may be an amorphous oxide semiconductor or a polycrystalline oxide semiconductor, such as amorphous indium gallium zinc oxide a-IGZO, HIZO, IZO, a-InZnO, ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, either in a single layer or in multiple layers.
In one possible embodiment, the semiconductor layer 14 includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer overlying the first metal oxide semiconductor layer, the first metal oxide semiconductor layer having a lower electrical conductivity than the second metal oxide semiconductor layer.
Wherein the thickness of the first metal oxide semiconductor layer is
Figure BDA0002434360320000064
The second metal oxide semiconductor layer has a thickness of
Figure BDA0002434360320000065
In the deposition of metal oxygenIn the case of an oxide semiconductor layer, the conductivity of the metal oxide semiconductor can be effectively controlled by controlling the oxygen content in the metal oxide semiconductor thin film, the higher the oxygen content in the deposited metal oxide semiconductor thin film, the better the conductivity of the metal oxide semiconductor thin film is and the closer to a conductor, and the lower the oxygen content in the deposited metal oxide semiconductor thin film, the worse the conductivity of the metal oxide semiconductor thin film is and the closer to a semiconductor.
In this embodiment, the first metal oxide semiconductor layer with lower conductivity is directly in contact with the gate insulating layer 13 to form a channel of the thin film transistor, so that the performance of the thin film transistor is more stable. The second metal oxide semiconductor layer with higher conductivity is in contact with the source electrode 17 and the drain electrode 18, so that the contact resistance of the semiconductor layer 14 and the source electrode 17 and the drain electrode 18 is reduced, and the on-state current of the thin film transistor is improved.
Then, depositing by sputtering or thermal evaporation to a thickness of
Figure BDA0002434360320000071
The source-drain metal layer 15 may be made of Cr, W, Ti, Ta, Mo, or other metals and alloys, and may be a single layer or a multilayer. In one possible embodiment, the source-drain metal layer 15 includes a copper barrier layer 151 and a metallic copper layer 152 overlying the copper barrier layer 151. The copper barrier layer 151 may be Cr, W, Ti, Ta, Mo alloy, Ti alloy, or the like, and the copper barrier layer 151 serves as a barrier layer of the metal copper layer 152, which may prevent the metal copper layer 152 from diffusing into the semiconductor layer 14 and may increase the adhesion of the metal copper layer 152. Wherein the thickness of the copper barrier layer 151 is 1/20-1/10 of the metallic copper layer 152, and specifically, the thickness of the copper barrier layer 151 is about
Figure BDA0002434360320000072
The thickness of metallic copper layer 152 is about
Figure BDA0002434360320000073
Optionally, the source-drain metal layer 15 may further include a copper protection layer (not shown) covering the metal copper layer 152, and the copper protection layer may be Cr, W, Ti, Ta, Mo alloy, Ti alloy, or the like, and may be provided in conformity with the material of the copper barrier layer 151. The copper protective layer is provided to protect the copper metal layer 152, and prevent the color filter color resist layer and the protective layer containing silicon oxide formed in the subsequent steps from affecting the performance of the copper metal layer 152.
Specifically, the second photolithography is performed by a halftone mask process or a gray tone mask process. Among them, a Half-tone Mask (HTM for short) is a process of incompletely exposing a photoresist by using a semi-permeable membrane on the Mask. A Gray-tone Mask (Gray-tone Mask) is a process for incompletely exposing a photoresist by using a light blocking strip of a Gray scale area on the Mask.
With continued reference to fig. 4, after exposure and development through the mask, the array substrate is divided into a completely transparent region 251, a partially transparent region 252 and an opaque region 253, the opaque region 253 is provided with a thicker photoresist 25, the partially transparent region 252 is provided with a thinner photoresist 25, and the completely transparent region 251 is not provided with the photoresist 25. The opaque region 253 corresponds to a region where the source electrode 17, the drain electrode 18, and the data line 19 are located, the partially transparent region 252 corresponds to the channel region 20, and the fully transparent region 251 corresponds to a region excluding the opaque region 253 and the partially transparent region 252.
Fig. 5 is a cross-sectional view along the AB direction after the array substrate provided in the embodiment of the present invention is subjected to the first etching in the second photolithography process, and referring to fig. 5, the first etching is performed on the basis of fig. 4 to etch the source/drain metal layer 15 and the semiconductor layer 14 corresponding to the completely light-transmitting region 251, so that only the gate insulating layer 13 and the portion below the completely light-transmitting region 251 are remained. After the first etching is completed, the semiconductor layer 14 forms an active island, the source-drain metal layer 15 above the active island is reserved, and the semiconductor layer 14 and the source-drain metal layer 15 outside the active island are etched.
Fig. 6 is a cross-sectional view along the direction AB after the array substrate provided in the embodiment of the invention is subjected to ashing in the second photolithography process, and referring to fig. 6, a photolithography ashing process is performed on the basis of fig. 5 to remove the photoresist 25 in a portion of the light-transmitting region 252, and the photoresist 25 in the light-blocking region 251 is thinned.
Fig. 7 is a cross-sectional view along the AB direction after the array substrate provided in the embodiment of the present invention is subjected to the second photolithography process, and referring to fig. 7, on the basis of fig. 6, a second etching is performed to etch away part of the source/drain metal layer 15 in the light-transmitting region 252 to form a channel region 20; meanwhile, the source-drain metal layer 15 corresponding to the opaque region 253 remains, and the source electrode 17, the drain electrode 18, and the data line 19 are formed.
It should be noted that, during the second etching, the second metal oxide semiconductor layer in the channel region 20 can be etched away, the first metal oxide semiconductor layer in the channel region 20 remains, and the first metal oxide semiconductor layer with low conductivity can make the performance of the thin film transistor more stable.
Further, in order to improve the performance of the thin film transistor, a surface of the first metal oxide semiconductor layer in the channel region 20 may be subjected to a primary treatment, such as a nitrous oxide treatment, to repair damage and contamination to the first metal oxide semiconductor layer during etching.
And S103, coating the color filter color resistance layer 21 through a suspension coating process, and carrying out exposure development.
Fig. 8 is a cross-sectional view along the direction AB after the array substrate provided by the embodiment of the invention is completely coated with a color filter color resistance layer, and referring to fig. 8, on the basis of fig. 7, a color filter color resistance material is coated by a suspension coating process, and then an exposure developing process is performed to form the color filter color resistance layer 21 shown in fig. 8. The color filter color resistance layer 21 located at the thin film transistor can absorb light, and the stability of light irradiation of the thin film transistor is improved.
Fig. 9 is a cross-sectional view of the array substrate after the color filter color-resist layer is coated, and referring to fig. 9, the color filter color-resist layer 21 covers the data line 19 to prevent the copper metal layer of the data line 19 from being oxidized by the protective layer containing silicon oxide formed in the subsequent step.
And S104, depositing the protective layer 22, and forming a conductive through hole 23 on the protective layer 22 and the color filter color resistance layer 21 above the drain electrode 18 through a third photoetching process.
FIG. 10 is a cross-sectional view taken along the AB direction after a third photolithography process is performed on the array substrate according to an embodiment of the present invention, and referring to FIG. 10, specifically, a thickness of the array substrate is continuously deposited by a plasma enhanced chemical vapor deposition method based on FIG. 8
Figure BDA0002434360320000081
The protective layer 22 may be made of an oxide, a nitride, or an oxynitride, and may be a single layer or a plurality of layers. The reaction gas corresponding to the silicon oxide may be SiH4、N2The reaction gas corresponding to O, nitride or oxynitride can be SiH4，NH3，N2Or SiH2Cl2，NH3，N2。
After the protective layer is deposited, a third photolithography process is further required to correspondingly form a conductive via 23 on the protective layer 22 and the color filter color resist layer 21, and the conductive via 23 is located above the drain 18 and is used for communicating the drain 18 with the pixel electrode 24.
And S105, depositing a transparent conductive layer, and forming a pixel electrode 24 on the transparent conductive layer through a fourth photoetching process, wherein the pixel electrode 24 is communicated with the drain electrode 18 through the conductive through hole 23.
Fig. 11 is a cross-sectional view along the AB direction of the array substrate after the fourth photolithography process is completed, and referring to fig. 11, specifically, on the basis of completing S104, a thickness of the array substrate is continuously deposited by sputtering or thermal evaporation
Figure BDA0002434360320000091
The transparent conductive layer of (2) may be indium tin oxide ITO or indium zinc oxide IZO, or other transparent metal oxides. Through the fourth photolithography process, the transparent conductive layer is formed into the pixel electrode 24, and the pixel electrode 24 and the drain electrode 18 are communicated through the conductive via 23.
Fig. 12 is a cross-sectional view of the data line after the fourth photolithography process is performed on the array substrate according to the embodiment of the invention, referring to fig. 12, a color filter color-resist layer 21 and a protection layer 22 are provided above the data line 19, and the color filter color-resist layer 21 without the pixel electrode 24 plays a role in protecting the metal copper layer of the data line 19 and preventing copper from being oxidized when the protection layer 22 is formed.
According to the manufacturing method of the array substrate and the array substrate, the metal oxide thin film transistor structure is adopted, the step of coating the color filter color resistance layer is added after the source electrode and the drain electrode are formed through the second photoetching process, so that the color filter color resistance layer at the position of the thin film transistor can absorb light, the illumination stability of the thin film transistor is improved, and meanwhile, the color filter color resistance layer above the data line can protect a metal copper layer in the data line from being oxidized when a protective layer is formed. In this embodiment, the data line, the source electrode and the drain electrode are both of a double-layer structure, the bottom layer is a barrier layer, the upper layer is a metal copper layer, and the barrier layer can prevent copper from diffusing into the semiconductor layer and increase the adhesion of the metal copper layer. In addition, a primary halftone or gray tone mask is used in the second photoetching process to simultaneously form a metal oxide semiconductor layer pattern, a source drain metal electrode, a data scanning line and a channel region between the source drain, so that 2 times of photoetching processes are saved, and the production efficiency is improved.
In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", and the like, are used to indicate an orientation or positional relationship based on that shown in the drawings, merely to facilitate the description of the invention and to simplify the description, and do not indicate or imply that the position or element referred to must have a particular orientation, be of particular construction and operation, and thus, are not to be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; may be mechanically coupled, may be electrically coupled or may be in communication with each other; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A manufacturing method of an array substrate is characterized by comprising the following steps:
depositing a gate metal layer on a substrate, and forming a gate and a scanning line on the gate metal layer through a first photoetching process;
depositing a grid insulation layer, a semiconductor layer and a source drain metal layer in sequence, forming an active island on the semiconductor layer through a second photoetching process, forming a source electrode, a drain electrode and a data line on the source drain metal layer, and forming a channel region between the source electrode and the drain electrode;
coating a color filter color resistance layer by a suspension coating process, and carrying out exposure development;
depositing a protective layer, and forming a conductive through hole on the protective layer above the drain electrode and the color filter color resistance layer through a third photoetching process;
and depositing a transparent conducting layer, and forming a pixel electrode on the transparent conducting layer through a fourth photoetching process, wherein the pixel electrode is communicated with the drain electrode through the conducting through hole.
2. The manufacturing method of claim 1, wherein the source-drain metal layer comprises a copper barrier layer and a metal copper layer covering the copper barrier layer.
3. The method of claim 2, wherein the source drain metal layer further comprises a copper protection layer overlying the copper metal layer.
4. The method of claim 3, wherein the copper barrier layer and the copper protective layer each comprise chromium, tungsten, tantalum, molybdenum, or titanium.
5. The method of claim 2, wherein the copper barrier layer has a thickness of 1/20-1/10 of the metallic copper layer.
6. The method of claim 1, wherein the second photolithography process comprises a gray tone mask process or a halftone mask process.
7. The method according to claim 6, wherein the second photolithography process specifically comprises:
exposing and developing through a mask to form a completely transparent area, a partially transparent area and an opaque area, wherein the opaque area corresponds to the source electrode, the drain electrode and the data line, and the partially transparent area corresponds to the channel area;
etching the source drain metal layer and the semiconductor layer corresponding to the completely light-transmitting area for the first time;
carrying out a photoetching ashing process for one time, and removing the photoresist of the partial light-transmitting area; performing second etching to etch the source drain metal layer in the partial light-transmitting region to form the channel region;
and reserving the source drain metal layer corresponding to the light-tight region to form the source electrode, the drain electrode and the data line.
8. The method of claim 1, wherein the gate metal layer comprises an adhesion layer and a metal copper layer overlying the adhesion layer.
9. The method according to claim 1, wherein the semiconductor layer comprises a first metal oxide semiconductor layer and a second metal oxide semiconductor layer covering the first metal oxide semiconductor layer, and wherein the first metal oxide semiconductor layer has a lower electrical conductivity than the second metal oxide semiconductor layer.
10. An array substrate manufactured by the manufacturing method of any one of claims 1 to 9.
CN202010247584.8A 2020-03-31 2020-03-31 Manufacturing method of array substrate and array substrate Pending CN113467141A (en)

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