CN113466277B - Preparation method of test sample and test sample - Google Patents
Preparation method of test sample and test sample Download PDFInfo
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Abstract
The embodiment of the disclosure discloses a preparation method of a test sample. The method comprises the following steps: providing a structure to be processed comprising a failure region; wherein the structure to be processed comprises: the multi-stage step comprises a dielectric layer covering the step, a contact plug positioned above the surface of the step and arranged in the dielectric layer, and a virtual channel column penetrating through the step; thinning the structure to be processed towards the steps along a preset direction intersecting with the inclined plane where the multistage steps are located to form a preprocessed sample; wherein the pre-treated sample comprises the failure zone; along the preset direction, the thickness of the contact plug remained on the surface of the pretreated sample is greater than or equal to a first preset thickness; and removing the dielectric layer remained on the surface of the pretreatment sample to expose the virtual channel column to form the test sample.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a preparation method of a test sample and the test sample.
Background
In the development and production processes of semiconductor devices, an abnormality usually occurs in a certain portion of the device, and at this time, the failure region needs to be analyzed to find out an abnormal problem. Through failure analysis, research and development and production personnel can be helped to find out the problems of defects in design, abnormal change of process parameters or misoperation in production and the like, and necessary feedback information is provided for subsequent product design or production.
In the process of performing failure analysis, preparing a test sample becomes the primary step in performing failure analysis. Therefore, it is important to provide a good test sample to improve the test efficiency or reduce the test cost. However, in the related art, due to the defects of the sample preparation method, the efficiency of preparing the test sample for failure analysis is low, the cost is high, and the actual requirements cannot be met. Therefore, how to improve the sample preparation efficiency and reduce the cost of failure analysis is a problem that needs to be solved urgently.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a method for preparing a test sample and a test sample.
According to a first aspect of embodiments of the present disclosure, there is provided a method of preparing a test sample, comprising:
providing a structure to be processed comprising a failure region; wherein the structure to be processed comprises: the multi-stage step comprises a dielectric layer covering the step, a contact plug positioned above the surface of the step and arranged in the dielectric layer, and a virtual channel column penetrating through the step;
thinning the structure to be processed towards the steps along a preset direction intersecting with the inclined plane where the multistage steps are located to form a preprocessed sample; wherein the pre-treated sample comprises the failure zone; along the preset direction, the contact plug remained on the surface of the pretreated sample is greater than or equal to a first preset thickness;
and removing the dielectric layer remained on the surface of the pretreatment sample to expose the virtual channel column to form the test sample.
In some embodiments, the thinning the structure to be processed toward the step along a preset direction intersecting with the inclined plane where the multistage step is located includes:
under a first current, adopting a focused ion beam process to perform first thinning treatment on the structure to be treated towards the step along the preset direction;
after the structure to be processed is subjected to the first thinning treatment for a first preset time, under a second preset current, a focused ion beam process is adopted, and the structure to be processed is subjected to second thinning treatment towards the step along the preset direction;
wherein the first preset current is greater than the second preset current.
In some embodiments, the thinning the structure to be processed toward the step along a preset direction intersecting with the inclined plane where the multistage step is located further includes:
detecting the structure to be processed to obtain a first detection image;
when the top surface of the virtual channel column is not exposed in the first detection image, continuing to perform the second thinning treatment on the structure to be processed;
and when the top surface of the virtual channel column is exposed in the first detection image, stopping performing the second thinning treatment on the structure to be processed.
In some embodiments, the process conditions of the first thinning process include: the first voltage range of the focused ion beam process is 5-30 kV, and the first current range is 1-60 nanoamperes;
the processing conditions of the second thinning processing include: the second voltage range of the focused ion beam process is 5 kilovolts to 30 kilovolts, and the second current range is 0.1 nanoamperes to 15 nanoamperes.
In some embodiments, the removing the dielectric layer remaining on the surface of the pretreatment sample to expose the dummy trench pillar to form the test sample includes:
and soaking the pretreatment sample for at least 1 time by adopting etching liquid to expose the top surface of the virtual channel column to form the test sample.
In some embodiments, the immersing the pre-processed sample at least 1 time with an etching solution to expose the top surface of the dummy trench pillar to form the test sample includes:
soaking the pretreatment sample for the nth time by using the etching liquid for a second preset time so as to enable the etching liquid to perform chemical reaction with the pretreatment sample and generate a liquid product and/or a gaseous product; wherein n is a natural number greater than or equal to 1;
separating the pretreated sample soaked for the nth time from the etching solution, and removing the etching solution attached to the surface of the pretreated sample;
detecting the pretreated sample soaked for the nth time to obtain a second detection image;
when the top surface of the virtual channel column is not exposed in the second detection image, soaking the pretreated sample subjected to the nth soaking by the etching liquid for the second preset time;
determining that the test sample is formed when the top surfaces of the dummy channel pillars are exposed in the second inspection image.
In some embodiments, the second preset duration ranges from 5s to 15 s.
In some embodiments, the etching liquid includes: hydrofluoric acid or buffered oxide etch solutions.
In some embodiments, the structure to be processed includes two sidewalls oppositely disposed, and the contact plug is located in a dielectric layer between the two sidewalls, and the method further includes:
thinning at least one side wall until the side face of the multistage step is exposed;
locating a target range including the failure region;
along crossing in the preset direction on multistage step place inclined plane, orientation the step attenuate pending structure to form the preliminary treatment sample that has preset thickness, include:
and thinning the target range towards the steps along a preset direction intersecting with the inclined plane where the multistage steps are located so as to form the pretreatment sample.
According to a second aspect of embodiments of the present disclosure, there is provided a test sample prepared using the method of any one of the above embodiments.
According to the embodiment of the disclosure, the structure to be processed is thinned to the preset thickness along the direction intersecting with the inclined plane where the multistage step is located, so that a part of the contact plug and the dielectric layer on the surface of the step is removed, and a preprocessed sample is obtained. And removing the residual dielectric layer on the step of the preprocessed sample to expose the virtual channel column, thereby obtaining the test sample with the contact plug and the virtual channel column exposed on the surface of the step at the same time. Therefore, when the test sample is detected to obtain a detection image, the detection images of the contact plug and the virtual channel column can be clearly displayed, so that the position information of the contact plug and the virtual channel column can be accurately obtained.
The test sample prepared by the method disclosed by the embodiment of the disclosure can be directly used for Scanning Electron Microscope (SEM) detection, can replace TEM (Transmission Electron Microscope) detection, and can greatly save sample preparation time and sample preparation cost compared with a TEM sample with complex preparation requirements. In addition, the method for preparing the test sample in the embodiment of the disclosure can prepare samples in a large area, so that a larger detection area can be obtained in one sample, and the sample preparation quantity is reduced. In addition, according to the test sample prepared according to the embodiment of the disclosure, the SEM is adopted to replace the TEM for detection, so that the use cost of the detection equipment can be reduced, and the cost of failure analysis can be further reduced.
Drawings
FIG. 1 is a plot of a step zone local topography of a sample according to an exemplary embodiment;
FIGS. 2 a-2 d are schematic diagrams illustrating a test sample preparation method according to an exemplary embodiment;
FIG. 3 is a step surface structure diagram of another test specimen shown in accordance with an exemplary embodiment;
FIG. 4 is a flow chart illustrating a method of preparing a test sample according to an exemplary embodiment;
FIG. 5 is a partial schematic view of a structure to be processed in accordance with an exemplary embodiment;
FIG. 6 is a schematic illustration of a thinning direction according to an exemplary embodiment;
FIGS. 7-9 are schematic diagrams illustrating a test sample preparation method according to an exemplary embodiment;
FIG. 10 is a partial schematic view of another pending structure shown in accordance with an exemplary embodiment;
fig. 11a to 11c are schematic diagrams illustrating a method for automatically measuring a relative position deviation according to an exemplary embodiment.
Detailed Description
The technical solution of the present disclosure is further described in detail with reference to the drawings and specific embodiments.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not used for describing a particular order or sequence.
In the disclosed embodiment, the term "a is in contact with B" includes the case where a is in direct contact with B, or A, B is in contact with B indirectly with another component interposed between the two.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sublayers.
It is to be understood that the meaning of "on … …", "over … …" and "over … …" in this disclosure is to be interpreted in its broadest sense such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.
It should be noted that although the present description is described in terms of embodiments, not every embodiment includes only a single technical solution, and such description of the embodiments is merely for clarity, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that can be understood by those skilled in the art.
3D NAND memory, an emerging non-volatile memory, has greatly improved storage density compared to two-dimensional (2D) memory due to its unique three-dimensional structure. The 3D NAND memory generally includes a silicon substrate, and a stacked structure in which insulating layers and conductive layers are alternately stacked on the silicon substrate. The conductive layer mainly serves as a gate layer (including a word line layer and a selection gate layer), and the insulating layer serves as an interlayer dielectric layer to separate the gate layers. The laminated structure comprises a core area and a step area, the core area is an area where the memory unit is located, and a channel column penetrating through the laminated structure is formed in the core area along a direction perpendicular to the substrate, so that a memory string comprising a plurality of memory units is formed, and the memory density on the unit substrate area is improved.
The step regions are generally located at both ends of the stacked structure, and include multi-step, which is a stepped structure formed at the end of the stacked structure due to each conductive layer and each insulating layer in the stacked structure extending for different lengths in a direction parallel to the substrate. Each level of steps may comprise at least one conductive layer and at least one insulating layer. A conductive Contact plug (CT) is formed on each step, and is electrically connected to the conductive layer to lead out the conductive layer and connect to a control circuit.
In the process of manufacturing the 3D NAND memory by the "gate last" process, a sacrificial layer is usually formed at a position where a gate layer is formed, a channel pillar penetrating through the stacked structure is formed, the sacrificial layer is removed, and a conductive layer is filled in a gap where the sacrificial layer is removed. In order to prevent the collapse of the stacked structure of the stepped region when the sacrificial layer is removed, Dummy Channel pillars (DCH) penetrating the stacked structure of the stepped region are formed in the stepped region to support the stacked structure.
Normally, the contact plug and the dummy channel pillar cannot overlap as viewed in a direction perpendicular to the substrate. When the contact plug overlaps the dummy trench pillar, there is a risk of leakage, which may cause memory failure and reduce yield.
FIG. 1 is a partial top view of a stepped region of a sample according to one example. Referring to fig. 1, the contact plug 21 is deviated from the predetermined position, and even a portion of the contact plug 21 overlaps the dummy channel pillar 22, and therefore, it is necessary to find an abnormal region and determine a positional deviation of the contact plug 21 with respect to the dummy channel pillar 22, thereby better correcting the formation position of the contact plug 21.
The test samples for detecting the positional deviation of the contact plugs with respect to the dummy channel pillars include preparing TEM samples for observation by a transmission electron microscope using a Focused Ion Beam (FIB), and preparing SEM samples for observation by a scanning electron microscope.
When a transmission electron microscope is used to detect a sample, because the TEM has higher requirements on the sample than the SEM, the FIB is usually used to thin the sample to a very small thickness to form a thin sheet, so as to obtain images of the contact plugs and the dummy channel pillars located at different layers. And the TEM sample is small, the detected area is very limited, sometimes, in order to obtain a complete image of a certain structural area, even a plurality of samples need to be spliced together, the sample preparation difficulty is high, the sample preparation success rate is low, and the consumed time is long. Therefore, the sample preparation cost of TEM samples is high.
Fig. 2a to 2d show schematic diagrams of a method for preparing SEM samples using FIB according to an exemplary embodiment, the method comprising the steps of:
the method comprises the following steps: referring to fig. 2a, the first sample is formed by thinning the sample toward the step in a direction perpendicular to the slope where the multistage step is located to a position close to the step and leaving a portion of each contact plug 21.
Fig. 2b shows a surface topography of the first sample, and referring to the topography shown in fig. 2b, although the contact plug 21 has a clear topography, since the step surface is covered with a part of the dielectric layer, the profile of the dummy trench pillar 22 in the detection image obtained by SEM is very blurred, and the position thereof cannot be accurately measured.
Step two: referring to fig. 2c, the first sample formed in step one is further processed by etching down the step surface in a direction perpendicular to the step surface using a focused ion beam (as indicated by the arrow in fig. 2 c) to remove the dielectric layer overlying the step to form a second sample.
Fig. 2d shows a surface topography of the second sample, and referring to the topography shown in fig. 2d, it can be seen that, since the dielectric layer covering the step surface is removed, the profile of the dummy trench pillar 22 in the SEM detection image is relatively clear, but if the dielectric layer on the step is completely removed to expose the dummy trench pillar, the contact plug 21 is also etched, and the integrity of the contact plug 21 cannot be ensured; or, on the premise of ensuring the integrity of the contact plug 21, the dielectric layer on the step cannot be removed completely, and thus the clear profile of the large-area virtual trench pillar 22 cannot be ensured.
Fig. 3 shows a structure diagram of a sample object obtained by another sample processing method in which a sample is directly subjected to acid soaking treatment, and the dielectric layer is removed by immersing the sample in an acid solution that reacts with the dielectric layer, thereby exposing the contact plugs 21 and the dummy trench pillars 22. The dielectric layer covering the surface of the step is thick, so that the pickling treatment needs a long time. In addition, the contact plug 21 has a high height, and is easy to collapse when the support of the dielectric layer is lost. As can be seen from the physical diagram shown in fig. 3, since many contact plugs 21 are inclined or collapsed, the positions thereof cannot be detected, and further, the positional deviation of the contact plugs 21 with respect to the dummy trench posts 22 cannot be determined.
Fig. 4 is a flow chart illustrating a method of preparing a test sample according to an embodiment of the present disclosure. Referring to fig. 4, the method includes the steps of:
s100: providing a structure to be processed comprising a failure region; wherein, pending structure includes: the device comprises a multi-stage step, a dielectric layer covering the step, a contact plug positioned above the surface of the step and arranged in the dielectric layer, and a virtual channel column penetrating through the step.
S110: reducing the structure to be processed towards the steps along a preset direction intersecting with the inclined plane where the multistage steps are located to form a pre-processing sample; wherein the pretreated sample includes the failure region; the thickness of the contact plug remained on the surface of the pretreatment sample is greater than or equal to a first preset thickness along the preset direction.
S120: and removing the residual dielectric layer on the surface of the pretreatment sample to expose the virtual channel column to form a test sample.
The structure to be processed may include a structure having a semiconductor device. For example, the structure to be processed may include: structures with three-dimensional NAND memory, etc. The structure to be processed may further include: a partial structure of a three-dimensional NAND memory, and the like.
Illustratively, referring to fig. 5, the structure to be processed 100 includes a plurality of steps, and a dielectric layer 13 is covered on the steps. The contact plug 11 is located in the dielectric layer 13 and contacts the upper surface of each step. The dummy trench pillar 12 penetrates the step structure.
It is emphasized that the dummy channel pillar 12 does not overlap the contact plug 11 in the extending direction of the dummy channel pillar 12, and the top of the dummy channel pillar 12 and the bottom of the contact plug 11 are located on the upper surface of each step.
Typically, the failure zone is located inside the structure to be treated. For example, the electrical failure analysis may be performed on the structure to be processed to determine an approximate position of the failure region in the structure to be processed, and thus, the region to be thinned of the structure to be processed is determined according to the approximate position in S110.
Exemplary failure zones may include: in a plane parallel to the upper surface of the step, a contact plug 11 overlaps with the dummy channel pillar 12.
Illustratively, the inclined plane of the multistage step comprises: the plane where the vertexes of the steps are located, or the fitting plane where the vertexes of the steps are located.
In some embodiments, the predetermined direction may intersect with the slope of the multi-step, in practical applications, as shown in fig. 6, an included angle between the slope SS 'of the multi-step and the upper surface of the substrate is α, an included angle between the predetermined direction in step S110 and the slope SS' of the multi-step is θ, and θ may be set to be greater than α and less than α +90 °, that is, the predetermined direction is between a direction perpendicular to the upper surface of the substrate and a direction parallel to the upper surface of the substrate.
In some embodiments, in the process of thinning the structure to be processed toward the step along the preset direction, an included angle between the preset direction and an inclined plane where the multistage step is located may be adjusted according to the state that the structure to be processed is thinned to control the thinning direction, so as to reduce the thickness of the dielectric layer above the step as much as possible in the process of thinning the dielectric layer above the step and the contact plug on the premise of ensuring the integrity of the bottom of the contact plug, thereby improving the thinning quality.
Illustratively, S110 may include: and thinning the structure to be processed by using a focused ion beam towards the step along a preset direction vertical to the inclined plane where the multistage step is located, and reducing the structure above the step by a certain thickness (for example, thinning the structure to the dotted line in fig. 5) to form a pretreatment sample.
In some embodiments, the predetermined direction for thinning the structure to be processed may also be a direction that is not perpendicular to the inclined plane where the multi-step is located.
During the thinning process, each contact plug 11 and the dielectric layer 13 are simultaneously partially cut away. Therefore, the formed pre-processed sample still has a certain thickness of the contact plug 11 and a certain thickness of the dielectric layer 13 remaining on each step. Since the dielectric layer overlying the step is now thin, the profile of the top surface of the dummy trench pillar 12 can be observed through the dielectric layer.
Illustratively, the first preset thickness may include: the minimum value of the thickness of the contact plug is greater than zero in the direction in which the contact plug extends.
In the formed pretreatment sample, the thickness of the dielectric layer which is remained on the surface of the step and covers the virtual channel column is smaller than or equal to a second preset thickness. The second predetermined thickness may include: the thickness of the dielectric layer above the top surface of the dummy channel pillar is greater than zero in the direction in which the contact plug extends, and the profile of the top surface of the dummy channel pillar is observed through the dielectric layer. The first preset thickness and the second preset thickness can be set by setting the thinning end point position, namely the distance between the thinning plane and the inclined plane where the multistage step is located can be obtained by controlling the thinning end time of the structure to be processed, so that the first preset thickness and the second preset thickness are controlled.
It is to be noted that when the outline of the top surface of the dummy channel pillar 12 is observed to be clear, the thinning is considered to be completed, that is, the thinning reaches the end position.
Illustratively, S120 may include: and removing the residual dielectric layer 13 on the step in the preprocessed sample by using etching liquid only reacting with the dielectric layer 13 to expose the top of the virtual channel column 12, so as to obtain the tested sample. At this time, the contact plug 11 and the dummy channel pillar 12 may be simultaneously exposed on the upper surface of each step, so that the position profiles of the contact plug 11 and the dummy channel pillar 12 can be clearly displayed in the inspection image of the test sample, so as to accurately acquire the position information of the contact plug 11 and the dummy channel pillar 12.
In the embodiment of the disclosure, the structure to be processed is thinned to a preset thickness along the direction intersecting with the inclined plane where the multistage step is located, so as to remove a part of the contact plug and the dielectric layer on the surface of the step, obtain a preprocessed sample, and then remove the residual dielectric layer on the step of the preprocessed sample, so as to expose the virtual channel column, thereby obtaining a test sample in which the contact plug 11 and the virtual channel column 12 are simultaneously exposed on the surface of the step. In this way, when a test sample is detected to obtain a detection image, the detection images of the contact plugs 11 and the dummy channel posts 12 can be clearly displayed, so that the position information of the contact plugs 11 and the dummy channel posts 12 can be accurately obtained.
The test sample prepared by the method disclosed by the embodiment of the disclosure can be directly used for SEM detection, can replace TEM detection, and can greatly save sample preparation time and sample preparation cost compared with a TEM sample with complex preparation requirements. In addition, the method for preparing the test sample in the embodiment of the disclosure can prepare a sample in a large area, so that a larger detection area can be obtained in one sample, and the sample preparation quantity is reduced. In addition, according to the test sample prepared according to the embodiment of the disclosure, the SEM is adopted to replace the TEM for detection, so that the use cost of the detection equipment can be reduced, and the cost of failure analysis can be further reduced.
In some embodiments, in the step S110, the step thinning the structure to be processed toward the step along the predetermined direction intersecting the inclined plane where the multi-step is located includes:
under a first current, adopting a focused ion beam process, and carrying out first thinning treatment on the structure to be treated towards the step along a preset direction;
after the structure to be processed is subjected to first thinning treatment for a first preset time, under a second preset current, a focused ion beam process is adopted, and second thinning treatment is carried out towards the step structure to be processed along a preset direction;
wherein the first preset current is greater than the second preset current.
Illustratively, referring to fig. 7, in a predetermined direction perpendicular to the inclined plane of the multi-step (as indicated by the arrow in fig. 7), a first thinning process is performed by using a focused ion beam with a larger current, and the ion beam is thinned to a position close to the step (as indicated by the dashed line a-a' in fig. 7) for a first predetermined time period. Because the surface of the structure to be processed before thinning is far from the A-A', the dielectric layer 13 and the contact plug 11 on the step are thicker, the thinning speed can be accelerated by adopting the focused ion beam with larger current to thin, and the sample preparation efficiency is improved.
After the structure to be processed is thinned to a position close to A-A' of the step, a focused ion beam with smaller current can be adopted to carry out second thinning processing along the direction of the first thinning processing. The position after the second thinning process is further close to the step (the position shown by the broken line B-B' in fig. 7) with respect to the first thinning process. Referring to fig. 8, the contact plug on each step in the structure to be processed after the second thinning process still remains a part, at least a complete bottom.
The second thinning treatment adopts a focused ion beam with smaller current, reduces the thinning rate, can improve the thinning precision, and prevents the over-cutting caused by the over-high thinning speed from completely removing the residual contact plug 11 on the step or ensuring the integrity of the residual contact plug, thereby causing the position information of the contact plug not to be detected and further measuring the deviation of the contact plug relative to the virtual channel column.
In some embodiments, in step S110, the step of thinning the structure to be processed toward the step along a predetermined direction intersecting the inclined plane where the multi-step is located further includes:
detecting a structure to be processed to obtain a first detection image;
when the top surface of the virtual channel column 12 is not exposed in the first detection image, continuously performing second thinning processing on the structure to be processed;
and when the top surface of the virtual channel column 12 is exposed in the first detection image, stopping performing second thinning processing on the structure to be processed.
The dielectric layer 13 includes silicon oxide, and has transparency when the thickness is small, and the transparency is high when the thickness is small. In the second thinning process, when the dielectric layer on the step is thinned to be less than a certain thickness, the top surface of the dummy channel pillar 12 in the first detection image is exposed, and the thinner the dielectric layer 13 is, the clearer the top surface of the dummy channel pillar 12 in the first detection image is.
Illustratively, the detecting the structure to be processed and obtaining the first detection image may include: the structure to be processed is inspected by a focused ion beam microscope to obtain a first inspection image of the thinned surface of the structure to be processed.
When the top surface of the dummy trench pillar 12 is not present in the image, it indicates that the remaining thickness of the dielectric layer 13 is still larger, and may be further thinned. It is emphasized that, in the second thinning process, the contact plugs 11 are observed from time to time, and each contact plug 11 cannot be cut off completely, leaving at least the bottom of the contact plug 11 intact.
When the top surface of the dummy trench pillar 12 appears in the first inspection image, the top surface profile of the dummy trench pillar 12 in the first image can be made clear as much as possible on the premise of ensuring the integrity of the bottom of each contact plug 11, which is beneficial to removing the dielectric layer 13 on the step more quickly in the subsequent steps.
In some embodiments, the process conditions of the first thinning process include: the first voltage range of the focused ion beam process is 5-30 kV, and the first current range is 1-60 nanoamperes;
the processing conditions of the second thinning process include: the second voltage range of the focused ion beam process is 5 kv to 30 kv, and the second current range is 0.1 nanoampere to 15 nanoampere.
In the embodiment of the disclosure, the first current is set to be larger than the second current, so that the first thinning rate is improved, and the thinning efficiency is improved. The smaller second current reduces the rate of the second thinning treatment, so that the second thinning treatment has higher accuracy, and meanwhile, the change of the morphology of each structure in the first detection image is favorably observed.
In some embodiments, in step S120, removing the residual dielectric layer 13 on the surface of the pre-processed sample to expose the dummy trench pillars 12, and forming a test sample, including:
and soaking the pretreatment sample for at least 1 time by using etching liquid to expose the top surface of the virtual channel column 12 to form a test sample.
Referring to fig. 8, after step S110, the step of the obtained preprocessed sample is still covered with a dielectric layer 13 with a certain thickness, and the definition of the top surface contour of the virtual channel pillar 12 detected in the first detection image is low, which cannot meet the requirement of the automatic detection system for measuring the position of the virtual channel pillar 12, and the residual dielectric layer 13 on the step needs to be removed.
For example, the pre-processed sample may be processed with an etching solution that reacts with the dielectric layer 13, for example, the pre-processed sample may be soaked with the etching solution for a certain period of time, and a chemical reaction between the etching solution and the contact plug 11 is an inert reaction, or a reaction rate between the etching solution and the contact plug 11 is smaller than a reaction rate between the etching solution and the dielectric layer 13. In this way, the integrity of the contact plug 11 can be maintained while removing the remaining dielectric layer on the step.
Fig. 9 is a schematic structural diagram of a test sample obtained after removing and processing a dielectric layer remaining on a surface of the structure, and referring to fig. 9, the contact plug 11 and the dummy channel pillar 12 are exposed on a surface of each step of the test sample.
In some embodiments, the immersing the pre-processed sample at least 1 time with the etching solution to expose the top surface of the dummy trench pillar to form the test sample includes:
soaking the pretreatment sample for the nth time by using the etching liquid for a second preset time so as to enable the etching liquid and the preset treatment sample to perform chemical reaction and generate a liquid product and/or a gaseous product; wherein n is a natural number greater than or equal to 1;
separating the pretreated sample soaked for the nth time from the etching solution, and removing the etching solution attached to the surface of the pretreated sample;
detecting the pretreated sample soaked for the nth time to obtain a second detection image;
when the top surface of the virtual channel column 12 is not exposed in the second detection image, soaking the pretreated sample subjected to the nth soaking for a second preset time by using an etching solution for the (n +1) th time;
when the top surfaces of the dummy channel pillars 12 are exposed in the second inspection image, it is determined that the test sample is formed.
Illustratively, the etching solution does not react with the contact plug 11 and the step surface, and can chemically react with the dielectric layer 13 to generate liquid products and/or gaseous products.
For example, the immersion treatment may be performed on the pretreated sample several times, each immersion treatment is maintained for the same duration, and after each immersion treatment, a test is performed to determine whether the step surface exposes the top surface of the dummy trench pillar 12. When the complete top surface of the virtual channel column 12 is exposed in the second detection image, it is indicated that the dielectric layer on the step is completely removed, and the formation of the test sample can be determined.
It should be noted that, each soaking process performed on the pre-processed sample further includes: and (4) washing and drying the pretreated sample after the soaking treatment. The pretreatment sample can be flushed to remove the etching solution attached to the surface of the pretreatment sample, and then the pretreatment sample is sprayed with air to remove the moisture on the surface of the pretreatment sample.
The adopted etching liquid reacts with the medium layer to generate a liquid product and/or a gaseous product, so that the product is easy to separate and discharge, and the generated solid product is prevented from being attached to the surface of the sample to influence detection.
In the embodiment of the disclosure, the immersion treatment is performed on the preprocessed sample for multiple times, so that on one hand, the time when the virtual channel column is exposed on the surface of the step can be accurately grasped, and the waste of time for continuing immersing the sample after the dielectric layer is completely removed is favorably reduced. On the other hand, when the composition material of the virtual channel column comprises the same material as the dielectric layer or the material of the virtual channel column can react with the etching solution, the top surface of the virtual channel column is prevented from being etched to influence the subsequent image detection by soaking for multiple times and controlling the time of each soaking.
In some embodiments, the second preset duration ranges from: 5s to 15 s.
For example, the second preset duration may be set according to a reaction rate of the etching solution and the dielectric layer. When the reaction rate of the etching solution and the dielectric layer is faster, the second preset time period may be set to a smaller value, for example, 5 s. When the reaction rate of the etching solution and the dielectric layer is slow, the second preset time period may be set to a large value, for example, 15 s.
In some embodiments, the etching liquid includes: hydrofluoric acid (HF) or Buffered Oxide Etch (BOE).
Illustratively, the material of the dielectric layer 13 includes silicon oxide, and the product generated by chemical reaction with the dielectric layer is in a gas state and a liquid state and is easily separated from the sample by using hydrofluoric acid or buffered oxide etching solution.
In some embodiments, the structure to be processed includes two sidewalls oppositely disposed, and the contact plug is located in the dielectric layer between the two sidewalls, and the method further includes:
thinning at least one side wall until the side face of the multistage step is exposed;
locating a target range including a failure region;
the step thinning structure to be processed along the preset direction intersecting with the inclined plane where the multistage steps are located so as to form a pre-processed sample with a preset thickness, comprises:
and thinning the target range towards the steps along a preset direction intersected with the inclined plane where the multistage steps are located so as to form a pretreatment sample.
Illustratively, referring to fig. 10, the structure to be processed is surrounded by a thicker dielectric layer 13, the structure to be processed includes two sidewalls 13a and 13b disposed oppositely, and the contact plug 11 is located in the dielectric layer 13 between the two sidewalls 13a and 13 b. Note that the side surface of the multistage step is parallel to the two side walls 13a and 13b of the structure to be processed, and the direction in which the multistage step ascends or descends can be observed through the side surface of the multistage step. Because the side wall of the structure to be processed is covered with the thicker dielectric layer, the side surface of the step structure is not exposed on the side wall. At least one of the side walls is thinned, for example, the side wall 13a and/or the side wall 13b is thinned until the side surface of the multi-step is exposed, and further, a target range where the failure region is located is found according to the side surface structure of the step and the number of the contact plugs on the step.
After the target range in which the failure region is located is determined, the target range in the structure to be processed may be processed by the method illustrated in fig. 7 to 9, so as to obtain a test sample including the target range. Therefore, the processing of the structure to be processed in a large range can be avoided, and the preparation time of the test sample is saved.
The embodiment of the disclosure also provides a test sample prepared by the method of any one of the embodiments.
Illustratively, referring to fig. 9, the test sample includes: the structure comprises a multi-stage step, a contact plug 11 positioned above the upper surface of the step and a virtual channel column 12 penetrating through the step; wherein the top surface of the dummy channel pillar 12 is exposed on the upper surface of the step.
In some embodiments, the top surface of the dummy trench pillar 12 may also protrude above the step upper surface, in the dielectric layer 13 at the step upper surface. Illustratively, the material of the dummy trench pillar 12 may be the same as that of the dielectric layer 13, and during the process of thinning the removed dielectric layer 13, the portion of the dummy trench pillar 12 located in the removed dielectric layer is also removed.
It should be noted that, in the sample preparation process, the sample is thinned along the preset direction forming a certain included angle with the inclined plane where the multistage step is located, so that the top surface of the contact plug 11 in the test sample is not parallel to the upper surface of the step, but in the planar detection image, the observation and detection of the position of the contact plug 11 are not affected.
A method for automatically measuring the position deviation of a contact plug with respect to a dummy channel pillar, which may be performed by an automatic measurement system, according to a test sample provided in an embodiment of the present disclosure is described below with reference to fig. 11a to 11 c.
Fig. 11 shows a schematic view of a part of the surface of a test specimen, which, with reference to fig. 11a, comprises: a first dummy channel pillar 31, a second dummy channel pillar 32, and a contact plug 30. Each contact plug 30 has two first dummy channel pillars 31 and two second dummy channel pillars 32 around it, and is arranged in a central symmetrical manner.
The method comprises the following steps: an electronic scan picture of the surface of the test sample is taken (as shown schematically in figure 11 a).
Illustratively, an electron scan picture is taken by a camera system under an electron beam scan at a voltage of 20kV and a current of 0.2 nA.
Step two: the automatic metrology system obtains the profile and center of the first dummy trench pillar 31, the second dummy trench pillar 32, and the contact plug 30 based on the electronic scan image obtained in step one.
Referring to fig. 11b (fig. 11b is a portion of fig. 11a, which is taken through region R), the center of contact plug 30 is o, and the centers of first dummy channel pillar 31 and second dummy channel pillar 32 are o1、o2。
Step three: with the center o of the contact plug 30 as the origin, an xoy coordinate system as shown in fig. 11b is established in the plane of the electronic scan picture. Determining the center o of the contact plug 30 to the center o of the first dummy channel pillar 311Vector oo formed by the connecting lines of (1)1Component ox on the x-axis1And the center o of the contact plug 30 to the center o of the second dummy channel pillar 322Vector oo formed by the connecting lines of (1)2Component on the y-axis of the vector oy1。
Step four: referring to fig. 11c, fig. 11c shows the theoretical design position of the contact plug 30, and also establishes an x 'o' y 'coordinate system with the theoretical design position center of the contact plug 30 as an origin o'. Determining the theoretical design center o' of the contact plug 30 to the center o of the first dummy channel pillar 311Is connected to form a vector o' o1Component o 'x on the x' axis0And the theoretical design center o' of the contact plug 30 to the center o of the second dummy trench pillar 322Is connected to form a vector o' o2Component o 'y on the y' axis0。
Step five: will divide the vector ox1And component o' x0By comparison, it is found that the actual position center o of the contact plug 30 is relative to the center o of the first dummy channel post 311The amount of deviation in the x-direction; will divide the vector oy1And component o' y0By comparison, the actual position center o of the contact plug 30 with respect to the center o of the second dummy channel pillar 32 is found2The amount of deviation in the y-direction.
For example, the position of the mask for forming the contact plug 30 may be corrected according to the deviation of the actual position center of the contact plug 30 from the centers of the first dummy channel post 31 and the second dummy channel post 32, thereby adjusting the formation position of the contact plug 30.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A method of preparing a test sample, comprising:
providing a structure to be processed comprising a failure region; wherein the structure to be processed comprises: the multi-stage step comprises a dielectric layer covering the step, a contact plug positioned above the surface of the step and arranged in the dielectric layer, and a virtual channel column penetrating through the step;
thinning the structure to be processed towards the steps along a preset direction intersecting with the inclined plane where the multistage steps are located to form a preprocessed sample; wherein the pre-treated sample comprises the failure zone; along the preset direction, the thickness of the contact plug remained on the surface of the pretreated sample is greater than or equal to a first preset thickness;
removing the dielectric layer remained on the surface of the pretreatment sample to expose the virtual channel column to form the test sample; wherein the test sample reveals at least a portion of the remaining contact plug.
2. The method according to claim 1, wherein the thinning the structure to be processed toward the step along a predetermined direction intersecting with the inclined plane on which the multistage step is located comprises:
under a first current, adopting a focused ion beam process to perform first thinning treatment on the structure to be treated towards the step along the preset direction;
after the structure to be processed is subjected to the first thinning treatment for a first preset time, under a second current, a focused ion beam process is adopted, and the structure to be processed is subjected to second thinning treatment towards the step along the preset direction;
wherein the first current is greater than the second current.
3. The method according to claim 2, wherein thinning the structure to be processed toward the step along a predetermined direction intersecting the slope on which the multistage step is located, further comprises:
detecting the structure to be processed to obtain a first detection image;
when the top surface of the virtual channel column is not exposed in the first detection image, continuing to perform the second thinning treatment on the structure to be processed;
and when the top surface of the virtual channel column is exposed in the first detection image, stopping performing the second thinning treatment on the structure to be processed.
4. The method of claim 2,
the processing conditions of the first thinning processing include: the first voltage range of the focused ion beam process is 5-30 kV, and the first current range is 1-60 nanoamperes;
the processing conditions of the second thinning processing include: the second voltage range of the focused ion beam process is 5 kilovolts to 30 kilovolts, and the second current range is 0.1 nanoamperes to 15 nanoamperes.
5. The method of claim 1, wherein the removing the dielectric layer remaining on the surface of the pre-processed sample to expose the dummy trench pillar to form the test sample comprises:
and soaking the pretreatment sample for at least 1 time by adopting etching liquid to expose the top surface of the virtual channel column to form the test sample.
6. The method of claim 5,
the dipping of the pretreatment sample for at least 1 time by using the etching solution to expose the top surface of the virtual channel column to form the test sample comprises:
soaking the pretreatment sample for the nth time by using the etching liquid for a second preset time so as to enable the etching liquid and the pretreatment sample to generate a chemical reaction and generate a liquid product and/or a gaseous product; wherein n is a natural number greater than or equal to 1;
separating the pretreated sample soaked for the nth time from the etching solution, and removing the etching solution attached to the surface of the pretreated sample;
detecting the pretreated sample soaked for the nth time to obtain a second detection image;
when the top surface of the virtual channel column is not exposed in the second detection image, soaking the pretreated sample subjected to the nth soaking for the second preset time by using the etching liquid for the (n +1) th time;
determining that the test sample is formed when the top surfaces of the dummy channel pillars are exposed in the second inspection image.
7. The method of claim 6, wherein the second predetermined period of time ranges from 5s to 15 s.
8. The method according to any one of claims 5 to 7, wherein the etching liquid comprises: hydrofluoric acid or buffered oxide etch solutions.
9. The method of claim 1, wherein the structure to be processed comprises two sidewalls disposed opposite to each other, and the contact plug is located in a dielectric layer between the two sidewalls, the method further comprising:
thinning at least one side wall until the side face of the multistage step is exposed;
locating a target range including the failure region;
along crossing in the preset direction on multistage step place inclined plane, orientation the step attenuate pending structure to form the preliminary treatment sample that has preset thickness, include:
and thinning the target range towards the steps along a preset direction intersecting with the inclined plane where the multistage steps are located so as to form the pretreatment sample.
10. A test sample prepared by the method of any one of claims 1 to 9.
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