CN113437110A - Phase change memory system and method of manufacturing the same - Google Patents

Phase change memory system and method of manufacturing the same Download PDF

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CN113437110A
CN113437110A CN202110637570.1A CN202110637570A CN113437110A CN 113437110 A CN113437110 A CN 113437110A CN 202110637570 A CN202110637570 A CN 202110637570A CN 113437110 A CN113437110 A CN 113437110A
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circuit
array
phase change
forming
change memory
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CN113437110B (en
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刘峻
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Yangtze River Advanced Storage Industry Innovation Center Co Ltd
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Yangtze River Advanced Storage Industry Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The embodiment of the invention provides a phase change memory system and a manufacturing method thereof. Wherein the phase change memory system comprises: a first semiconductor structure comprising at least a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry; a second semiconductor structure including at least an array of phase change memory cells and another portion of the array access circuitry arranged in a stack, and a second bonding layer including a second conductive contact; a bonding layer between the first semiconductor structure and the second semiconductor structure; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.

Description

Phase change memory system and method of manufacturing the same
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a phase change memory system and a method for manufacturing the same.
Background
Phase Change Memory (PCM) in a Phase Change Memory system is a Memory technology using chalcogenide as a Memory medium, and uses the difference in resistance of materials in different states to store data. The phase change memory has the advantages of being addressable by bits, not losing data after power failure, high storage density, high read-write speed and the like, and is considered to be the most promising next-generation memory.
However, various challenges also exist with phase change memory systems in the related art.
Disclosure of Invention
To solve the related technical problems, embodiments of the present invention provide a phase change memory system and a method for manufacturing the same.
An embodiment of the present invention provides a phase change memory system, including:
a first semiconductor structure comprising at least a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry;
a second semiconductor structure including at least an array of phase change memory cells and another portion of the array access circuitry arranged in a stack, and a second bonding layer including a second conductive contact;
a bonding layer between the first semiconductor structure and the second semiconductor structure; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.
In the above solution, the first semiconductor structure includes a memory controller, a peripheral circuit, a data transmission path, an input/output circuit, and a first bonding layer including a first conductive contact; the memory controller at least comprises a processor and an error correction ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory;
the second semiconductor structure comprises a phase change memory cell array and array access circuitry and a second bonding layer comprising a second conductive contact; wherein the array access circuit includes at least an address line driver, an address line decoder, and a page buffer.
In the above aspect, the second semiconductor structure includes:
a second substrate;
the array access circuitry located on the second substrate;
the array of phase change memory cells on the array access circuit;
the second bonding layer located on the array of phase change memory cells;
the first semiconductor structure includes:
the first bonding layer on the second bonding layer;
the memory controller, the peripheral circuit, the data transmission path and the input and output circuit are positioned on the first bonding layer;
a first substrate on the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit.
In the above scheme, the array access circuit includes a first sub-array access circuit and a second sub-array access circuit;
the first semiconductor structure comprises a memory controller, a first subarray access circuit, a data transmission path, an input output circuit and a first bonding layer comprising a first conductive contact; wherein, the memory controller at least comprises a processor and an ECC circuit; the first sub-array access circuit comprises at least a page buffer;
the second semiconductor structure comprises a phase change memory cell array, a peripheral circuit, a second subarray access circuit and a second bonding layer containing a second conductive contact; wherein, the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the second sub-array access circuit includes at least an address line driver and an address line decoder.
In the above aspect, the second semiconductor structure includes:
a second substrate;
peripheral circuitry and second sub-array access circuitry located on the second substrate;
an array of phase change memory cells on the peripheral circuit and the second subarray access circuit;
the second bonding layer located on the array of phase change memory cells;
the first semiconductor structure includes:
the first bonding layer on the second bonding layer;
the memory controller, the first subarray access circuit, the data transmission path and the input and output circuit are positioned on the first bonding layer;
a first substrate on the memory controller, the first sub-array access circuits, the data transmission paths, and the input-output circuits.
In the above scheme, the array access circuit includes a first sub-array access circuit and a second sub-array access circuit;
the first semiconductor structure comprises a memory controller, a peripheral circuit, a first subarray access circuit, a data transmission path, an input-output circuit and a first bonding layer comprising a first conductive contact; wherein, the memory controller at least comprises a processor and an ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the first sub-array access circuit includes at least a page buffer;
the second semiconductor structure comprises a phase change memory cell array and a second sub-array access circuit and a second bonding layer comprising a second conductive contact; wherein the second sub-array access circuit includes at least an address line driver and an address line decoder.
In the above aspect, the second semiconductor structure includes:
a second substrate;
the second sub-array access circuit located on the second substrate;
the array of phase change memory cells on the second subarray access circuit;
the second bonding layer located on the array of phase change memory cells;
the first semiconductor structure includes:
the first bonding layer on the second bonding layer;
the memory controller, the peripheral circuit, the first sub-array access circuit, the data transmission path and the input and output circuit are positioned on the first bonding layer;
a first substrate on the memory controller, the peripheral circuitry, the first sub-array access circuitry, the data transmission paths, and the input-output circuitry.
In the above solution, the phase change memory system further includes an electrical lead-out structure on the first substrate; the phase change memory system is connected with an external device through the electric leading-out structure;
the electrical lead-out structure includes: a via in the first substrate; a conductive plunger in the through hole; a rewiring layer on the first substrate; and a bonding pad on the redistribution layer.
Another aspect of the embodiments of the present invention provides a method for manufacturing a phase change memory system, including:
forming a first semiconductor structure; the first semiconductor structure at least comprises a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry;
forming a second semiconductor structure; the second semiconductor structure at least comprises a phase change memory cell array and another part of array access circuit which are arranged in a stacking mode, and a second bonding layer containing a second conductive contact;
bonding the first bonding layer and the second bonding layer to form a bonding layer; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.
In the foregoing scheme, the forming the first semiconductor structure includes:
providing a first substrate;
forming the memory controller, a peripheral circuit, a data transmission path, and an input-output circuit over the first substrate; wherein, the memory controller at least comprises a processor and an ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory;
forming the first bonding layer on the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit;
the forming a second semiconductor structure includes:
providing a second substrate;
forming array access circuitry on the second substrate; wherein the array access circuit comprises at least an address line driver, an address line decoder, and a page buffer;
forming an array of phase change memory cells of the phase change memory system on the array access circuitry;
forming the second bonding layer on the array of phase change memory cells.
In the above scheme, the method further comprises:
forming a first interconnection layer on the memory controller, the peripheral circuits, the data transmission path, and the input-output circuit after forming the memory controller, the peripheral circuits, the data transmission path, and the input-output circuit on the first substrate;
the forming the first bonding layer on the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit includes:
forming the first bonding layer on the first interconnection layer to connect the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit with the first conductive contact through the first interconnection layer;
the method further comprises the following steps:
forming a second interconnect layer on the array of phase change memory cells after forming the array of phase change memory cells of the phase change memory system on the array access circuitry;
the forming the second bonding layer on the array of phase change memory cells includes:
forming the second bonding layer on the second interconnect layer to connect the array of phase change memory cells forming the phase change memory system on the array access circuitry with the second conductive contact through the second interconnect layer.
In the above scheme, the array access circuit includes a first sub-array access circuit and a second sub-array access circuit;
the forming a first semiconductor structure includes:
providing a first substrate;
forming the memory controller, a first sub-array access circuit, a data transmission path, and an input-output circuit on the first substrate; wherein, the memory controller at least comprises a processor and an ECC circuit; the first sub-array access circuit includes at least a page buffer; forming the first bonding layer on the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit;
the forming a second semiconductor structure includes:
providing a second substrate;
forming a peripheral circuit and a second sub-array access circuit of the phase change memory system on the second substrate; wherein, the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the second sub-array access circuit comprises at least an address line driver and an address line decoder;
forming a phase change memory cell array of the phase change memory system on the peripheral circuit and the second sub-array access circuit;
forming the second bonding layer on the array of phase change memory cells.
In the above scheme, the method further comprises:
after forming the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit on the first substrate, forming a first interconnection layer on the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit;
the forming the first bonding layer on the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit includes:
forming the first bonding layer on the first interconnect layer to connect the memory controller, the first sub-array access circuits, the data transmission paths, and the input-output circuits with the first conductive contacts through the first interconnect layer;
the method further comprises the following steps:
forming a second interconnect layer on the phase change memory cell array after forming the phase change memory cell array of the phase change memory system on the peripheral circuit and a second sub-array access circuit;
the forming the second bonding layer on the array of phase change memory cells includes:
forming the second bonding layer on the second interconnect layer such that an array of phase change memory cells forming the phase change memory system on the peripheral circuitry and second sub-array access circuitry are connected with the second conductive contact through the second interconnect layer.
In the above scheme, the array access circuit includes a first sub-array access circuit and a second sub-array access circuit;
the forming a first semiconductor structure includes:
providing a first substrate;
forming the memory controller, peripheral circuits, a first sub-array access circuit, data transmission paths, and input-output circuits on the first substrate; wherein, the memory controller at least comprises a processor and an ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the first sub-array access circuit includes at least a page buffer;
forming the first bonding layer on the memory controller, peripheral circuitry, first sub-array access circuitry, data transmission paths, and input-output circuitry;
the forming a second semiconductor structure includes:
providing a second substrate;
forming a second sub-array access circuit on the second substrate; wherein the second sub-array access circuit comprises at least an address line driver and an address line decoder;
forming an array of phase change memory cells of the phase change memory system on the second sub-array access circuit;
forming the second bonding layer on the array of phase change memory cells.
In the above scheme, the method further comprises:
after forming the memory controller, peripheral circuits, the first sub-array access circuits, data transmission paths, and input-output circuits on the first substrate, forming a first interconnect layer on the memory controller, peripheral circuits, the first sub-array access circuits, data transmission paths, and input-output circuits;
the forming the first bonding layer on the memory controller, the peripheral circuitry, the first sub-array access circuitry, the data transmission path, and the input-output circuitry includes:
forming the first bonding layer on the first interconnect layer to connect the memory controller, peripheral circuitry, first sub-array access circuitry, data transmission paths, and input-output circuitry with the first conductive contacts through the first interconnect layer;
the method further comprises the following steps:
forming a second interconnect layer on the phase change memory cell array of the phase change memory system after forming the phase change memory cell array on the second sub-array access circuit;
the forming the second bonding layer on the array of phase change memory cells includes:
forming the second bonding layer on the second interconnect layer such that the array of phase change memory cells forming the phase change memory system on the second sub-array access circuit is connected with the second conductive contact through the second interconnect layer.
In the above-described aspect, after the bonding layer is formed,
the first semiconductor structure is formed over the second semiconductor structure.
In the above scheme, the method further comprises:
forming an electrical extraction structure on the first substrate; the phase change memory system is connected with an external device through the electric leading-out structure;
the forming of the electrical lead-out structure includes:
forming a via in the first substrate;
filling a conductive material in the through hole to form a conductive plunger;
forming a rewiring layer on the first substrate;
and forming a welding pad on the rewiring layer.
The embodiment of the invention provides a phase change memory system and a manufacturing method thereof, wherein the phase change memory system comprises: a first semiconductor structure comprising at least a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry; a second semiconductor structure including at least an array of phase change memory cells and another portion of the array access circuitry arranged in a stack, and a second bonding layer including a second conductive contact; a bonding layer between the first semiconductor structure and the second semiconductor structure; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat. In the phase change memory system provided by the embodiment of the invention, a first semiconductor structure containing a peripheral device and a second semiconductor structure containing a phase change memory cell array and at least part of an array access circuit are combined together through a bonding combination layer; in this way, the usable area of the peripheral device can be increased under the condition that the area of the substrate used for forming the phase change memory system is unchanged or reduced, and the usable area of the peripheral device can be increased to better meet the requirements of the next generation chip size and circuit complexity.
Drawings
Fig. 1 is a schematic diagram of a phase change memory cell array of a phase change memory system observed by a scanning electron microscope provided in the related art;
FIG. 2 is a partial three-dimensional schematic diagram of a phase-change memory system having a layer of memory cells provided in the related art;
fig. 3 is a schematic diagram of a layout of an array access circuit of a phase change memory system provided in the related art;
fig. 4 is a schematic diagram illustrating a structure of a phase change memory system provided in the related art;
fig. 5 is a schematic cross-sectional view of a phase change memory system according to an embodiment of the present invention;
FIG. 6a is a schematic diagram illustrating a partial cross-sectional view of a phase-change memory cell array of a phase-change memory system having a first bonding structure according to an embodiment of the present invention;
FIG. 6b is a cross-sectional view of a first phase-change memory system with a first bonding structure according to an embodiment of the present invention;
FIG. 6c is a cross-sectional view of a second phase-change memory system with a first bonding structure according to an embodiment of the present invention;
FIG. 7a is a schematic diagram illustrating a partial cross-sectional view of a phase-change memory cell array of a phase-change memory system having a second bonding structure according to an embodiment of the present invention;
FIG. 7b is a cross-sectional view of a first phase-change memory system with a second bonding structure according to an embodiment of the present invention;
FIG. 7c is a cross-sectional view of a second phase-change memory system with a second bonding structure according to an embodiment of the present invention;
FIG. 8a is a schematic diagram illustrating a partial cross-sectional view of a phase change memory cell array of a phase change memory system having a third bonding structure according to an embodiment of the present invention;
FIG. 8b is a cross-sectional view of a first phase-change memory system with a third bonding structure according to an embodiment of the present invention;
FIG. 8c is a cross-sectional view of a second phase-change memory system with a third bonding structure according to an embodiment of the present invention;
fig. 9 is a schematic diagram of device layouts in a first semiconductor structure and a second semiconductor structure of a phase change memory system according to an embodiment of the present invention;
FIG. 10 is a flowchart illustrating a method for manufacturing a phase change memory system according to an embodiment of the present invention;
FIGS. 11a-11e are schematic diagrams illustrating a manufacturing method of a phase-change memory system having a first bonding structure according to an embodiment of the present invention;
FIGS. 12a-12e are schematic diagrams illustrating a method for manufacturing a phase-change memory system having a second bonding structure according to an embodiment of the present invention;
fig. 13a to 13e are schematic diagrams illustrating an implementation process of a manufacturing method of a phase change memory system having a third bonding structure according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
In practical applications, the phase change memory system may include a phase change memory cell array, an array access circuit, a peripheral circuit, a memory controller, and the like; wherein the phase change memory cell array, array access circuitry, and peripheral circuitry may be integrated on the same die as the memory controller, which allows for a wider bus and higher operating speed. In practice, the stacked phase change memory cell array and array access circuit may be formed in different areas on the same plane in parallel with the peripheral circuits and the memory controller. A phase change memory system, alternatively referred to as a phase change memory device, includes an array of phase change memory cells, array access circuitry, and peripheral circuitry.
It should be noted that, in the phase change memory cell array, the array access circuit, the peripheral circuit, and the memory controller formed in different regions on the same plane, the substrate area occupied by the phase change memory cell array is much larger than the substrate area occupied by the array access circuit, the peripheral circuit, and the memory controller.
In some embodiments, the stacked phase change memory cell array and array access circuit in a phase change memory system occupy 90% of the area of the substrate, while the peripheral circuit occupies 10% of the area of the substrate.
Here, the phase change memory cell array is mainly used to store data. Referring to fig. 1, fig. 1 is a partial cross-sectional view of a phase change memory cell array in the related art observed through a scanning electron microscope.
In some embodiments, the architecture of the phase change memory cell array may include phase change memory cells having a one-layer phase change memory cell, phase change memory cells having a two-layer stack, phase change memory cells having a four-layer stack, and the like.
Illustratively, as shown in FIG. 2, an architecture having a layer of phase change memory cells comprises: a bit line layer (including a plurality of bit lines), a phase change memory cell layer, and a word line layer (including a plurality of word lines); each phase change memory cell 20 in the phase change memory cell layer may include a stacked PCM element 202, a gate element 204, and a plurality of electrodes 201, 203, and 205. Heating or quenching of the phase change memory element 202 by the electrode is achieved by conduction of the gating element 204 to achieve switching between the crystalline and amorphous states of the PCM element 202; the storage of data is achieved by switching between the crystalline and amorphous states of the PCM element 202. Here, the bit line layer, the phase change memory cell layer, and the word line layer are generally formed of a constant line width (L/S) of 20nm/20nm formed after the patterning process.
In practice, the material of the PCM element comprises a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the material of the gating element may comprise any suitable gating element material, such as ZnxTey、GexTey、NbxOy、SixAsyTezEtc.; the material of the electrode may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicideOr any combination thereof. In some embodiments, the material of the electrodes comprises carbon, such as amorphous carbon.
It is understood that an architecture with multiple layers of phase change memory cells may be simply understood as a stack of architectures with one layer of phase change memory cells.
In some phase change memory systems, the connections (which may be expressed as contacts) for connecting the word, bit lines and word bit line drivers are all disposed at intermediate locations between the corresponding word and bit lines, and these connections are typically disposed vertically between the word, bit lines and word bit line drivers. Based on this, word and bit line decoders are generally disposed in mutually perpendicular stripe regions as shown in fig. 3, and word and bit lines cannot be disposed above these stripe regions, i.e., memory cells for data storage cannot be provided. Since the phase change memory system is made up of many small memory array blocks (the location occupied by the two dashed boxes in fig. 3 is one memory whole column block), the areas for setting the word and bit line decoders occupy a large portion of the substrate area, reducing array efficiency without merging memory cells in these areas. In the case of a memory cell comprising a plurality of stacks, the available substrate area under the memory cell array can only be used to provide simple array access circuitry in addition to the word and bit decoders, since the word and bit decoder circuits occupy a large substrate area. There may not be sufficient substrate area to enable complex array access circuitry. Especially when more stacked memory cells are integrated into a single memory, more array access circuitry and peripheral circuitry are required to implement the memory function, making the available substrate area for peripheral circuitry and memory controllers, etc. a bottleneck for technology expansion.
That is, in practical applications, on one hand, as the functional requirements increase, peripheral circuits and memory controllers in the phase change memory system become more and more complex and occupy more and more substrate areas; therefore, it is necessary to increase the substrate utilization area of the corresponding peripheral circuits and memory controller. On the other hand, when more and more layers of stacked memory cells are included in the phase change memory system, more array access circuits and peripheral circuits are needed to realize the functions of the phase change memory system; therefore, it is necessary to increase the substrate utilization area of the array access circuit.
Based on this, the embodiment of the invention provides a phase change memory system. Fig. 4 is a schematic structural diagram of a phase change memory system 400 according to an embodiment of the present invention. As shown in fig. 4, the phase change memory system 400 includes:
a first semiconductor structure 401, the first semiconductor structure 401 comprising at least a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry;
a second semiconductor structure 402, the second semiconductor structure 402 including at least an array of phase change memory cells and another portion of array access circuitry arranged in a stack, and a second bonding layer including a second conductive contact;
a bonding layer 403 between the first semiconductor structure 401 and the second semiconductor structure 402; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.
Here, the first semiconductor structure 401 includes at least peripheral devices; the peripheral device includes peripheral circuitry and/or a portion of array access circuitry.
In practice, the peripheral devices include circuits other than the phase change memory cell array, such as peripheral circuits, array access circuits, and the like. The peripheral circuit may include a voltage generator, a current generator, a Random Access Memory (RAM), a Read-Only Memory (ROM), a fuse protection circuit, a control logic, a data buffer, and the like; under the action of the control logic, the peripheral circuit can perform data interaction with an external device through the data buffer.
The array access circuit can be understood as a corresponding circuit closely related to the phase change memory cell array, such as a driver, a decoder, a read circuit, a write circuit, etc., when the control logic receives a read/write operation command and address data, the decoder can apply a corresponding voltage generated from the driver to a corresponding address line based on the decoded address under the action of the control logic, so as to realize the read/write of the data.
Note that when a part of the array access circuit is included in the first semiconductor structure 401, another part of the array access circuit other than the part of the array access circuit included in the first semiconductor structure 401 is included in the second semiconductor structure 402.
It is to be understood that, in order to achieve bonding of the two semiconductor structures, a first bonding layer is further provided in the first semiconductor structure 401, and a second bonding layer is further provided in the second semiconductor structure 402. The first bonding layer may include: the first dielectric layer, a plurality of first trenches penetrating the first dielectric layer, and first conductive contacts located in the first trenches. The second bonding layer may include: the second dielectric layer, the second groove which penetrates through the second dielectric layer, and the second conductive contact which is positioned in the second groove. Here, the topography of the corresponding structures in the first bonding layer and the second bonding layer may be the same or different, and specifically, the width of the first conductive contact (here, the width of the diameter may be understood as the width of the cross section in the width direction of the first trench) and the width of the second conductive contact may be the same or different. In practical application, the cross sections of the first groove and the second groove can be circular, oval or long-strip-shaped; the materials of the first dielectric layer and the second dielectric layer include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof; the material of the first and second conductive contacts may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.
Here, the bonding interface between the first bonding layer and the second bonding layer presents both a metal (conductive contact) and a bonding of a dielectric substance. In some specific embodiments, the first conductive contact and the second conductive contact are conductively connected by way of contact; when the materials of the first dielectric layer and the second dielectric layer both comprise silicon oxide, the first dielectric layer and the second dielectric layer are combined together by forming Si-O-Si bonds through Si-OH bonds on the surfaces of the first dielectric layer and the second dielectric layer. The bonding layer formed by bonding the first dielectric layer and the second dielectric layer is a bonding layer.
It is understood that the area of the first plane of the first semiconductor structure may be the same as or different from the area of the first plane of the second semiconductor structure. In the process of forming, in order to facilitate better bonding of the first semiconductor structure and the second semiconductor structure, the area of the first semiconductor structure in a first plane is formed to be the same as the area of the second semiconductor structure in the first plane, wherein the first plane is parallel to the surface of the substrate forming the phase change memory system.
Thus, as shown in fig. 5, by bonding the first semiconductor structure 401 and the second semiconductor structure 402 together by the bonding layer 403, the phase-change memory system 400 can be formed to provide a larger usable area for peripheral circuits and array access circuits, thereby improving the memory efficiency of the phase-change memory cell array.
In practical applications, the first semiconductor structure 401 may be disposed above the second semiconductor structure 402, or disposed below the second semiconductor structure 402.
It should be noted that, in each embodiment of the present invention, the forming positions of the peripheral circuit and the array access circuit may be reasonably adjusted according to the substrate areas occupied by the peripheral circuit and the array access circuit. That is, the bonding of the first semiconductor structure 401 and the second semiconductor structure 402 through the bonding layer 403 to form different bonding structures can be achieved through various blending methods, three of which are described in detail below.
First, a first bonding structure is described:
in some embodiments, as shown in fig. 6a, the first semiconductor structure 401 includes a memory controller 4012, a peripheral circuit 4013, a data transmission path 4014, an Input/Output (I/O) circuit 4015, and a first bonding layer 4016 including a first conductive contact; the memory controller 4012 at least includes a processor and an Error Checking and Correction ECC (english can be expressed as Error Checking and Correction) circuit; the peripheral circuit 4013 at least comprises a voltage generator, a RAM and a ROM;
the second semiconductor structure 402 includes a phase change memory cell array 4023, an array access circuit 4022, and a second bonding layer 4024 including a second conductive contact; the array access circuit 4022 includes at least an address line driver, an address line decoder, and a page buffer.
In practical applications, the memory controller 4012 may comprise an overall control device for controlling the phase change memory system 400 to perform various operations such as read operation, write operation, erase operation, etc. For example, a Central Processing Unit (CPU), an ECC circuit that can implement error correction, and other elements mainly related to logic operations.
In practical applications, as shown in fig. 6a, when the phase change memory system 400 includes a smaller number of stacked memory cell layers, the array access circuit 4022 included in the phase change memory system also occupies a smaller substrate area, and at this time, the entire array access circuit 4022 and the phase change memory cell array 4023 may be disposed in the second semiconductor structure 402. Meanwhile, a memory controller 4012, a peripheral circuit 4013, a data transmission path 4014, and an I/O circuit 4015 are provided in the first semiconductor structure 401.
Thus, compared with the related art in which the memory controller, the peripheral circuit, the data transmission path, the I/O circuit, the array access circuit, and the phase-change memory cell array are disposed in one semiconductor structure, the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014, and the I/O circuit 4015 in the embodiment of the present invention are disposed in a semiconductor structure different from the phase-change memory cell array 4023, which can save the substrate area for forming the corresponding semiconductor structure devices (reduce the substrate area occupied by the peripheral circuit 4013, the data transmission path 4014, and the I/O circuit 4015 before); in addition, a larger usable substrate area is provided for the formation of the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014 and the I/O circuit 4015 (the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014 and the I/O circuit 4015 can share the same substrate area as the phase change memory cell array 4023), and more complex circuits can be realized in the phase change memory system.
In practical applications, as shown in fig. 6b, the first semiconductor structure 401 may be disposed above the second semiconductor structure 402.
Based thereon, in some embodiments, the second semiconductor structure 402 includes:
a second substrate 4021;
the array access circuitry 4022 located on the second substrate 4021;
the phase change memory cell array 4023 located on the array access circuit 4022;
the second bonding layer 4024 located on the phase change memory cell array 4023;
the first semiconductor structure 401 includes:
the first bonding layer 4016 on the second bonding layer 4024;
the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014, and the I/O circuit 4015 are located on the first bonding layer 4016;
a first substrate 4011 on the memory controller 4012, the peripheral circuits 4013, the data transmission path 4014, and the I/O circuit 4015.
Illustratively, as shown in fig. 6b, the second semiconductor structure 402 includes: a second substrate 4021, an array access circuit 4022, a phase change memory cell array 4023, and a second bonding layer 4024; the material of the second substrate 4021 includes, but is not limited to, silicon, and in practical applications, the second substrate 4021 may be doped according to practical requirements. The first semiconductor structure 401 includes: a first substrate 4011, a memory controller 4012, a peripheral circuit 4013, a data transfer path 4014, an I/O circuit 4015, and a first bonding layer 4016; the material of the first substrate 4011 includes, but is not limited to, silicon.
In practical applications, the first semiconductor structure 401 may also be disposed below the second semiconductor structure 402.
Based on this, in some embodiments, as shown in figure 6c,
the first semiconductor structure 401 includes:
a first substrate 4011;
the memory controller 4012, a peripheral circuit 4013, a data transfer path 4014, and an I/O circuit 4015 over the first substrate 4011;
the first bonding layer 4016 is located on the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014, and the I/O circuit 4015;
the second semiconductor structure 402 includes:
the second bonding layer 4024 on the first bonding layer 4016;
the phase change memory cell array 4023 on the second bonding layer 4024;
the array access circuit 4022 located on the phase change memory cell array 4023;
a second substrate 4021 located on the array access circuitry 4022.
Here, the first semiconductor structure 401 and the second semiconductor structure 402 are formed the same as the first semiconductor structure 401 and the second semiconductor structure 402 in the foregoing embodiment, and are not described again here.
It is understood that when the first semiconductor structure 401 is disposed above the second semiconductor structure 402, the I/O circuit is disposed on the top side of the first semiconductor structure 401, i.e., the side away from the second semiconductor structure 402, so as to facilitate the leading-out of the electrical connection structure.
It is understood that compared to some embodiments described above, in which the stacked phase change memory cell array and array access circuit occupy 90% of the area of the substrate, and the peripheral circuit occupies 10% of the area of the substrate, when the memory cell array and the array access circuit continue to use 90% of the substrate area as described above in the first bonding configuration, the entire phase change memory system eventually occupies 90% of the substrate area, that is, the area of the substrate occupied by the entire phase change memory system is reduced, the array efficiency is higher, and at this time, the area of the peripheral circuitry is greatly increased, considering that the peripheral circuitry may not require the first 90% of the substrate area, and therefore, a memory controller, a data transmission path, an I/O circuit, and the like may be further provided on the semiconductor structure where the peripheral circuit is located.
Next, a second bonding structure is described:
in some embodiments, as shown in FIG. 7a, the array access circuitry 4022 includes first subarray access circuitry 4022-1 and second subarray access circuitry 4022-2;
the first semiconductor structure 401 includes a memory controller 4012, a first sub-array access circuit 4022-1, a data transmission path 4014, an I/O circuit 4015, and a first bonding layer 4016 including a first conductive contact; wherein, the memory controller 4012 at least comprises a processor and an ECC circuit; the first sub-array access circuit 4022-1 at least includes a Page Buffer (which may be expressed as Page Buffer in english);
the second semiconductor structure 402 includes a phase change memory cell array 4023, a peripheral circuit 4013, a second sub-array access circuit 4022-2, and a second bonding layer 4024 including a second conductive contact; wherein, the peripheral circuit 4013 at least comprises a voltage generator, a RAM and a ROM; the second sub-array access circuit 4022-2 includes at least an address line driver and an address line decoder.
Here, a processor, such as a CPU, in the memory controller 4012 may be better used to implement the interaction between the phase change memory cell array and the corresponding connection circuit. Here, the peripheral circuit 4013 may include a corresponding current generator, a fuse protection circuit, and the like, in addition to the voltage generator, the RAM, and the ROM.
In practical applications, in the phase change memory system, the array access circuit 4022 is complex, and occupies a large substrate area when disposed in a semiconductor structure with a corresponding phase change memory cell array 4023. Based on this, the corresponding circuits included in the array access circuit 4022 may be split, where at least two sub-array access circuits, that is, a first sub-array access circuit 4022-1 and a second sub-array access circuit 4022-2, may be split; thus, the sub-array access circuit which is connected more closely to the memory controller, such as the first sub-array access circuit 4022-1, can be provided on one semiconductor structure, such as the first semiconductor structure 401. Meanwhile, a sub-array access circuit which is connected with the phase change memory cell array and an address line thereof more closely, such as the second sub-array access circuit 4022-2, and the phase change memory cell array 4023 are provided on another semiconductor structure, such as the second semiconductor structure 402. Therefore, the complex array access circuit in the existing requirement can be realized, and a larger usable substrate area can be provided for the complex array access circuit, so that the requirements of the next generation chip size and circuit complexity can be better met.
Here, the page buffer in the first sub-array access circuit 4022-1 may include a read circuit, a write circuit, and the like of the corresponding phase change memory cell array. The role of the address line driver and the address line decoder in the second sub-array access circuit 4022-2 may be to apply a corresponding voltage generated from the address line driver to a corresponding address line based on an address decoded by the address line decoder, so as to read and write data.
In practical applications, the first semiconductor structure 401 may be disposed above the second semiconductor structure 402.
Based on this, in some embodiments, as shown in figure 7b,
the second semiconductor structure 402 includes:
a second substrate 4021;
a peripheral circuit 4013 and a second sub-array access circuit 4022-2 on the second substrate 4021;
a phase change memory cell array 4023 located on the peripheral circuit 4013 and the second sub array access circuit 4022-2;
a second bonding layer 4024 on the phase change memory cell array 4023;
the first semiconductor structure 401 includes:
a first bonding layer 4016 on said second bonding layer 4024;
a memory controller 4012, a first sub-array access circuit 4022-1, a data transmission path 4014, and an I/O circuit 4015 on the first bonding layer 4016;
a first substrate 4011 is provided over the memory controller 4012, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015.
Illustratively, as shown in fig. 7b, the second semiconductor structure 402 includes: a second substrate 4021, a second sub array access circuit 4022-2, a phase change memory cell array 4023, a peripheral circuit 4013, and a second bonding layer 4024; the material of the second substrate 4021 includes, but is not limited to, silicon, and in practical applications, the second substrate 4021 may be doped according to practical requirements. The first semiconductor structure 401 includes: a first substrate 4011, a memory controller 4012, a first sub array access circuit 4022-1, a data transmission path 4014, an I/O circuit 4015, and a first bonding layer 4016; the material of the first substrate 4011 includes, but is not limited to, silicon.
In practical applications, the first semiconductor structure 401 may also be disposed below the second semiconductor structure 402.
Based on this, in some embodiments, as shown in figure 7c,
the first semiconductor structure 401 includes:
a first substrate 4011 formed on a substrate,
a memory controller 4012, a first sub array access circuit 4022-1, a data transmission path 4014, and an I/O circuit 4015 which are located over the first substrate 4011;
a first bonding layer 4016 located on the memory controller 4012, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015;
the second semiconductor structure 402 includes:
a second bonding layer 4024 on the first bonding layer 4016;
a phase change memory cell array 4023 on the second bonding layer 4024;
a peripheral circuit 4013 and a second sub array access circuit 4022-2 which are located on the phase change memory cell array 4023;
a second substrate 4021 located on the peripheral circuit 4013 and the second sub-array access circuit 4022-2.
Here, the first semiconductor structure 401 and the second semiconductor structure 402 are formed the same as the first semiconductor structure 401 and the second semiconductor structure 402 in the foregoing embodiment, and are not described again here.
It is understood that when the first semiconductor structure 401 is disposed above the second semiconductor structure 402, the I/O circuit is disposed on the top side of the first semiconductor structure 401, i.e., the side away from the second semiconductor structure 402, so as to facilitate the leading-out of the electrical connection structure.
It is understood that, compared to some embodiments described above, in the phase change memory system, the stacked phase change memory cell array and array access circuit occupy 90% of the area of the substrate, and the stacked peripheral circuit occupies 10% of the area of the substrate, when the second bonding structure is adopted, the area of the previous substrate can be reserved, a part of the array access circuit and the peripheral circuit can be reserved under the memory cell array, and another part of the array access circuit can be disposed in another semiconductor structure, in this case, the area of the substrate occupied by the whole phase change memory system is equivalent to that of the previous one, but the used areas of the array access circuit and the peripheral circuit are both improved to a greater extent.
The third bonding structure is described below:
in some embodiments, as shown in FIG. 8a, the array access circuitry 4022 includes first subarray access circuitry 4022-1 and second subarray access circuitry 4022-2;
the first semiconductor structure 401 includes a memory controller 4012, a peripheral circuit 4013, a first sub-array access circuit 4022-1, a data transmission path 4014, an I/O circuit 4015, and a first bonding layer 4016 including a first conductive contact; wherein, the memory controller 4012 at least comprises a processor and an ECC circuit; the peripheral circuit 4013 at least comprises a voltage generator, a RAM and a ROM; the first sub-array access circuit includes at least a page buffer;
the second semiconductor structure 402 includes a phase change memory cell array 4023, a second sub-array access circuit 4022-2, and a second bonding layer 4024 including a second conductive contact; wherein the second sub-array access circuitry 4022-2 includes at least an address line driver and an address line decoder.
In practical applications, a processor, such as a CPU, in the memory controller 4012 may be better used to implement the interaction between the phase change memory cell array 4023 and the corresponding connection circuit. Here, the peripheral circuit 4013 may further include a corresponding current generator and a fuse protection circuit in addition to the voltage generator, the RAM, and the ROM.
It should be noted that, in the phase change memory cell array architecture, the number of layers of the memory cells is increased, the corresponding peripheral circuits and memory controllers are more complicated, and the occupied substrate area is increased, so in this embodiment, the more complicated peripheral circuits and memory controllers are disposed in a different semiconductor structure from the phase change memory cell array.
Here, the corresponding circuits included in the array access circuit 4022 are also split, where at least two sub-array access circuits, that is, a first sub-array access circuit and a second sub-array access circuit, can be split; thus, the sub-array access circuit which is connected more closely to the memory controller, such as the first sub-array access circuit 4022-1, can be provided on one semiconductor structure, such as the first semiconductor structure 401. Meanwhile, a sub-array access circuit which is connected with the phase change memory cell array and an address line thereof more closely, such as the second sub-array access circuit 4022-2, and the phase change memory cell array 4023 are provided on another semiconductor structure, such as the second semiconductor structure 402.
In practical applications, the first semiconductor structure 401 may be disposed above the second semiconductor structure 402.
Based on this, in some embodiments, as shown in figure 8b,
the second semiconductor structure 402 includes:
a second substrate 4021;
a second sub-array access circuit 4022-2 located on the second substrate 4021;
a phase change memory cell array 4023 located in the second sub array access circuit 4022-2;
a second bonding layer 4024 on the phase change memory cell array 4023;
the first semiconductor structure 401 includes:
a first bonding layer 4016 on said second bonding layer 4024;
a memory controller 4012, a peripheral circuit 4013, a first sub-array access circuit 4022-1, a data transmission path 4014, and an I/O circuit 4015 on the first bonding layer 4016;
a first substrate 4011 located on the memory controller 4012, the peripheral circuit 4013, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015.
Illustratively, as shown in fig. 8b, the second semiconductor structure 402 includes: a second substrate 4021, a second sub array access circuit 4022-2, a phase change memory cell array 4023, and a second bonding layer 4024; the material of the second substrate 4021 includes, but is not limited to, silicon, and in practical applications, the second substrate 4021 may be doped according to practical requirements. The first semiconductor structure 401 includes: a first substrate 4011, a memory controller 4012, a peripheral circuit 4013, a first sub array access circuit 4022-1, a data transmission path 4014, an I/O circuit 4015, and a first bonding layer 4016; the material of the first substrate 4011 includes, but is not limited to, silicon.
In practical applications, the first semiconductor structure 401 may also be disposed below the second semiconductor structure 402.
Based on this, in some embodiments, as shown in figure 8c,
the first semiconductor structure 401 includes:
a first substrate 4011;
a memory controller 4012, a peripheral circuit 4013, a first sub array access circuit 4022-1, a data transmission path 4014, and an I/O circuit 4015 which are located on the first substrate 4011;
a first bonding layer 4016 located on the memory controller 4012, the peripheral circuit 4013, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015;
the second semiconductor structure 402 includes:
a second bonding layer 4024 on the first bonding layer 4016;
a phase change memory cell array 4023 on the second bonding layer 4024;
a second sub array access circuit 4022-2 located on the phase change memory cell array 4023;
a second substrate 4021 located on the second sub-array access circuit 4022-2.
Here, the first semiconductor structure 401 and the second semiconductor structure 402 are formed the same as the first semiconductor structure 401 and the second semiconductor structure 402 in the foregoing embodiment, and are not described again here.
It is understood that when the first semiconductor structure 401 is disposed above the second semiconductor structure 402, the I/O circuit is disposed on the top side of the first semiconductor structure 401, i.e., the side away from the second semiconductor structure 402, so as to facilitate the leading-out of the electrical connection structure.
It can be understood that, compared to some embodiments described above, in the phase change memory system, the stacked phase change memory cell array and array access circuit occupy 90% of the area of the substrate, and the stacked peripheral circuit occupies 10% of the area of the substrate, when the third bonding structure is adopted, the area of the previous substrate can be reserved, a part of the array access circuit is reserved below the memory cell array, and another part of the array access circuit and the peripheral circuit is disposed in another semiconductor structure, in this case, the area of the substrate occupied by the entire phase change memory system is equivalent to that of the previous substrate, but the used areas of the array access circuit and the peripheral circuit are both greatly increased.
In some embodiments, the phase change memory system further includes an electrical exit structure 404 on the top substrate; the phase change memory system is connected to an external device through the electrical lead-out structure 404; the top substrate is a substrate positioned above the first substrate and the second substrate;
the electrical exit structure 404 comprises: a via 4041 in the top substrate; a conductive plunger 4042 positioned in the through-hole; a rewiring layer 4043 on the top substrate; and pad 4044 on the redistribution layer.
In practical applications, the electrical lead-out structure 404 may be disposed on top of the phase change memory system for leading out components of the phase change memory system that need to be connected to an external device, so as to facilitate connection with the external device. Here, the external device refers to an external circuit, an external device, an external system, or the like that the phase change memory system needs to be connected to when the phase change memory system is used. The electrical lead-out structure can be referred to in particular in fig. 8 b.
Here, the top substrate is a substrate disposed on top of the phase change memory system. Illustratively, when the second semiconductor structure 402 is disposed over the first semiconductor structure 401, the top substrate may refer to the second substrate 4021. Illustratively, when the first semiconductor structure 401 is disposed over the second semiconductor structure 402, the top substrate may refer to the first substrate 4011.
In practice, the conductive plugs 4042 are used to electrically connect the redistribution layer 4043 to the first interconnect layer 4017 via a connection structure. The conductive plunger 4042 generally comprises a conductive material, including but not limited to copper. The rewiring layer 4043 is used to conductively connect the conductive plungers 4042 to the pads 4044. One end of the pad 4044 is connected to the redistribution layer 4043, and the other end is connected to an external device, and finally, electrical connection can be achieved through the pad and the external device. It can be understood that the position layout of the bonding pads can be more flexible through the function of the rewiring layer.
In the phase change memory system provided in the embodiment of the present invention, as shown in fig. 9, the array access circuit having the phase change memory cell array and the relatively close connection thereto is disposed on the wafer 1, at least the peripheral circuit and the memory controller are disposed on the wafer 2, and then the wafer 1 and the wafer 2 are bonded together. In this way, more real estate can be provided for the array access circuitry and/or peripheral circuitry to allow for complex array access circuitry and peripheral circuitry with more embedded functionality.
Meanwhile, for the first bonding structure, the overall substrate area is reduced compared with the prior art, so that the array efficiency is higher and the overall cost is lower.
Based on the phase change memory system, the embodiment of the invention further provides a manufacturing method of the phase change memory system. FIG. 10 is a flowchart illustrating a method for manufacturing a phase change memory system according to an embodiment of the invention. As shown in fig. 10, the method comprises the steps of:
step 1001: forming a first semiconductor structure; the first semiconductor structure at least comprises a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry;
step 1002: forming a second semiconductor structure; the second semiconductor structure at least comprises a phase change memory cell array and another part of array access circuit which are arranged in a stacking mode, and a second bonding layer containing a second conductive contact;
step 1003: bonding the first bonding layer and the second bonding layer to form a bonding layer; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.
Here, fig. 11a to 11e, fig. 12a to 12e, and fig. 13a to 13e are all examples of cross-sectional views of a manufacturing process of a phase change memory system according to an embodiment of the present invention. It should be understood that the operations shown in fig. 10 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Methods of forming phase change memory systems according to various embodiments of the present invention are described below with reference to fig. 10, 11a-11e, 12a-12e, and 13a-13 e.
In practical application, the three bonding structures can be formed by adopting the steps; forming a phase change memory system with a first bonding structure by adopting the first method; forming a phase change memory system with a second bonding structure by adopting the second method; and forming the phase change memory system with the third bonding structure by adopting the third method. The corresponding methods employed to form the three bond structures described above are described below, as follows:
the method comprises the following steps:
in step 1001, as shown in fig. 11a, a processor, an ECC circuit, a voltage generator, a RAM, a ROM, a data transmission path, and an I/O circuit of the phase change memory system are mainly formed.
In some embodiments, the forming the first semiconductor structure 401 includes:
providing a first substrate 4011;
forming the memory controller 4012, a peripheral circuit 4013, a data transfer path 4014, and an I/O circuit 4015 over the first substrate 4011; wherein, the memory controller 4012 at least comprises a processor and an ECC circuit; the peripheral circuit 4013 at least comprises a voltage generator, a RAM and a ROM;
referring to fig. 11b, the first bonding layer 4016 is formed on the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014, and the I/O circuit 4015.
In practical applications, the peripheral circuit 4013 of the phase change memory system may specifically include a Complementary Metal Oxide Semiconductor (CMOS) transistor and a control circuit of the CMOS transistor. The specific process of forming the transistors and the related control circuits of the peripheral circuit of the phase change memory system may include: forming a P-type well region (PWell) and an N-type well region (NWell) on a substrate (such as a silicon substrate), respectively carrying out N doping on the PWell and P doping on the NWell to form a required semiconductor doping region; then, a metal gate is formed above the surface of the substrate, resulting in a peripheral circuit including transistors and associated control circuitry.
It should be noted that the peripheral circuit 4013 may further include a corresponding current generator and a fuse protection circuit in addition to the voltage generator, the RAM and the ROM. Namely, the related control circuits here may include a voltage generator, a current generator, a RAM, a ROM, a fuse protection circuit, and a processor, an ECC circuit included in the memory controller.
Wherein, in some embodiments, as shown in fig. 11b, the method further comprises:
after the memory controller 4012, the peripheral circuits 4013, the data transfer path 4014, and the I/O circuit 4015 are formed over the first substrate 4011, a first interconnect layer 4017 is formed over the memory controller 4012, the peripheral circuits 4013, the data transfer path 4014, and the I/O circuit 4015;
the forming of the first bonding layer 4016 on the memory controller 4012, the peripheral circuit 4013, the data transmission path 4014, and the I/O circuit 4015 includes:
the first bonding layer 4016 is formed on the first interconnect layer 4017 so that the memory controller 4012, the peripheral circuits 4013, the data transmission path 4014, and the I/O circuit 4015 are connected to the first conductive contact 4018 through the first interconnect layer 4017.
In practical applications, the method for forming the first interconnect layer 4017 includes: forming a dielectric layer; forming a hole or a groove which penetrates through the dielectric layer and extends into the structure to be connected in the dielectric layer; the holes or trenches are filled with a conductive material to form a first interconnect layer 4017. Here, the dielectric layer may include silicon oxide, and the conductive material may include copper or tungsten.
In practical applications, the process of forming the first bonding layer 4016 may include: forming a first dielectric layer; forming a first groove in the first dielectric layer; and filling a metal material into the first groove to form a conductive contact. Here, the manner of forming the first dielectric layer may be a thermal oxidation method or a deposition method; for example, the oxidizing atmosphere of the thermal oxidation method may be dry oxygen oxidation, water vapor oxidation, and wet oxygen oxidation; the deposition method can be physical vapor deposition, chemical vapor deposition, sputtering, and the like. The manner of forming the trench may include etching, for example, dry etching. The manner of filling the metal material may be a commonly used metal deposition method.
In step 1002, a stacked arrangement of a phase change memory cell array and address line drivers, address line decoders, and page buffers are primarily formed.
In some embodiments, as shown in fig. 11c and 11d, the forming the second semiconductor structure 402 includes:
providing a second substrate 4021;
forming an array access circuit 4022 over the second substrate 4021; wherein the array access circuitry 4022 comprises at least an address line driver, an address line decoder, and a page buffer;
a phase change memory cell array 4023 of the phase change memory system is formed over the array access circuit 4022;
the second bonding layer 4024 is formed on the phase change memory cell array 4023.
In practical applications, the method for forming the phase change memory cell array 4023 may include: forming a first address line layer on the address line interconnect layer; forming a plurality of memory cells and a second address line layer on the first address line layer to form the phase change memory cell array; wherein the first address line layer and the second address line layer are parallel to a same plane and perpendicular to each other, each of the plurality of memory cells being perpendicular to both the first address line layer and the second address line layer.
In practical applications, the first address line layer may include a word line layer, and correspondingly, the second address line layer may include a bit line layer; alternatively, the first address line layer may comprise a bit line layer and the corresponding second address line layer may comprise a word line layer. The first address line layer may include a plurality of word lines or bit lines; the second address line layer may include a plurality of bit lines or word lines. In practical applications, the material of the word line or the bit line may include tungsten. The first address line layer is parallel to the second address line layer, and the address lines (word lines or bit lines) of the first address line layer are perpendicular to the address lines (bit lines or word lines) of the second address line layer; each memory cell of the plurality of memory cells is perpendicular to both the first address line layer and the second address line layer. Each of the memory cells includes: the phase change memory device comprises a first electrode layer, a gating layer, a second electrode layer, a phase change memory layer and a third electrode layer which are sequentially stacked. Here, the relative positional relationship among the word lines, the bit lines, and the memory cells and the structure of the memory cells can all refer to fig. 2.
In practical applications, the step of forming an address line of the corresponding first address line layer or an address line of the corresponding second address line layer includes: depositing a conductor layer; patterning the conductor layer; and etching the conductor layer subjected to patterning treatment to form an address line corresponding to the first address line layer or an address line corresponding to the second address line layer.
In practical applications, referring to fig. 2, the step of forming the corresponding memory cell includes: sequentially depositing a first electrode layer 205, a gate layer 204, a second electrode layer 203, a phase change material layer 202 and a third electrode layer 201 on the corresponding first address line layer; patterning the first electrode layer 205, the gate layer 204, the second electrode layer 203, the phase change material layer 202 and the third electrode layer 201; and etching the first electrode layer 205, the gate layer 204, the second electrode layer 203, the phase change material layer 202 and the third electrode layer 201 after the patterning treatment to form a corresponding memory cell.
Wherein, in some embodiments, as shown in fig. 11d, the method further comprises:
after forming a phase change memory cell array 4023 of the phase change memory system over the array access circuit 4022, a second interconnect layer 4025 is formed over the phase change memory cell array 4023;
the forming of the second bonding layer 4024 on the phase change memory cell array 4023 includes:
the second bonding layer 4024 is formed over the second interconnect layer 4025, so that the phase change memory cell array 4023 of the phase change memory system formed over the array access circuit 4022 is connected to the second conductive contact 4026 through the second interconnect layer 4025.
In practical applications, the specific manner of forming the second interconnect layer 4025 is similar to the specific manner of forming the first interconnect layer, and is not described herein again.
It should be noted that the execution order of step 1001 and step 1002 is not limited, and both may be parallel. As long as it is done before step 1003.
In step 1003, as shown in fig. 11e, the formed first semiconductor structure 401 and the second semiconductor structure 402 are mainly bonded.
In practical applications, the bonding manner may specifically include: the first bonding layer 4016 in the first semiconductor structure 401 and the second bonding layer 4024 in the second semiconductor structure 402 are aligned such that the first conductive contact 4018 is in contact with the second conductive contact 4026. Subsequently, the conductive contacts of the two are electrically connected together by heating, and the hydrogen ions and the oxygen ions of the non-metal regions of the two semiconductor structures are combined with each other, so that the non-metal regions of the first semiconductor structure 401 and the second semiconductor structure 402 are combined together. Before the first semiconductor structure 401 and the second semiconductor structure 402 are contacted, the method further comprises the following steps: the surfaces of the first semiconductor structure 401 and the second semiconductor structure 402 are cleaned and ion bombarded, so that free hydrogen ions and oxygen ions on the surfaces of the semiconductor structures are increased, and subsequent bonding is facilitated.
The second method comprises the following steps:
in step 1001, as shown in fig. 12a, 12b, and 12c, a processor, an ECC circuit, a page buffer, a data transfer path, and an I/O circuit of the phase change memory system are mainly formed.
In some embodiments, the array access circuitry 4022 includes first subarray access circuitry 4022-1 and second subarray access circuitry 4022-2;
the forming of the first semiconductor structure 401 includes:
providing a first substrate 4011;
referring to fig. 12b, the memory controller 4012, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015 are formed over the first substrate 4011; wherein, the memory controller 4012 at least comprises a processor and an ECC circuit; the first sub-array access circuit 4022-1 includes at least a page buffer; the first bonding layer 4016 is formed over the memory controller 4012, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015.
In practical applications, the specific manner of forming the page buffer is similar to the specific manner of forming the processor, the ECC circuit, the data transmission path, and the I/O circuit, and will not be described herein again.
Wherein, in some embodiments, as shown in fig. 12b, the method further comprises:
after the memory controller 4012, the first sub array access circuit 4022-1, the data transfer path 4014, and the I/O circuit 4015 are formed over the first substrate 4011, a first interconnect layer 4017 is formed over the memory controller 4012, the first sub array access circuit 4022-1, the data transfer path 4014, and the I/O circuit 4015;
the forming of the first bonding layer 4016 on the memory controller 4012, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015 includes:
the first bonding layer 4016 is formed on the first interconnect layer 4017 so that the memory controller 4012, the first subarray access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015 are connected to the first conductive contact 4018 through the first interconnect layer 4017.
In step 1002, a phase change memory cell array, a voltage generator, a RAM, a ROM, an address line driver, and an address line decoder of a phase change memory system are mainly formed.
In some embodiments, as shown in fig. 12c and 12d, the forming the second semiconductor structure 402 includes:
providing a second substrate 4021;
a peripheral circuit 4013 and a second sub array access circuit 4022-2 of the phase change memory system are formed over the second substrate 4021; wherein, the peripheral circuit 4013 at least comprises a voltage generator, a RAM and a ROM; the second sub-array access circuit 4022-2 includes at least an address line driver and an address line decoder;
a phase change memory cell array 4023 of the phase change memory system is formed over the peripheral circuit 4013 and the second subarray access circuit 4022-2;
the second bonding layer 4024 is formed on the phase change memory cell array 4023.
In practical applications, the specific manner of forming the page buffer is similar to the specific manner of forming the processor, the ECC circuit, the data transmission path, and the I/O circuit, and will not be described herein again.
Wherein, in some embodiments, as shown in fig. 12d, the method further comprises:
after forming a phase change memory cell array 4023 of the phase change memory system over the peripheral circuit 4013 and the second subarray access circuit 4022-2, a second interconnect layer 4025 is formed over the phase change memory cell array 4023;
the forming of the second bonding layer 4024 on the phase change memory cell array 4023 includes:
the second bonding layer 4024 is formed over the second interconnect layer 4025, so that the phase change memory cell array 4023 of the phase change memory system formed over the peripheral circuit 4013 and the second sub array access circuit 4022-2 is connected to the second conductive contact 4026 through the second interconnect layer 4025.
In practical applications, the specific manner of forming the second interconnect layer 4025 is similar to that of forming the first interconnect layer 4017, and is not described herein again.
It should be noted that the execution order of step 1001 and step 1002 is not limited, and both may be parallel. As long as it is done before step 1003.
In step 1003, as shown in fig. 12e, the formed first semiconductor structure and the second semiconductor structure are mainly bonded.
In practical applications, the specific bonding manner is the same as that described in the foregoing embodiments, and is not described herein again.
The third method comprises the following steps:
in step 1001, as shown in fig. 13a, a processor, an ECC circuit, a voltage generator, a RAM, a ROM, a page buffer, a data transmission path, and an I/O circuit of the phase change memory system are mainly formed.
In some embodiments, the array access circuitry comprises first and second sub-array access circuitry;
the forming of the first semiconductor structure 401 includes:
providing a first substrate 4011;
forming the memory controller 4012, a peripheral circuit 4013, a first sub array access circuit 4022-1, a data transmission path 4014, and an I/O circuit 4015 over the first substrate 4011; wherein, the memory controller 4012 at least comprises a processor and an ECC circuit; the peripheral circuit 4013 at least comprises a voltage generator, a RAM and a ROM; the first sub-array access circuit 4022-1 includes at least a page buffer;
forming the first bonding layer 4016 on the memory controller 4012, the peripheral circuit 4013, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015;
in practical applications, the specific manner of forming the processor, the ECC circuit, the page buffer, the data transmission path, and the I/O circuit is similar to the specific manner of forming the processor, the ECC circuit, the page buffer, the data transmission path, and the I/O circuit, and the specific manner of forming the first bonding layer is similar to the specific manner of forming the first bonding layer and the second bonding layer, which is not repeated herein.
Wherein, in some embodiments, as shown in fig. 13b, the method further comprises:
after the memory controller 4012, the peripheral circuit 4013, the first sub-array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015 are formed over the first substrate 4011, a first interconnect layer 4017 is formed over the memory controller 4012, the peripheral circuit 4013, the first sub-array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015;
the forming of the first bonding layer 4016 on the memory controller 4012, the peripheral circuit 4013, the first sub array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015 includes:
the first bonding layer 4016 is formed on the first interconnect layer 4017 so that the memory controller 4012, the peripheral circuit 4013, the first sub-array access circuit 4022-1, the data transmission path 4014, and the I/O circuit 4015 are connected to the first conductive contact 4018 through the first interconnect layer 4017.
Here, the specific manner of forming the first interconnect layer is similar to that of forming the interconnect layer described above, and is not described here again.
In step 1002, as shown in fig. 13c and 13d, the phase change memory cell array, the address line driver and the address line decoder of the phase change memory system are mainly formed
In some embodiments, the forming the second semiconductor structure 402 includes:
providing a second substrate 4021;
forming a second sub array access circuit 4022-2 over the second substrate 4021; wherein the second sub-array access circuitry 4022-2 comprises at least an address line driver and an address line decoder;
forming a phase change memory cell array 4023 of the phase change memory system on the second sub array access circuit 4022-2;
the second bonding layer 4024 is formed on the phase change memory cell array 4023.
Wherein, in some embodiments, as shown in fig. 13d, the method further comprises:
after forming a phase change memory cell array 4023 of the phase change memory system over the second sub array access circuit 4022-2, a second interconnect layer 4025 is formed over the phase change memory cell array 4023;
the forming of the second bonding layer 4024 on the phase change memory cell array 4023 includes:
the second bonding layer 4024 is formed on the second interconnect layer 4025, so that the phase change memory cell array 4023 of the phase change memory system formed on the second sub array access circuit 4022-2 is connected to the second conductive contact 4026 through the second interconnect layer 4025.
Here, a specific manner of forming the second interconnect layer 4025 is similar to that of forming the interconnect layer described above, and details thereof are not described here.
It should be noted that the execution order of step 1001 and step 1002 is not limited, and both may be parallel. As long as it is done before step 1003.
In step 1003, the formed first semiconductor structure and the second semiconductor structure are mainly bonded.
In practical applications, the specific bonding manner is the same as that described in the foregoing embodiments, and is not described herein again.
In some embodiments, after forming the bonding bond layer,
the first semiconductor structure is formed over the second semiconductor structure.
In practical applications, the first semiconductor structure may also be formed below the second semiconductor structure.
It is understood that when the first semiconductor structure 401 is disposed above the second semiconductor structure 402, the I/O circuit is disposed on the top side of the first semiconductor structure 401, i.e., the side away from the second semiconductor structure 402, so as to facilitate the leading-out of the electrical connection structure.
In practice, after bonding, an electrical lead-out structure 404 may also be formed on top of the bonded structure, as shown in fig. 13 e.
In some embodiments, the method further comprises:
forming an electrical exit structure 404 on the first substrate; the phase change memory system is connected to an external device through the electrical lead-out structure 404;
the forming of the electrical exit structure 404 includes:
forming a via 4041 in the first substrate;
filling a conductive material in the through hole to form a conductive plunger 4042;
forming a rewiring layer 4043 over the first substrate;
a pad 4044 is formed on the redistribution layer.
Here, the first substrate may be understood as a substrate disposed on top of the phase change memory system.
Illustratively, when the second semiconductor structure 402 is disposed over the first semiconductor structure 401, the top substrate may be referred to as the second substrate 4021. Exemplarily, when the first semiconductor structure 401 is disposed over the second semiconductor structure 402, the top substrate may be referred to as a first substrate 4011, as shown in fig. 13 e.
In practical application, in order to reduce the difficulty of the process for forming the through hole, the top substrate may be thinned first and then the through hole may be etched. The conductive plunger 4042 generally comprises a conductive material, including but not limited to copper. The manner of forming the conductive plug may be a conventional metal deposition method. The rewiring layer can realize connection among different structures in a through hole or via hole mode.
Note that, in each of the first semiconductor structure 401 and the second semiconductor structure 402, a device which needs to be connected to the outside can be electrically led out through the first interconnect layer 4017, the second interconnect layer 4025, and the electrical lead-out structure 404.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (17)

1. A phase change memory system, comprising:
a first semiconductor structure comprising at least a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry;
a second semiconductor structure including at least an array of phase change memory cells and another portion of the array access circuitry arranged in a stack, and a second bonding layer including a second conductive contact;
a bonding layer between the first semiconductor structure and the second semiconductor structure; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.
2. The storage system of claim 1,
the first semiconductor structure comprises a memory controller, a peripheral circuit, a data transmission path, an input/output circuit and a first bonding layer comprising a first conductive contact; the memory controller at least comprises a processor and an error correction ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory;
the second semiconductor structure comprises a phase change memory cell array and array access circuitry and a second bonding layer comprising a second conductive contact; wherein the array access circuit includes at least an address line driver, an address line decoder, and a page buffer.
3. The storage system of claim 2,
the second semiconductor structure includes:
a second substrate;
the array access circuitry located on the second substrate;
the array of phase change memory cells on the array access circuit;
the second bonding layer located on the array of phase change memory cells;
the first semiconductor structure includes:
the first bonding layer on the second bonding layer;
the memory controller, the peripheral circuit, the data transmission path and the input and output circuit are positioned on the first bonding layer;
a first substrate on the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit.
4. The memory system of claim 1, wherein the array access circuit comprises a first subarray access circuit and a second subarray access circuit;
the first semiconductor structure comprises a memory controller, a first subarray access circuit, a data transmission path, an input output circuit and a first bonding layer comprising a first conductive contact; wherein, the memory controller at least comprises a processor and an ECC circuit; the first sub-array access circuit comprises at least a page buffer;
the second semiconductor structure comprises a phase change memory cell array, a peripheral circuit, a second subarray access circuit and a second bonding layer containing a second conductive contact; wherein, the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the second sub-array access circuit includes at least an address line driver and an address line decoder.
5. The storage system of claim 4,
the second semiconductor structure includes:
a second substrate;
peripheral circuitry and second sub-array access circuitry located on the second substrate;
an array of phase change memory cells on the peripheral circuit and the second subarray access circuit;
the second bonding layer located on the array of phase change memory cells;
the first semiconductor structure includes:
the first bonding layer on the second bonding layer;
the memory controller, the first subarray access circuit, the data transmission path and the input and output circuit are positioned on the first bonding layer;
a first substrate on the memory controller, the first sub-array access circuits, the data transmission paths, and the input-output circuits.
6. The memory system of claim 1, wherein the array access circuit comprises a first subarray access circuit and a second subarray access circuit;
the first semiconductor structure comprises a memory controller, a peripheral circuit, a first subarray access circuit, a data transmission path, an input-output circuit and a first bonding layer comprising a first conductive contact; wherein, the memory controller at least comprises a processor and an ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the first sub-array access circuit includes at least a page buffer;
the second semiconductor structure comprises a phase change memory cell array and a second sub-array access circuit and a second bonding layer comprising a second conductive contact; wherein the second sub-array access circuit includes at least an address line driver and an address line decoder.
7. The storage system of claim 6,
the second semiconductor structure includes:
a second substrate;
the second sub-array access circuit located on the second substrate;
the array of phase change memory cells on the second subarray access circuit;
the second bonding layer located on the array of phase change memory cells;
the first semiconductor structure includes:
the first bonding layer on the second bonding layer;
the memory controller, the peripheral circuit, the first sub-array access circuit, the data transmission path and the input and output circuit are positioned on the first bonding layer;
a first substrate on the memory controller, the peripheral circuitry, the first sub-array access circuitry, the data transmission paths, and the input-output circuitry.
8. The memory system of claim 3, 5 or 7, wherein the phase change memory system further comprises an electrical extraction structure on the first substrate; the phase change memory system is connected with an external device through the electric leading-out structure;
the electrical lead-out structure includes: a via in the first substrate; a conductive plunger in the through hole; a rewiring layer on the first substrate; and a bonding pad on the redistribution layer.
9. A method of manufacturing a phase change memory system, comprising:
forming a first semiconductor structure; the first semiconductor structure at least comprises a peripheral device and a first bonding layer comprising a first conductive contact; wherein the peripheral device comprises peripheral circuitry and/or a portion of array access circuitry;
forming a second semiconductor structure; the second semiconductor structure at least comprises a phase change memory cell array and another part of array access circuit which are arranged in a stacking mode, and a second bonding layer containing a second conductive contact;
bonding the first bonding layer and the second bonding layer to form a bonding layer; wherein the first conductive contact is electrically connected to the second conductive contact at the bonding bond coat.
10. The method of claim 9,
the forming a first semiconductor structure includes:
providing a first substrate;
forming the memory controller, a peripheral circuit, a data transmission path, and an input-output circuit over the first substrate; wherein, the memory controller at least comprises a processor and an ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory;
forming the first bonding layer on the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit;
the forming a second semiconductor structure includes:
providing a second substrate;
forming array access circuitry on the second substrate; wherein the array access circuit comprises at least an address line driver, an address line decoder, and a page buffer;
forming an array of phase change memory cells of the phase change memory system on the array access circuitry;
forming the second bonding layer on the array of phase change memory cells.
11. The method of claim 10, further comprising:
forming a first interconnection layer on the memory controller, the peripheral circuits, the data transmission path, and the input-output circuit after forming the memory controller, the peripheral circuits, the data transmission path, and the input-output circuit on the first substrate;
the forming the first bonding layer on the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit includes:
forming the first bonding layer on the first interconnection layer to connect the memory controller, the peripheral circuit, the data transmission path, and the input-output circuit with the first conductive contact through the first interconnection layer;
the method further comprises the following steps:
forming a second interconnect layer on the array of phase change memory cells after forming the array of phase change memory cells of the phase change memory system on the array access circuitry;
the forming the second bonding layer on the array of phase change memory cells includes:
forming the second bonding layer on the second interconnect layer to connect the array of phase change memory cells forming the phase change memory system on the array access circuitry with the second conductive contact through the second interconnect layer.
12. The method of claim 9, wherein the array access circuit comprises a first sub-array access circuit and a second sub-array access circuit;
the forming a first semiconductor structure includes:
providing a first substrate;
forming the memory controller, a first sub-array access circuit, a data transmission path, and an input-output circuit on the first substrate; wherein, the memory controller at least comprises a processor and an ECC circuit; the first sub-array access circuit includes at least a page buffer; forming the first bonding layer on the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit;
the forming a second semiconductor structure includes:
providing a second substrate;
forming a peripheral circuit and a second sub-array access circuit of the phase change memory system on the second substrate; wherein, the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the second sub-array access circuit comprises at least an address line driver and an address line decoder;
forming a phase change memory cell array of the phase change memory system on the peripheral circuit and the second sub-array access circuit;
forming the second bonding layer on the array of phase change memory cells.
13. The method of claim 12, further comprising:
after forming the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit on the first substrate, forming a first interconnection layer on the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit;
the forming the first bonding layer on the memory controller, the first sub-array access circuit, the data transmission path, and the input-output circuit includes:
forming the first bonding layer on the first interconnect layer to connect the memory controller, the first sub-array access circuits, the data transmission paths, and the input-output circuits with the first conductive contacts through the first interconnect layer;
the method further comprises the following steps:
forming a second interconnect layer on the phase change memory cell array after forming the phase change memory cell array of the phase change memory system on the peripheral circuit and a second sub-array access circuit;
the forming the second bonding layer on the array of phase change memory cells includes:
forming the second bonding layer on the second interconnect layer such that an array of phase change memory cells forming the phase change memory system on the peripheral circuitry and second sub-array access circuitry are connected with the second conductive contact through the second interconnect layer.
14. The method of claim 9, wherein the array access circuit comprises a first sub-array access circuit and a second sub-array access circuit;
the forming a first semiconductor structure includes:
providing a first substrate;
forming the memory controller, peripheral circuits, a first sub-array access circuit, data transmission paths, and input-output circuits on the first substrate; wherein, the memory controller at least comprises a processor and an ECC circuit; the peripheral circuit at least comprises a voltage generator, a random access memory and a read-only memory; the first sub-array access circuit includes at least a page buffer;
forming the first bonding layer on the memory controller, peripheral circuitry, first sub-array access circuitry, data transmission paths, and input-output circuitry;
the forming a second semiconductor structure includes:
providing a second substrate;
forming a second sub-array access circuit on the second substrate; wherein the second sub-array access circuit comprises at least an address line driver and an address line decoder;
forming an array of phase change memory cells of the phase change memory system on the second sub-array access circuit;
forming the second bonding layer on the array of phase change memory cells.
15. The method of claim 14, further comprising:
after forming the memory controller, peripheral circuits, the first sub-array access circuits, data transmission paths, and input-output circuits on the first substrate, forming a first interconnect layer on the memory controller, peripheral circuits, the first sub-array access circuits, data transmission paths, and input-output circuits;
the forming the first bonding layer on the memory controller, the peripheral circuitry, the first sub-array access circuitry, the data transmission path, and the input-output circuitry includes:
forming the first bonding layer on the first interconnect layer to connect the memory controller, peripheral circuitry, first sub-array access circuitry, data transmission paths, and input-output circuitry with the first conductive contacts through the first interconnect layer;
the method further comprises the following steps:
forming a second interconnect layer on the phase change memory cell array of the phase change memory system after forming the phase change memory cell array on the second sub-array access circuit;
the forming the second bonding layer on the array of phase change memory cells includes:
forming the second bonding layer on the second interconnect layer such that the array of phase change memory cells forming the phase change memory system on the second sub-array access circuit is connected with the second conductive contact through the second interconnect layer.
16. The method of claim 10, 12 or 14, wherein, after forming the bonding bond layer,
the first semiconductor structure is formed over the second semiconductor structure.
17. The method of claim 16, further comprising:
forming an electrical extraction structure on the first substrate; the phase change memory system is connected with an external device through the electric leading-out structure;
the forming of the electrical lead-out structure includes:
forming a via in the first substrate;
filling a conductive material in the through hole to form a conductive plunger;
forming a rewiring layer on the first substrate;
and forming a welding pad on the rewiring layer.
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