CN113517312B

CN113517312B - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN113517312B
Application number: CN202110402635.4A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2022-09-06
Anticipated expiration: 2041-04-14
Also published as: CN113517312A

Abstract

The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises: at least one memory cell array block; the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units and a second address line layer which are arranged in a stacked mode; wherein the first address line layer is parallel to the second address line layer; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the first direction is perpendicular to the second direction; the first phase change memory cell is perpendicular to both the first address line and the second address line; the length of the first address line in a first direction is substantially the same as the length of the second address line in a second direction, and the resistance of the first address line is substantially the same as the resistance of the second address line.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.

Background

Three-dimensional cross-point memories, such as Phase Change Memories (PCMs), are a Memory technology that uses chalcogenides as the storage medium to store data by using the difference in resistance of materials in different states. PCM has the advantages of bit-addressable, no data loss after power-off, high storage density, fast read-write speed, etc., and is considered as the most promising next-generation memory.

However, in the related art, three-dimensional cross-point memories also present various challenges.

Disclosure of Invention

In order to solve the related technical problems, the embodiment of the invention provides a three-dimensional memory.

An embodiment of the present invention provides a three-dimensional memory, including: at least one memory cell array block;

the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units and a second address line layer which are arranged in a stacked mode; wherein the first address line layer is parallel to the second address line layer; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the first direction is perpendicular to the second direction; the first phase change memory cell is perpendicular to both the first address line and the second address line;

the length of the first address line in a first direction is substantially the same as the length of the second address line in a second direction, and the resistance of the first address line is substantially the same as the resistance of the second address line.

In the above scheme, the first address line includes a first sub-address line and a second sub-address line which are arranged in a stacked manner, and the materials of the first sub-address line and the second sub-address line are the same or different;

and/or the presence of a gas in the gas,

the second address line comprises a third sub-address line and a fourth sub-address line which are arranged in a stacked mode, and the materials of the third sub-address line and the fourth sub-address line are the same or different.

In the above solution, the three-dimensional memory further includes a functional device of a peripheral circuit;

the functional devices include a first functional device connected to the first address line and a second functional device connected to the second address line;

the first functional device is arranged on the first area and the second area; the second functional device is arranged on the third area, the fourth area, the fifth area and the sixth area; the projection of the first area and the second area in the second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the projection lengths of the first area, the second area, the third area, the fourth area, the fifth area and the sixth area in the second direction are equal to the projection lengths of the first area and the second area in the second direction, and the projection lengths of the first area, the second area, the third area, the fourth area, the fifth area and the sixth area in the first direction are equal to the projection lengths of the third area, the fourth area, the fifth area and the sixth area in the first direction.

In the above solution, the pitches of the first address lines in the second direction are the same; the pitch of each second address line in the plurality of second address lines along the first direction is the same.

In the above solution, the three-dimensional memory further includes: a first connection portion in contact with the first address line and a second connection portion in contact with the second address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block through corresponding first connection portions, and the second functional devices are respectively connected to all second address lines in the memory cell array block through corresponding second connection portions;

the first connecting part is contacted with the geometric center of the first address wire;

and/or the presence of a gas in the gas,

the second connection portion is in contact with a geometric center of the second address line.

In the above scheme, the memory cell array block further includes: stacking a plurality of second phase change memory cells and a third address line layer disposed on the second address line layer; wherein the third address line layer is parallel to the second address line layer; the third address line layer comprises a plurality of third address lines which extend along the first direction; the third address line is overlapped with the projection part of the first address line on the first plane; the second phase change memory cell is perpendicular to the second address line and the third address line; the first plane is perpendicular to the stacking direction;

the length of the third address line in the first direction is substantially the same as the length of the second address line in the second direction, and the resistance of the third address line is substantially the same as the resistance of the second address line.

In the above-mentioned scheme, the first and second light sources,

the first address line comprises a first sub-address line and a second sub-address line which are arranged in a stacked mode, and the materials of the first sub-address line and the second sub-address line are the same or different;

the third address line comprises a fifth sub-address line and a sixth sub-address line which are arranged in a stacked mode, and the materials of the fifth sub-address line and the sixth sub-address line are the same or different;

and/or the presence of a gas in the gas,

In the above scheme, the three-dimensional memory further includes a functional device of a peripheral circuit;

the functional devices include a first functional device connected to the first address line, a second functional device connected to the second address line, and a third functional device connected to the third address line; the first functional device is arranged on the first area and the second area; the second functional device is arranged on the third area, the fourth area, the fifth area and the sixth area; the third functional device is arranged on the seventh area and the eighth area;

the projection of the first area and the second area in the second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the seventh area and the eighth area have a common endpoint in the projection of the second direction; the projection length of the first area, the second area, the third area, the fourth area, the fifth area, the sixth area, the seventh area and the eighth area in the second direction is equal to the projection length of the seventh area and the eighth area in the second direction, and the projection length of the first area, the second area, the third area, the fourth area, the fifth area, the sixth area, the seventh area and the eighth area in the first direction is equal to the projection length of the third area, the fourth area, the fifth area and the sixth area in the first direction.

In the above solution, the pitches of the first address lines in the second direction are the same; the pitches of the second address lines in the first direction are the same; and the pitches of the third address lines in the second direction are the same.

In the above solution, the three-dimensional memory further includes: a first connection portion contacting the first address line, a second connection portion contacting the second address line, and a third connection portion contacting the third address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block by corresponding first connecting portions, the second functional devices are respectively connected to all second address lines in the memory cell array block by corresponding second connecting portions, and the third functional devices are respectively connected to all third address lines in the memory cell array block by corresponding third connecting portions;

the first connecting part is contacted with the geometric center of the first address wire; the third connecting part is contacted with the geometric center of the third address line;

and/or the presence of a gas in the atmosphere,

In the above scheme, the three-dimensional memory further includes an interconnection layer, and the functional devices are connected to the corresponding connection portions through the interconnection layer.

In the above scheme, the functional device includes a decoder.

In the above scheme, one memory cell includes a phase change memory PCM element, a gate element, and a plurality of electrodes, which are stacked.

The embodiment of the invention also provides a manufacturing method of the three-dimensional memory, which comprises the following steps:

a plurality of first address lines forming a first address line layer, the plurality of first address lines each extending in a first direction;

forming a plurality of first phase change memory cells on the first address line layer;

forming a plurality of second address lines of a second address line layer on the plurality of first phase change memory cells, the plurality of second address lines each extending in a second direction perpendicular to the first direction; the first phase change memory cell is perpendicular to both the first address line and the second address line;

a length of the first address line in a first direction is substantially the same as a length of the second address line in a second direction, and a resistance of the first address line is substantially the same as a resistance of the second address line.

In the above-mentioned scheme, the first step of the method,

the step of forming each of the plurality of first address lines of the first address line layer includes:

forming a first sub-address line, and forming a second sub-address line on the first sub-address line to cover the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different;

and/or the presence of a gas in the gas,

the step of forming each of a plurality of second address lines of the second address line layer includes:

forming a third sub-address line on the first phase change memory cell, and forming a fourth sub-address line on the third sub-address line to cover the third sub-address line; the materials of the third sub-address line and the fourth sub-address line are the same or different.

In the above scheme, the method further comprises:

forming a plurality of second phase change memory cells on the second address line layer;

a plurality of third address lines forming a third address line layer on the plurality of second phase change memory cells, the plurality of third address lines each extending in the first direction; the second phase change memory unit is vertical to the second address line and the third address line;

a length of the third address line in a first direction is substantially the same as a length of the second address line in a second direction, and a resistance of the third address line is substantially the same as a resistance of the second address line.

In the above-mentioned scheme, the first and second light sources,

the step of forming each of the plurality of first address lines of the first address line layer includes: forming a first sub-address line, and forming a second sub-address line on the first sub-address line to cover the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different; the step of forming each of a plurality of third address lines of the third address line layer includes: forming a fifth sub-address line on the second phase change memory unit, and forming a sixth sub-address line on the fifth sub-address line to cover the fifth sub-address line; the materials of the fifth sub address line and the sixth sub address line are the same or different;

and/or the presence of a gas in the gas,

the step of forming each of a plurality of second address lines of the second address line layer includes: forming a third sub-address line on the first phase change memory cell, and forming a fourth sub-address line on the third sub-address line to cover the third sub-address line; the materials of the third sub-address line and the fourth sub-address line are the same or different.

The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises: at least one memory cell array block; the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units and a second address line layer which are arranged in a stacked mode; wherein the first address line layer is parallel to the second address line layer; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the first direction is perpendicular to the second direction; the first phase change memory cell is perpendicular to both the first address line and the second address line; the length of the first address line in a first direction is substantially the same as the length of the second address line in a second direction, and the resistance of the first address line is substantially the same as the resistance of the second address line. The length of the first address line along the first direction in the three-dimensional memory provided by the embodiment of the invention is equivalent to the length of the second address line along the second direction, so that the number of phase change memory cells in a single memory cell array block is increased, the occupied space size of the single memory cell array block is also increased, namely the area capable of being distributed by functional devices of a peripheral circuit corresponding to the single memory cell array block is also increased, and the increased area can better adapt to the requirements of the next generation chip size and circuit complexity.

Drawings

Fig. 1 is a schematic diagram of a memory cell array of a three-dimensional phase change memory observed by a scanning electron microscope provided in the related art;

FIG. 2a is a partial three-dimensional schematic diagram of a three-dimensional phase change memory having a layer of stacked memory cells according to the related art;

FIG. 2b is a partial horizontal view of a memory cell array of a three-dimensional phase change memory having a layer of stacked memory cells according to the related art;

FIG. 2c is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having a layer of stacked memory cells according to the related art;

FIG. 2d is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having a layer of stacked memory cells provided in the related art;

fig. 2e is a partial horizontal schematic diagram illustrating a distribution of an area for disposing a functional device in a peripheral circuit of a three-dimensional phase change memory having memory cells stacked in one layer provided in the related art;

FIG. 3a is a partial three-dimensional schematic diagram of a three-dimensional phase change memory having a stack of memory cells according to an embodiment of the present invention;

FIG. 3b is a partial first horizontal view of a memory cell array of a three-dimensional phase change memory having a layer of stacked memory cells according to an embodiment of the present invention;

FIG. 3c is a partial horizontal view of a memory cell array of a three-dimensional phase change memory having a stack of memory cells according to an embodiment of the present invention;

fig. 4a to fig. 4g are schematic diagrams illustrating different distribution situations of setting areas of functional devices corresponding to a memory cell block of a three-dimensional phase change memory having stacked memory cells according to an embodiment of the present invention;

FIG. 4h is a schematic diagram illustrating the distribution of word lines and bit lines corresponding to a memory cell block of a three-dimensional phase change memory having a stack of memory cells according to the related art and in an embodiment of the invention;

fig. 5 is a schematic diagram of a first connection portion and a second connection portion connected to corresponding functional devices by an interconnection layer according to an embodiment of the present invention;

FIG. 6a is a partial three-dimensional schematic diagram of a three-dimensional phase-change memory having two stacked memory cells according to the related art;

FIG. 6b is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having two stacked memory cells according to the related art;

FIG. 6c is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having two stacked memory cells according to the related art;

FIG. 6d is a schematic diagram illustrating a third schematic diagram of a memory cell array of a three-dimensional phase change memory having two stacked memory cells according to the related art;

fig. 6e is a partial horizontal schematic diagram illustrating a distribution of an area for disposing a functional device in a peripheral circuit of a three-dimensional phase change memory having two stacked memory cells provided in the related art;

FIG. 7a is a partial three-dimensional schematic diagram of a three-dimensional phase change memory having two stacked memory cells according to an embodiment of the present invention;

FIG. 7b is a partial first horizontal view of a memory cell array of a three-dimensional phase change memory having two stacked memory cells according to an embodiment of the present invention;

FIG. 7c is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having two stacked memory cells according to an embodiment of the present invention;

FIGS. 8a to 8e are schematic diagrams illustrating several different distributions of the layout areas of the functional devices corresponding to one memory cell block of the three-dimensional phase change memory having two stacked memory cells according to an embodiment of the present invention;

FIG. 8f is a schematic diagram illustrating the distribution of word lines and bit lines corresponding to a memory cell block of a three-dimensional phase change memory having two stacked memory cells according to the related art and in an embodiment of the invention;

FIG. 9a is a diagram illustrating an exemplary distribution of placement areas of functional devices corresponding to 4 adjacent memory cell blocks in a three-dimensional phase change memory having two stacked memory cells according to an embodiment of the present invention;

FIG. 9b is a distribution of first address lines based on FIG. 9 a;

FIG. 9c is a distribution of second address lines based on FIG. 9 a;

FIG. 9d is a distribution of third address lines based on FIG. 9 a;

fig. 10a to fig. 10n are schematic diagrams illustrating an implementation process of a method for manufacturing a three-dimensional phase change memory according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.

The three-dimensional Memory according to the embodiment of the present invention may include a three-dimensional Memory including a bit line, a word line and a Memory cell, which are staggered horizontally and vertically, and includes but is not limited to a PCM, a Ferroelectric Memory (FeRAM), a magnetic Memory (MRAM), a Resistive Random Access Memory (RRAM), and a Resistive Random Access Memory (RRAM). Hereinafter, only PCM will be described as an example.

Fig. 1 is a partial cross-sectional view of a three-dimensional phase-change memory cell array in the related art observed through a scanning electron microscope. As can be seen from fig. 1, the three-dimensional phase change memory chip is composed of a plurality of small memory cell array blocks having bit lines, word lines, and memory cells. Three-dimensional phase change memories generally include a top bit line, a word line, a bottom bit line, and a memory cell located at the intersection of the bit line and the word line. In practice, the word lines, the top bit lines and the bottom bit lines are generally formed of a constant line width (L/S) of 20nm/20nm formed after the patterning process.

To illustrate the solution of the embodiment of the present invention more clearly, a three-dimensional phase change memory is first introduced, specifically:

the three-dimensional phase change memory comprises a memory cell array and a peripheral circuit (which can be simply called CMOS); wherein the memory cell array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical applications, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, i.e., they are formed on different planes. For example, the memory cell array may be formed over peripheral circuits to reduce the chip size.

In practice, the peripheral circuitry may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating the PCM performing various operations such as read operations, write operations, erase operations, and the like. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers, and read/write circuits, among others. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated by the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data, and the data interaction is carried out with the outside through the data buffer.

In practical applications, the memory cell array is mainly used for storing data. In some embodiments, the architecture of the memory cell array may include memory cells having a one-layer stack, memory cells having a two-layer stack, memory cells having a four-layer stack, and the like.

In practical applications, each layer of memory cells may include a plurality of memory cells, and each memory cell in a memory cell layer may include a stacked PCM element, a gate element, and a plurality of electrodes. Heating or quenching the PCM element by the electrode through conduction of the gating element to switch crystalline state and amorphous state of the PCM element; the storage of data is achieved by switching between the crystalline and amorphous states of the PCM element. In practice, the material of the PCM element comprises a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the material of the gating element may comprise any suitable OTS material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, or the like; the material of the electrode may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes comprises carbon, such as amorphous carbon.

Fig. 2a to 2e are structural diagrams illustrating a three-dimensional phase change memory having one layer of memory cells according to the related art. FIG. 2a is a partial three-dimensional schematic view of the three-dimensional phase change memory; FIG. 2b is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Y-direction; FIG. 2c is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the X direction; FIG. 2d is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Z-direction; fig. 2e is a partial horizontal schematic view of a region of the peripheral circuit of the three-dimensional phase change memory, in which functional devices of the peripheral circuit are disposed, as viewed in the Z direction.

It is understood that the three-dimensional phase-change memory cell array is placed in front, the Z direction is understood as a top view direction (a direction viewed from the top bit line to the bottom bit line), the Y direction is understood as a left view direction (a direction in which the bit lines extend), the X direction is understood as a front view direction (a direction in which the word lines extend), and the partial isometric view of the three-dimensional phase-change memory cell array shown in fig. 2a is an isometric view viewed from the left view direction.

With reference to fig. 2 a-2 d, the three-dimensional phase change memory with one layer of memory cells includes: memory cell arrays and CMOS; wherein, the memory cell array includes: a plurality of bottom bit lines 11 in parallel and a plurality of top word lines 13 in parallel, a plurality of memory cells 12 between the plurality of bottom bit lines 11 and the plurality of top word lines 13; the bottom bit line 11 is perpendicular to the top word line 13, and the memory cell 12 is perpendicular to both the bottom bit line 11 and the top word line; the top word line 13 includes a third sub-address line 13-1 and a fourth sub-address line 13-2 arranged in a stack; each memory cell may include a stacked first electrode 101, a PCM element 102, a second electrode 103, a gate element 104, and a third electrode 105. In practical applications, the up-down positional relationship between the PCM element 102 and the gating element 104 is not limited. The three-dimensional phase change memory having one layer of memory cells further includes: a top word line connecting portion 131 (here, the english language of the connecting portion may be expressed as Contact, and the connecting portion may also be referred to as a Contact) which is in Contact with the top word line 13 and extends from between two adjacent bottom bit lines 11, and is used for connecting the top word line 13 to a functional device of a peripheral circuit, such as a decoder; a bottom bit line connection 111 in contact with the bottom bit line 11 for enabling connection of the bottom bit line 11 to a functional device of a peripheral circuit, such as a decoder.

In the three-dimensional phase change memory having one layer of memory cells shown in fig. 2a to 2d, each bit line connection portion and each word line connection portion penetrate vertically (in the Z direction) from the memory cell array portion into the peripheral circuit portion. And in order to ensure that the contact area of each bit line connection portion and each word line connection portion with the decoder in the functional device of the peripheral circuit is large enough to achieve sufficient contact, as shown in fig. 2d, the contact positions of the adjacent bottom bit line connection portions 111 and the corresponding two bottom bit lines 11 have a certain offset in the Y direction, and the contact positions of the adjacent top word line connection portions 131 and the corresponding two top word lines 13 have a certain offset in the X direction.

Fig. 2e shows the distribution of the setting areas of the functional devices corresponding to the architecture of fig. 2 d. In fig. 2e, each dashed line box shows the distribution of the setting regions of the functional devices corresponding to one memory cell block. The memory cell array block herein is a minimum unit in a memory cell array of the three-dimensional memory, on the basis of which the memory cell array is arranged to extend in the X direction and the Y direction, respectively, to form the memory cell array of the three-dimensional memory. The functional devices comprise a bit line functional device and a word line functional device; wherein the bit line function device is respectively connected to all bit lines in the memory cell array block through corresponding bit line connection parts, and can selectively activate the corresponding bit lines; the word line function devices are respectively connected to all word lines in the memory cell array block through corresponding word line connection portions, and are capable of selectively activating the corresponding word lines.

It should be noted that, in practical applications, the number of memory cell blocks of the three-dimensional phase change memory having one layer of memory cells is not limited to 2 shown in fig. 2 d; the number of the arrangement regions of the functional device of the three-dimensional phase change memory having one layer of memory cells is also not limited to 9 shown in fig. 2 e.

In the three-dimensional phase change memory having one layer of memory cells shown in fig. 2a to 2d, the thickness of the bottom bit line 11 is about half of the thickness of the top word line 13, and in order to ensure that the resistances of the bottom bit line 11 and the top word line 13 are equivalent, the length of the bottom bit line 11 in the first direction is about half of the length of the top word line 13 in the second direction, such that the number of bit lines in a single memory cell array block is twice the number of word lines. In practical applications, because the bit line functional device corresponding to the bottom bit line 11 and the word line functional device corresponding to the top word line 13 must be located below the cell array block, when the occupied space size of a single memory cell array block is small, the CMOS area corresponding to the single memory cell array block is also very limited (i.e., the projection area on the plane formed by the single memory cell array block along the X and Y directions is limited), and the limited area may not be able to meet the requirements of the next generation chip size and circuit complexity.

Based on this, an embodiment of the present invention provides a three-dimensional memory, including: at least one memory cell array block;

Fig. 3 a-3 c are architecture diagrams illustrating a three-dimensional phase change memory having one layer of memory cells according to an embodiment of the present invention. FIG. 3a is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Y direction; FIG. 3b is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the X direction; FIG. 3c is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Z-direction.

Here, the first address line layer and the second address line layer may each include a word line layer or a bit line layer, but both must be different. Illustratively, the first address line layer may include a word line layer, and correspondingly the second address line layer may include a bit line layer; alternatively, the first address line layer may comprise a bit line layer and the corresponding second address line layer may comprise a word line layer. In practical application, the bit line layer can be understood as a structure formed by a plurality of bit lines located on the same plane; the word line layer may be understood as a structure in which a plurality of word lines are formed in the same plane. In embodiments of the present invention, the first address line layer is parallel to the second address line layer.

Here, each of the first address line and the second address line may include a plurality of word lines or bit lines, but they must be different. Illustratively, the first address line may include a plurality of word lines, and the second address line may correspondingly include a plurality of bit lines; alternatively, the first address line may include a plurality of bit lines and the corresponding second address line may include a plurality of word lines.

Here, the first direction is a direction in which the first address line extends, the second direction is a direction in which the second address line extends, and the first direction is perpendicular to the second direction, that is, the first address line is perpendicular to the second address line. In practical applications, for convenience of understanding, the first address line is taken as a first bit line, the first direction is a Y direction, the second address line is taken as a first word line, and the second direction is an X direction.

Here, each of the plurality of memory cells located between the first address line layer and the second address line layer is perpendicular to the respective first address line and the second address line. The specific structure of each memory cell has been described above, and is not described herein again.

Here, the length of the first address line in the first direction and the length of the second address line in the second direction may be substantially the same, which means that the length of the first address line in the Y direction and the length of the second address line in the X direction may be equal, but a certain difference is allowed within a certain error range. In particular, the length of the error range may include a small design error range that allows for a small number of memory cells to be coupled between the first address line and the second address line, provided that both the first address line and the second address line are capable of coupling to the same number of memory cells; the length error range may also include error differences due to manufacturing. The length error range includes, but is not limited to, the above two cases.

The resistance of the first address line and the resistance of the second address line are substantially the same, which is to be understood as meaning that the resistance of the first address line and the resistance of the second address line may be equal, but a certain difference is allowed within a certain error range. In particular, the resistance error range may include a fine design error range that does not affect the electrical performance of the first address line and the second address line, provided that both the first address line and the second address line are capable of coupling to the same number of memory cells. The resistance error range may also include manufacturing-induced error variations. The resistance error range includes, but is not limited to, the above two cases.

It can be understood that, on the basis of the related art, the length of the first address line in the Y direction in the embodiment of the present invention is increased by about one time, so that the memory cells in a single memory cell array block are increased by about two times, that is, the occupied space size of the single memory cell array block is also increased by about one time, the area in which the functional devices of the peripheral circuit corresponding to the single memory cell array block can be arranged is also increased by about one time, and the increased area can better meet the requirements of the next generation chip size and circuit complexity.

Here, in order to make the resistances of the first address line and the second address line comparable, the thickness and material of the first address line and/or the second address line may be adjusted accordingly.

In some embodiments, the first address line comprises a first sub-address line and a second sub-address line which are arranged in a stacked mode, and the materials of the first sub-address line and the second sub-address line are the same or different;

and/or the presence of a gas in the gas,

In practice, as shown in FIGS. 3 a-3 c, the first address line may be arranged in a two-layer structure including the first sub-address line 11-1 and the second sub-address line 11-2, and the second address line may be arranged in a two-layer structure including the third sub-address line 13-1 and the fourth sub-address line 13-2.

Here, the materials constituting the first sub-address line 11-1, the second sub-address line 11-2, the third sub-address line 13-1, and the fourth sub-address line 13-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto.

It is to be understood that the first sub-address line 11-1 and the second sub-address line 11-2 are in parallel relationship, and the third sub-address line 13-1 and the fourth sub-address line 13-2 are also in parallel relationship. The provision of the sub-address lines may allow for a more precise adjustment of the resistance of the address lines. The materials of the first sub-address line 11-1, the second sub-address line 11-2, the third sub-address line 13-1 and the fourth sub-address line 13-2 can be selected in various ways according to different requirements of the phase change memory, and in order to ensure that the resistances of the first address line and the second address line are equivalent, the thicknesses of the first sub-address line 11-1, the second sub-address line 11-2, the third sub-address line 13-1 and the fourth sub-address line 13-2 can be adjusted correspondingly according to the selected materials.

Illustratively, when the materials of the first address line and the second address line are the same, the first address line and the second address line may be provided with comparable thicknesses to ensure that the lengths of the first address line and the second address line are the same and the resistances are comparable.

Illustratively, when the material of the first sub-address line 11-1 and the material of one of the second sub-address lines 11-2 are the same as the material of the second address line, and the material of the first sub-address line 11-1 and the material of the second sub-address line 11-2 are different, the resistances of the first sub-address line 11-1 and the second sub-address line 11-2 with the same thickness are different, and the first address line and the second address line should be set with different thicknesses according to the relation between the material thickness and the resistance to ensure that the lengths of the first address line and the second address line are the same and the resistances are equivalent.

In some embodiments, one memory cell includes a phase change memory PCM element, a gating element, and a plurality of electrodes arranged in a stack.

As can be seen from fig. 2d, since both the bottom bit line connection portion 111 and the top word line connection portion 131 vertically enter the peripheral circuits, based on this, in one memory cell array block, a vertical stripe region shown by a vertical dashed line box in fig. 2d is left between the two bottom bit lines 11 located in the middle in order to extend into the peripheral circuits avoiding the top word line connection portion 131 corresponding to the top word line 13, in which no bit line and no memory cell are provided for data storage. The vertical bars correspond to dedicated areas of the word line function device, namely the illustrated

areas

3 and 4 in fig. 2 e. Also in a memory cell array block, the middle two top word lines 13 have vertical bars (corresponding to the horizontal dashed line box in fig. 2 d) between them dedicated to the placement of dedicated regions for bit line functional devices, including

regions

1 and 2 shown in fig. 2 e.

It is understood that the vertical bar provided to extend the word line connection portion and the bit line connection portion occupies a large portion of the area of the substrate, but any word line, bit line or memory cell is not provided for data storage, and thus, the presence of the vertical bar reduces the array efficiency, i.e., the three-dimensional phase change memory having one layer of memory cells has a problem of low array efficiency.

Based on this, in some embodiments, the three-dimensional memory further includes functional devices of peripheral circuitry;

the first functional device is arranged on the first area and the second area; the second functional device is arranged on the third area, the fourth area, the fifth area and the sixth area; the projection of the first area and the second area in a second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the projection lengths of the first area, the second area, the third area, the fourth area, the fifth area and the sixth area in the second direction are equal to the projection lengths of the first area and the second area in the second direction, and the projection lengths of the first area, the second area, the third area, the fourth area, the fifth area and the sixth area in the first direction are equal to the projection lengths of the third area, the fourth area, the fifth area and the sixth area in the first direction.

In some embodiments, the functional device comprises a decoder.

Here, the three-dimensional memory includes functional devices of peripheral circuits in addition to the memory cell array block; wherein the memory cell array includes at least one memory cell array block, and the functional device of the peripheral circuit includes at least one decoder. In practical applications, in order to avoid insufficient driving force or excessive line loss, one memory cell array block corresponds to one decoder, that is, one decoder is responsible for controlling activation of all word lines and bit lines in one memory cell array block. In an embodiment of the invention, the memory cell array is configured to have at least one layer of memory cells.

Here, the functional devices include a first functional device (first bit line functional device) coupled to a first address line and a second functional device (first word line functional device) coupled to a second address line. In the embodiment of the invention, the area where the word line function device corresponding to one memory cell array is located is divided into four parts and is shifted, and the area where the bit line function device corresponding to one memory cell array is located is divided into two parts and is shifted, so that the bit lines, the word lines and the memory cells are introduced above the area where the word line function device is located and the area where the bit line function device is located, and thus, the array efficiency of the three-dimensional memory is greatly improved.

The specific distribution of the word line functional devices and the bit line functional devices corresponding to one memory cell array will be described in detail below.

Fig. 4a to fig. 4g are several different distribution situations of the setting regions of the functional devices corresponding to one memory cell block in the three-dimensional memory having one layer of memory cells according to the embodiment of the present invention. The dashed black lines in fig. 4 a-4 g represent the substrate area occupied by the footprint of a functional device in an embodiment of the present invention.

In connection with fig. 4 a-4 g, it can be appreciated that in an embodiment of the present invention, the first functional device is disposed on the first region (region 1 shown in fig. 4 a-4 g) and the second region (region 2 shown in fig. 4 a-4 g), and the second functional device is disposed on the third region (region 3 shown in fig. 4 a-4 g), the fourth region (region 4 shown in fig. 4 a-4 g), the fifth region (region 5 shown in fig. 4 a-4 g), and the sixth region (region 6 shown in fig. 4 a-4 g). In practical application, the first area, the second area, the third area, the fourth area, the fifth area and the sixth area are all square areas and are located at non-overlapping positions in the same plane.

Here, the end point may be understood as an end point of a projection line segment formed by projecting each region in the corresponding direction. The projection of the first region in the second direction and the projection of the second region in the second direction have a common endpoint can be understood as follows: the first region and the second region are seamlessly connected along the second direction, so that the occupied size of a functional device arrangement region along the second direction can be reduced relative to that of fig. 2 e. The projection of the third region in the first direction and the projection of the fourth region in the first direction have a common end point, which may be understood as seamless connection between the third region and the fourth region in the first direction, the projection of the fourth region in the first direction and the projection of the fifth region in the first direction have a common end point, which may be understood as seamless connection between the fourth region and the fifth region in the first direction, and the projection of the fifth region in the first direction and the projection of the sixth region in the first direction have a common end point, which may be understood as seamless connection between the fifth region and the sixth region in the first direction, so that, with respect to fig. 2e, the size of one functional device arrangement region in the first direction may be reduced.

Here, the projection lengths of the first, second, third, fourth, fifth and sixth regions in the second direction are equal to the projection lengths of the first and second regions in the second direction, and it can be understood that the length of the arrangement region of the functional device corresponding to a single memory cell array block in the second direction is the total length of the first and second regions in the second direction. The projection lengths of the first region, the second region, the third region, the fourth region, the fifth region and the sixth region in the first direction are equal to the projection lengths of the third region, the fourth region, the fifth region and the sixth region in the first direction, and it can be understood that the length of the setting region of the functional device corresponding to a single memory cell array block in the first direction is the total length of the third region, the fourth region, the fifth region and the sixth region in the first direction.

In some embodiments, the first address lines of the plurality of first address lines are equally spaced along the second direction; the pitch of each second address line in the plurality of second address lines along the first direction is the same.

In the embodiment of the present invention, no relevant vacancy needs to be left between the two bit lines in the middle, and no relevant vacancy needs to be left between the two word lines in the middle. That is, the pitches of the first address lines in the second direction are the same, and the pitches of the second address lines in the first direction are the same. In practice, the layout of the bit lines and word lines can be found in the right diagram of FIG. 4 h. The left side of fig. 4h illustrates the layout of the bit lines and word lines corresponding to fig. 2 e.

In some embodiments, the three-dimensional memory further comprises: a first connection portion contacting the first address line and a second connection portion contacting the second address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block through corresponding first connection portions, and the second functional devices are respectively connected to all second address lines in the memory cell array block through corresponding second connection portions;

and/or the presence of a gas in the gas,

In practice, the first functional devices are connected to all first address lines in the memory cell array block through corresponding first connection portions in contact with the first address lines, respectively, and the second functional devices are connected to all second address lines in the memory cell array block through corresponding second connection portions in contact with the second address lines, respectively. It will be appreciated that when the first connection contacts the geometric center of the first address line and the second connection contacts the geometric center of the second address line, the overall architecture is more uniformly symmetrical, interconnect routing difficulties, and bit line parasitic series resistance are lower.

In practical applications, the contact between the first connection portion and the geometric center of the first address line and the contact between the second connection portion and the geometric center of the second address line may be as shown in the right diagram of fig. 4 h.

In some embodiments, the three-dimensional memory further includes an interconnection layer through which the functional devices are connected with the respective connection portions.

Here, when the first connection portion contacts with the geometric center of the first address line and the second connection portion contacts with the geometric center of the second address line, the first connection portion and the second connection portion do not directly land on the corresponding functional device disposition region to connect with the corresponding functional device while being vertically downward. At this time, the first connection portion and the second connection portion may be connected to the respective functional devices through the interconnection layer. In practical applications, reference may be made to fig. 5. It should be noted that the connection relationship between the word lines or the bit lines and the corresponding functional devices in fig. 5 is only used for illustrating the connection manner, and is not used to limit the specific connection structure in the embodiment of the present invention.

Fig. 6a to 6e are structural diagrams illustrating a three-dimensional phase change memory having two layers of memory cells provided in the related art. FIG. 6a is a partial three-dimensional schematic view of the three-dimensional phase change memory; FIG. 6b is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Y-direction; FIG. 6c is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the X-direction; FIG. 6d is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Z-direction; fig. 6e is a partial horizontal schematic view of a region for disposing a functional device in the peripheral circuit of the three-dimensional phase change memory viewed in the Z direction.

It is understood that the three-dimensional phase-change memory cell array is placed in front, the Z direction is understood as a top-view direction (a direction viewed from a top bit line to a bottom bit line), the Y direction is understood as a left-view direction (a direction in which bit lines extend), the X direction is understood as a front-view direction (a direction in which word lines extend), and the partial isometric view of the three-dimensional phase-change memory cell array shown in fig. 6a is an isometric view viewed from the left-view direction.

With reference to fig. 6a to 6d, the three-dimensional phase change memory with two layers of memory cells includes: memory cell arrays and CMOS; wherein, the memory cell array includes: a plurality of bottom bit lines 21 in parallel, a plurality of word lines 23 in parallel, a plurality of top bit lines 25 in parallel, a plurality of bottom memory cells 22 between the plurality of bottom bit lines 21 and the plurality of word lines 23, and a plurality of top memory cells 24 between the plurality of word lines 23 and the plurality of top bit lines 25. There is an offset between the top bit line 25 and the corresponding bottom bit line 21 (one bottom bit line below the top bit line). In practice, the offset here may refer to the offset shown in fig. 6b, which shows half the bit line length along the Y direction. The bottom bit line 21, the top bit line 25 are both perpendicular to the word line 23, the bottom memory cell 22 is perpendicular to the bottom bit line 21 and the word line 23, and the top memory cell 24 is perpendicular to the word line 23 and the top bit line 25; each memory cell may include a first electrode 201, a PCM element 202, a second electrode 203, a gating element 204, and a third electrode 205 stacked. In practical applications, the up-down positional relationship between the PCM element 202 and the gating element 204 is not limited. The three-dimensional phase change memory with two layers of memory cells further comprises: a top bit line connection portion 251 which is in contact with the top bit line 25 and extends between the adjacent two word lines 23 and the adjacent two bottom bit lines 21, for implementing a function of the top bit line 25 and a peripheral circuit, such as a decoder connection; a word line connection portion 231 which is in contact with the word line 23 and extends from between the adjacent two bottom bit lines 21 for realizing connection of the word line 23 and a functional device of a peripheral circuit, such as a decoder; a bottom bit line connection 211 in contact with the bottom bit line 21 for enabling connection of the bottom bit line 21 to a functional device of a peripheral circuit, such as a decoder.

It should be noted that the top bit lines 25 and the corresponding bottom bit lines 21 may have no offset or a small offset along the X direction, and in fig. 6d, in order to fully show the top bit lines 25 and the corresponding bottom bit lines 21, the top bit lines 25 and the corresponding bottom bit lines 21 are arranged to have an offset along the X direction.

In the three-dimensional phase change memory having two layers of memory cells shown in fig. 6a to 6d, each bit line connection portion and each word line connection portion penetrate vertically (in the Z direction) from the memory cell array portion into the peripheral circuit portion. And in order to ensure that the contact area of each bit line connection portion and each word line connection portion with the functional device in the peripheral circuit is large enough to achieve sufficient contact, as shown in fig. 6d, the contact positions of the adjacent bottom bit line connection portions 211 and the corresponding two bottom bit lines 21 have a certain offset in the Y direction, the contact positions of the adjacent word line connection portions 231 and the corresponding two word lines 23 have a certain offset in the X direction, and the contact positions of the adjacent top bit line connection portions 251 and the corresponding two top bit lines 25 have a certain offset in the Y direction.

Fig. 6e shows the distribution of the setting areas of the functional devices corresponding to the architecture of fig. 6 d. The distribution of the placement area of the functional devices corresponding to one memory cell block is shown in each dashed line box in fig. 6 e. The memory cell array block herein is a minimum unit in a memory cell array of the three-dimensional memory, on the basis of which the memory cell array is arranged to extend in the X direction and the Y direction, respectively, to form the memory cell array of the three-dimensional memory. The functional devices comprise a bottom bit line functional device, a word line functional device and a top bit line functional device; wherein the bottom bit line functional devices are connected to all bottom bit lines in the memory cell array block, respectively, by respective bottom bit line connections, and are capable of selectively activating respective bottom bit lines 21; the word line function devices are respectively connected to all word lines in the memory cell array block through corresponding word line connection portions, and are capable of selectively activating the corresponding word lines 23; the top bit line functional devices are respectively connected to all top bit lines in the memory cell array block through respective top bit line connections and are capable of selectively activating the respective top bit lines 25.

It should be noted that, in practical applications, the number of memory cell blocks of the three-dimensional phase change memory having two layers of memory cells is not limited to 2 shown in fig. 6 d; the number of the arrangement regions of the functional device of the three-dimensional phase change memory having two layers of memory cells is also not limited to 9 shown in fig. 6 e.

In the three-dimensional phase change memory having one layer of memory cells shown in fig. 6a to 6d, the thickness of the bottom bit lines 21 and the top bit lines 25 is about one-half of the thickness of the word lines 23, and in order to ensure that the resistances of the bottom bit lines 21, the top bit lines 25 and the word lines 23 are equivalent, the lengths of the bottom bit lines 21 and the top bit lines 25 in the first direction are about one-half of the lengths of the word lines 23 in the second direction, such that the number of top bit lines or the number of bottom bit lines in a single memory cell array block is twice the number of word lines. In practical applications, because the bottom bit line 21, the bit line functional device corresponding to the top bit line 25, and the word line functional device corresponding to the word line 23 all have to be located below the cell array block, when the occupied space size of a single memory cell array block is small, the CMOS area corresponding to the single memory cell array block is also very limited (i.e., the projection area on the plane formed by the single memory cell array block along the X and Y directions is limited), and the limited area may not be able to meet the requirements of the next generation chip size and circuit complexity.

Based on this, an embodiment of the present invention provides a three-dimensional memory, where on the basis of the three-dimensional memory having one layer of storage units, the storage unit array block further includes: stacking a plurality of second phase change memory cells and a third address line layer disposed on the second address line layer; wherein the third address line layer is parallel to the second address line layer; the third address line layer includes a plurality of third address lines each extending in a first direction; the third address line is overlapped with the projection part of the first address line on the first plane; the second phase change memory unit is vertical to the second address line and the third address line; the first plane is perpendicular to the stacking direction;

Fig. 7 a-7 c are architecture diagrams illustrating a three-dimensional phase change memory having one layer of memory cells according to an embodiment of the present invention. FIG. 7a is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Y-direction; FIG. 7b is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the X-direction; FIG. 7c is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Z-direction.

Here, a plurality of second phase change memory cells and a third address line layer, which are newly added, are further introduced on the basis of the aforementioned three-dimensional memory having one layer of memory cells. In an embodiment of the invention, the memory cell array is configured to have at least two layers of memory cells.

Here, the third address line layer may include a word line layer or a bit line layer, but must be the same as the first address line layer. Illustratively, the first address line layer may include a word line layer, and correspondingly the third address line layer also includes a word line layer; alternatively, the first address line layer may include a bit line layer and the corresponding third address line layer may include a bit line layer. In an embodiment of the present invention, the first address line layer, the second address line layer, and the third address line layer are all parallel to each other.

Here, the third address line may include a plurality of word lines or bit lines, but must be the same as the first address line. For example, the first address line may include a plurality of word lines, and the third address line may also include a plurality of word lines; alternatively, the first address line may include a plurality of bit lines, and the corresponding third address line may also include a plurality of bit lines.

Here, the first direction is a direction in which the first address line extends, the second direction is a direction in which the second address line extends, and the first direction is perpendicular to the second direction, that is, the first address line is perpendicular to the second address line. In practical applications, for convenience of understanding, the first address line is taken as a first bit line, the first direction is a Y direction, the second address line is a first word line, the second direction is an X direction, and the third address line is taken as a second bit line.

Here, the first plane may include a plane parallel to a plane formed by the first direction and the second direction, that is, a plane parallel to a plane formed by the X, Y direction. The projection of the third address lines and the projection of the first address lines on the first plane are overlapped, which may be understood as that each third address line and the corresponding first address line have an offset in the first plane and along the Y direction, and the offset may be the length of half of the first address line, or may be another amount.

Here, each of a plurality of first memory cells located between the first address line layer and the second address line layer is perpendicular to the respective first address line and the second address line; each memory cell of the plurality of second memory cells located between the second address line layer and the third address line layer is perpendicular to the respective second address line and third address line. The specific structure of each memory cell has been described above, and is not described herein again.

Here, a length of the third address line in the first direction is substantially the same as a length of the second address line in the second direction, and a resistance of the third address line is substantially the same as that of the second address line. It is understood that the length of the second address line in the X direction and the length of the third address line in the Y direction may be equal, but a certain difference is allowed within a certain error range. Specifically, the error range of the length may include a small design error range that is allowed to exist between the second address line and the third address line on the premise that the second address line and the third address line can be coupled with the same number of memory cells; the length error range may also include error differences due to manufacturing. The length error range includes, but is not limited to, the above two cases.

The resistance of the third address line and the resistance of the second address line are substantially the same, which is to be understood as meaning that the resistance of the third address line and the resistance of the second address line may be equal, but a certain difference is allowed within a certain error range. In particular, the resistance error range may include a fine design error range that does not affect the electrical performance of the third address line and the second address line, provided that both the third address line and the second address line are capable of coupling to the same number of memory cells. The resistance error range may also include manufacturing-induced error variations. The resistance error range includes, but is not limited to, the above two cases.

It can be understood that, on the basis of the related art, the length of the third address line in the Y direction in the embodiment of the present invention is increased by one time, so that the memory cells in a single memory cell array block are increased by two times in the related art, that is, the occupied space size of the single memory cell array block is also increased by about one time, the area in which the functional devices of the peripheral circuit corresponding to the single memory cell array block can be arranged is also increased by about one time, and the increased area can better meet the requirements of the next generation chip size and circuit complexity.

Here, in order to make the resistances of the third address line and the second address line comparable, the thickness and material of the third address line and/or the second address line may be adjusted accordingly.

and/or the presence of a gas in the gas,

the second address line includes a third sub-address line and a fourth sub-address line arranged in a cascade, and the materials of the third sub-address line and the fourth sub-address line are the same or different.

In practice, as shown in FIGS. 7 a-7 c, the first address line may be arranged in a two-layer structure including the first sub-address line 21-1 and the second sub-address line 21-2, the second address line may be arranged in a two-layer structure including the third sub-address line 23-1 and the fourth sub-address line 23-2, and the third address line may be arranged in a two-layer structure including the fifth sub-address line 25-1 and the sixth sub-address line 25-2.

Here, the materials constituting the first sub-address line 21-1, the second sub-address line 21-2, the third sub-address line 23-1, the fourth sub-address line 23-2, the fifth sub-address line 25-1, and the sixth sub-address line 25-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto.

It is understood that the first sub-address line 21-1 and the second sub-address line 21-2 are in parallel, the third sub-address line 23-1 and the fourth sub-address line 23-2 are in parallel, and the fifth sub-address line 25-1 and the sixth sub-address line 25-2 are in parallel. The provision of the sub-address lines may allow for a more precise adjustment of the resistance of the address lines. The materials of the first sub-address line 21-1, the second sub-address line 21-2, the third sub-address line 23-1, the fourth sub-address line 23-2, the fifth sub-address line 25-1 and the sixth sub-address line 25-2 can be selected in various ways according to different requirements of the phase change memory, and in order to ensure that the resistances of the first address line, the second address line and the third address line are equivalent, the thicknesses of the first sub-address line 21-1, the second sub-address line 21-2, the third sub-address line 23-1, the fourth sub-address line 23-2, the fifth sub-address line 25-1 and the sixth sub-address line 25-2 can be adjusted correspondingly according to the selected materials.

Illustratively, when the materials of the third address line and the second address line are the same, the third address line and the second address line may be provided with comparable thicknesses to ensure that the third address line and the second address line have the same length and comparable resistance.

Illustratively, when one of the materials of the fifth sub-address line 25-1 and the sixth sub-address line 25-2 is the same as the material of the second address line, and the material of the fifth sub-address line 25-1 is different from the material of the sixth sub-address line 25-2, the resistances of the fifth sub-address line 25-1 and the sixth sub-address line 25-2 with the same thickness are different, and the third address line and the second address line should be set with different thicknesses according to the relationship between the material thickness and the resistance to ensure that the lengths of the third address line and the second address line are the same and the resistances are equivalent.

As can be seen from fig. 6d, since the bottom bit line connection portions 211, the word line connection portions 231, and the top bit line connection portions 251 all vertically enter the peripheral circuits, based on this, in one memory cell array block, a vertical stripe region shown by a vertical dashed line box in fig. 6d is left between the two bottom bit lines 21 located in the middle in order to extend into the peripheral circuits avoiding the word line connection portions 231 corresponding to the word lines 23, in which no bit line and no memory cell are provided for data storage. The vertical bars correspond to dedicated areas of the word line function device, namely the illustrated

areas

3 and 4 in fig. 6 e. Also, in a memory cell array block, the middle two word lines 23 have vertical bars between them that correspond to dedicated areas dedicated to the placement of bottom bit line functional devices, including the area 1 and the area 2 shown in fig. 6 e. At the same time, the corresponding vertical bars of the dedicated area dedicated to the placement of the top bit line functional device, including the illustrated area 7 and the area 8 in fig. 6e, are also left out between two adjacent memory cell array blocks.

It is understood that the vertical bar provided to extend the word line connection portion and the bit line connection portion occupies a large portion of the area of the substrate, but any word line, bit line or memory cell is not provided for data storage, and thus, the presence of the vertical bar reduces the array efficiency, i.e., the three-dimensional phase change memory having two layers of memory cells has a problem of low array efficiency.

Based on this, in some embodiments, the three-dimensional memory further comprises functional devices of peripheral circuitry;

In the embodiment of the invention, the area where the first word line functional device corresponding to one memory cell array is located is divided into four parts and is shifted, the area where the first bit line functional device corresponding to one memory cell array is located is divided into two parts and is shifted, and the area where the second bit line functional device corresponding to one memory cell array is located is divided into two parts and is shifted, so that bit lines, word lines and memory cells are introduced above the area where the word line functional device is located and the area where the corresponding bit line functional device is located, and thus, the array efficiency of the three-dimensional memory is greatly improved.

Fig. 8a to 8e are several different distribution situations of the setting regions of the functional devices corresponding to one memory cell block in the three-dimensional memory having two layers of memory cells according to the embodiment of the present invention. The dashed black lines in fig. 8 a-8 e represent the substrate area occupied by the placement area of one functional device in an embodiment of the present invention.

With reference to fig. 8a to 8e, it can be understood that, in the embodiment of the present invention, the first functional device is provided on the first region (region 1 shown in fig. 8a to 8 e) and the second region (region 2 shown in fig. 8a to 8 e), and the second functional device is provided on the third region (region 3 shown in fig. 8a to 8 e), the fourth region (region 4 shown in fig. 8a to 8 e), the fifth region (region 5 shown in fig. 8a to 8 e), the sixth region (region 6 shown in fig. 8a to 8 e). The third functional device is provided on the seventh area (area 7 shown in fig. 8a to 8 e) and the eighth area (area 8 shown in fig. 8a to 8 e). In practical application, the first region, the second region, the third region, the fourth region, the fifth region, the sixth region, the seventh region and the eighth region are square regions and are located at positions which are not overlapped with each other in the same plane.

Here, the end point may be understood as an end point of a projection line segment formed by projecting each region in the corresponding direction. The projection of the first region in the second direction and the projection of the second region in the second direction have a common endpoint may be understood as follows: the first region and the second region are seamlessly connected along the second direction, so that the occupied size of a functional device arrangement region along the second direction can be reduced compared with that of fig. 6 e. The projection of the third region in the first direction and the projection of the fourth region in the first direction have a common end point, which may be understood as seamless connection between the third region and the fourth region in the first direction, the projection of the fourth region in the first direction and the projection of the fifth region in the first direction have a common end point, which may be understood as seamless connection between the fourth region and the fifth region in the first direction, and the projection of the fifth region in the first direction and the projection of the sixth region in the first direction have a common end point, which may be understood as seamless connection between the fifth region and the sixth region in the first direction, so that the size of one functional device arrangement region in the first direction may be reduced with respect to fig. 6 e. Meanwhile, the projection of the seventh area in the second direction and the projection of the eighth area in the second direction have a common end point, which can be understood as that the seventh area and the eighth area are seamlessly connected along the second direction, so that, compared with fig. 6e, the size occupied by one functional device installation area along the second direction can be reduced.

Here, the projection lengths of the first region, the second region, the third region, the fourth region, the fifth region, the sixth region, the seventh region and the eighth region in the second direction are equal to the projection lengths of the seventh region and the eighth region in the second direction, and it can be understood that the length of the arrangement region of the functional device corresponding to a single memory cell array block in the second direction is the total length of the seventh region and the eighth region in the second direction. The projection length of the first region, the second region, the third region, the fourth region, the fifth region, the sixth region, the seventh region, and the eighth region in the first direction is equal to the projection length of the third region, the fourth region, the fifth region, and the sixth region in the first direction, and it can be understood that the length of the setting region of the functional device corresponding to a single memory cell array block in the first direction is the total length of the third region, the fourth region, the fifth region, and the sixth region in the first direction.

In some embodiments, the first address lines of the plurality of first address lines are equally spaced along the second direction; the pitches of the second address lines in the first direction are the same; and the pitches of the third address lines in the second direction are the same.

In the embodiment of the invention, no relevant vacant position needs to be reserved between the two bit lines in the middle, and no relevant vacant position needs to be reserved between the two word lines in the middle. That is, the pitches of the first address lines in the first direction are the same, the pitches of the second address lines in the second direction are the same, and the pitches of the third address lines in the third direction are the same. In practice, the layout of the bit lines and word lines can be seen with reference to the right diagram of fig. 8 f. The left side of fig. 8f illustrates the layout of the bit lines and word lines corresponding to fig. 6 e.

To further explain the arrangement of the first address line, the second address line and the third address line in this embodiment, a distribution manner of the setting region of the functional device corresponding to one memory cell block shown in fig. 8b is taken as an example to be described in detail below.

FIG. 9a is a diagram illustrating an exemplary distribution of placement areas of functional devices corresponding to 4 adjacent blocks of memory cells in a three-dimensional memory having two levels of memory cells; FIG. 9b is a distribution of first address lines based on FIG. 9 a; FIG. 9c is a distribution of second address lines based on FIG. 9 a; fig. 9d shows a distribution of third address lines on the basis of fig. 9 a.

In some embodiments, the three-dimensional memory further comprises: a first connection portion contacting the first address line, a second connection portion contacting the second address line, and a third connection portion contacting the third address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block by corresponding first connecting portions, the second functional devices are respectively connected to all second address lines in the memory cell array block by corresponding second connecting portions, and the third functional devices are respectively connected to all third address lines in the memory cell array block by corresponding third connecting portions; the first connecting part is contacted with the geometric center of the first address wire; the third connecting part is contacted with the geometric center of the third address line;

and/or the presence of a gas in the gas,

In practice, the first functional devices are connected to all first address lines in the memory cell array block by corresponding first connecting portions in contact with first address lines, the second functional devices are connected to all second address lines in the memory cell array block by corresponding second connecting portions in contact with second address lines, and the third functional devices are connected to all third address lines in the memory cell array block by corresponding third connecting portions in contact with third address lines. It can be understood that when the first connection part is contacted with the geometric center of the first address wire, the second connection part is contacted with the geometric center of the second address wire, and the third connection part is contacted with the geometric center of the third address wire, the whole structure is more uniform and symmetrical, the interconnection wiring difficulty is lower, and the parasitic series resistance of the bit line is smaller.

In practical applications, the first connection portion contacts with the geometric center of the first address line, the second connection portion contacts with the geometric center of the second address line, and the third connection portion contacts with the geometric center of the third address line, as shown in the right diagram of fig. 8 f.

In practical application, when the first connecting part contacts with the geometric center of the first address wire; a third connection portion is in contact with a geometric center of the third address line; and/or when the second connecting part is contacted with the geometric center of the second address line, the first connecting part, the second connecting part and the third connecting part cannot directly land on the setting area of the corresponding functional device when vertically downwards so as to be connected with the corresponding functional device. At this time, the first connection portion, the second connection portion, and the third connection portion may be connected to the corresponding functional device through the interconnection layer.

An embodiment of the present invention provides a three-dimensional memory, including: at least one memory cell array block; the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units and a second address line layer which are arranged in a stacked mode; wherein the first address line layer is parallel to the second address line layer; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the first direction is perpendicular to the second direction; the first phase change memory cell is perpendicular to both the first address line and the second address line; the length of the first address line in a first direction is substantially the same as the length of the second address line in a second direction, and the resistance of the first address line is substantially the same as the resistance of the second address line. The length of the first address line along the first direction in the three-dimensional memory provided by the embodiment of the invention is equivalent to the length of the second address line along the second direction, so that the number of phase change memory cells in a single memory cell array block is increased, the occupied space size of the single memory cell array block is also increased, namely the area capable of being distributed by functional devices of a peripheral circuit corresponding to the single memory cell array block is also increased, and the increased area can better adapt to the requirements of the next generation chip size and circuit complexity.

Based on the three-dimensional memory, the embodiment of the invention also provides a manufacturing method of the three-dimensional memory, which comprises the following steps:

In some embodiments of the present invention, the,

and/or the presence of a gas in the gas,

In some embodiments, the method further comprises:

forming a first functional device connected to the first address line on the first area and the second area;

forming a second functional device connected to the second address line over the third region, the fourth region, the fifth region, and the sixth region;

the projection of the first area and the second area in the second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the projection lengths of the first area, the second area, the third area, the fourth area, the fifth area and the sixth area in the second direction are equal to the projection lengths of the first area and the second area in the second direction, and the projection lengths of the first area, the second area, the third area, the fourth area, the fifth area and the sixth area in the first direction are equal to the projection lengths of the third area, the fourth area, the fifth area and the sixth area in the first direction.

In some embodiments, the method further comprises:

forming a first connection portion contacting a first address line before forming the first address line; forming a second connection portion contacting the second address line before forming the second address line; wherein the content of the first and second substances,

and/or the presence of a gas in the gas,

In some embodiments, the method further comprises:

forming a plurality of third address lines of a third address line layer on the plurality of second phase change memory cells, the plurality of third address lines each extending in the first direction; the second phase change memory unit is vertical to the second address line and the third address line;

In some embodiments of the present invention, the,

and/or the presence of a gas in the gas,

the step of forming each of a plurality of second address lines of the second address line layer includes: forming a third sub-address line on the first phase change memory cell, forming a fourth sub-address line on the third sub-address line overlying the third sub-address line; the materials of the third sub-address line and the fourth sub-address line are the same or different.

In some embodiments, the method further comprises:

forming a third functional device connected to the third address line on a seventh area and an eighth area;

In some embodiments, the method further comprises:

forming a first connection portion contacting a first address line before forming the first address line; forming a second connection portion contacting the second address line before forming the second address line; forming a third connection portion contacting a third address line before forming the third address line; wherein the content of the first and second substances,

and/or the presence of a gas in the atmosphere,

The following describes the method for fabricating the three-dimensional memory according to the embodiment of the present invention in detail with reference to fig. 10a to 10 n.

As shown in fig. 10 a-10 b, a bottom bit line connection 211 is formed. A plurality of bottom bit lines are formed on the bottom bit line connection 211, the bottom bit lines including two parts: the first sub-address line 21-1 and the second sub-address line 21-2 are formed by, as shown in fig. 10 c-10 d, first forming the first sub-address line 21-1 on the bottom bit line connection portion 211, where the first sub-address line 21-1 is formed by first depositing a material for forming the first sub-address line 21-1, and then removing a portion of the material for forming the first sub-address line 21-1 by etching or the like, thereby forming the first sub-address line 21-1, or by first depositing a dielectric material, and then removing a portion of the dielectric material by etching to form a trench, and filling the trench with the material for forming the first sub-address line 21-1, thereby forming the first sub-address line 21-1. As shown in fig. 10e to 10f, the second sub-address line 21-2 is formed on the first sub-address line 21-1; and a first phase change memory cell layer 22' is formed on the second sub-address line 21-2. As shown in FIGS. 10g-10h, a first phase change memory cell 22 is formed on the second sub-address line 21-2. Forming a word line on the first phase change memory cell 22, the word line comprising two portions: third sub-address line 23-1 and fourth sub-address line 23-2, as shown in FIGS. 10g-10h, the third sub-address line 23-1 is formed on the first phase change memory cell 22, and the word line connection portion 231 is formed before the third sub-address line 23-1 is formed; as shown in fig. 10i to 10j, the fourth sub-address line 23-2 is formed on the third sub-address line 23-1. Through the manufacturing process, the three-dimensional memory with one layer of memory cells is formed.

The dielectric material includes, but is not limited to, silicon nitride and silicon oxide

Here, the method of forming the second sub-address line 21-2, the third sub-address line 23-1, and the fourth sub-address line 23-2 is similar to the aforementioned method of forming the first sub-address line 21-1, and two methods may be included, which are not described herein again.

Here, the materials constituting the first sub-address line 21-1, the second sub-address line 21-2, the third sub-address line 23-1, and the fourth sub-address line 23-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto. And the constituent materials of the first sub-address line 21-1 and the second sub-address line 21-2 may be the same or different, and the constituent materials of the third sub-address line 23-1 and the fourth sub-address line 23-2 may be the same or different.

On the basis of the above-described three-dimensional memory in which memory cells are stacked in one layer, as shown in fig. 10i to 10j, the second phase change memory cell 24 is formed on the fourth sub-address line 23-2, and the top bit line connection portion 251 is formed. Forming a top bit line on the second phase change memory cell 24, the top bit line comprising two portions: the fifth sub-address line 25-1 and the sixth sub-address line 25-2, as shown in fig. 10k-10l, form the fifth sub-address line 25-1 on the second phase change memory cell 24; as shown in fig. 10m-10n, a sixth sub-address line 25-2 is formed on the fifth sub-address line 25-1. Through the manufacturing process, the three-dimensional memory with the memory cells stacked in two layers is formed.

Here, the method of forming the fifth sub-address line 25-1 and the sixth sub-address line 25-2 is similar to the aforementioned method of forming the first sub-address line 21-1, and two methods may be included, which are not described herein again.

Here, the materials constituting the fifth sub-address line 25-1 and the sixth sub-address line 25-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto. And the composition materials of the fifth sub-address line 25-1 and the sixth sub-address line 25-2 may be the same or different.

In practical applications, methods for forming the corresponding connection portion, the address line, and the memory cell are mature in the related art, and are not described herein again.

It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A three-dimensional memory, comprising: at least one memory cell array block;

2. The three-dimensional memory according to claim 1, wherein the first address line comprises a first sub-address line and a second sub-address line which are arranged in a stacked manner, and the materials of the first sub-address line and the second sub-address line are the same or different;

and/or the presence of a gas in the atmosphere,

3. The three-dimensional memory according to claim 1, further comprising a functional device of a peripheral circuit;

the first functional device is arranged on the first area and the second area; the second functional device is arranged on the third area, the fourth area, the fifth area and the sixth area;

4. The three-dimensional memory according to claim 3, wherein the first address lines of the plurality of first address lines are equally spaced along the second direction; the pitch of each second address line in the plurality of second address lines along the first direction is the same.

5. The three-dimensional memory according to claim 3, further comprising: a first connection portion in contact with the first address line and a second connection portion in contact with the second address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block through corresponding first connection portions, and the second functional devices are respectively connected to all second address lines in the memory cell array block through corresponding second connection portions;

and/or the presence of a gas in the gas,

6. The three-dimensional memory according to claim 1, wherein the memory cell array block further comprises: stacking a plurality of second phase change memory cells and a third address line layer disposed on the second address line layer; wherein the third address line layer is parallel to the second address line layer; the third address line layer includes a plurality of third address lines each extending in a first direction; the third address line is overlapped with the projection part of the first address line on the first plane; the second phase change memory unit is vertical to the second address line and the third address line; the first plane is perpendicular to the stacking direction;

7. The three-dimensional memory according to claim 6,

and/or the presence of a gas in the gas,

8. The three-dimensional memory according to claim 6, further comprising functional devices of peripheral circuitry;

9. The three-dimensional memory according to claim 8, wherein the first address lines of the plurality of first address lines are equally spaced along the second direction; the pitches of the second address lines in the first direction are the same; and the pitches of the third address lines in the second direction are the same.

10. The three-dimensional memory according to claim 8, further comprising: a first connection portion contacting the first address line, a second connection portion contacting the second address line, and a third connection portion contacting the third address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block by corresponding first connecting portions, the second functional devices are respectively connected to all second address lines in the memory cell array block by corresponding second connecting portions, and the third functional devices are respectively connected to all third address lines in the memory cell array block by corresponding third connecting portions; the first connecting part is contacted with the geometric center of the first address wire; the third connecting part is contacted with the geometric center of the third address line;

and/or the presence of a gas in the gas,

11. The three-dimensional memory according to any one of claims 5 or 10, further comprising an interconnect layer through which the functional devices are connected with the respective connections.

12. The three-dimensional memory according to any one of claims 3 or 8, wherein the functional device comprises a decoder.

13. The three-dimensional memory according to any one of claims 1 to 10, wherein one memory cell comprises a Phase Change Memory (PCM) element, a gate element and a plurality of electrodes arranged in a stack.

14. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:

15. The method of claim 14, wherein the three-dimensional memory is formed by a single process,

forming a first sub-address line, forming a second sub-address line on the first sub-address line covering the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different;

and/or the presence of a gas in the gas,

16. The method of fabricating a three-dimensional memory according to claim 14, further comprising:

a plurality of third address lines forming a third address line layer on the plurality of second phase change memory cells, the plurality of third address lines each extending in the first direction; the second phase change memory cell is perpendicular to the second address line and the third address line;

17. The method of claim 16, wherein the three-dimensional memory is formed by a single process,

the step of forming each of a plurality of first address lines of the first address line layer includes: forming a first sub-address line, and forming a second sub-address line on the first sub-address line to cover the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different; the step of forming each of a plurality of third address lines of the third address line layer includes: forming a fifth sub-address line on the second phase change memory unit, and forming a sixth sub-address line on the fifth sub-address line to cover the fifth sub-address line; the materials of the fifth sub address line and the sixth sub address line are the same or different;

and/or the presence of a gas in the gas,