CN113437051B - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN113437051B CN113437051B CN202110985480.1A CN202110985480A CN113437051B CN 113437051 B CN113437051 B CN 113437051B CN 202110985480 A CN202110985480 A CN 202110985480A CN 113437051 B CN113437051 B CN 113437051B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
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Abstract
The application provides a semiconductor device, relates to semiconductor technology field, includes: the semiconductor layer comprises an active region and a passive region positioned at the periphery of the active region; the capacitor structure can be formed in the drain electrode test pad through the drain electrode bottom layer metal, the dielectric layer and the drain electrode top layer metal, and similarly, the capacitor structure can also be formed in the grid electrode test pad through the grid electrode bottom layer metal, the dielectric layer and the grid electrode top layer metal, and then the grid electrode bottom layer metal and the drain electrode bottom layer metal are respectively connected with the source electrode test pad through the conducting structure. Therefore, in the direct current test process, a circuit with a conductive structure and a capacitor connected in series can be formed between the source electrode test pad and the drain electrode test pad and between the source electrode test pad and the grid electrode test pad to form a leakage channel for grounding alternating current signals, and alternating current noise signals introduced by an external test circuit can be timely grounded by using the circuit, so that the self-excitation problem of the semiconductor device in the direct current test is restrained.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
With the high integration of semiconductor devices, efforts have been made to improve the yield of semiconductor devices. In the semiconductor manufacturing process, a source test pad, a drain test pad and a gate test pad are usually disposed on a device, so that a direct current test is performed on the device before a wafer is cut.
When the existing direct current test is carried out, alternating current noise is easily introduced through an external test circuit, so that the self-excitation problem of a device is easily caused when the direct current test is carried out.
Disclosure of Invention
The present application is directed to provide a semiconductor device, which utilizes a dc test pad to add a passive device, thereby suppressing the self-excitation problem of the device during dc test.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in an aspect of an embodiment of the present application, there is provided a semiconductor device including: a substrate; the semiconductor layer is arranged on the substrate and comprises an active region and a passive region positioned at the periphery of the active region; the drain electrode test pad comprises drain electrode bottom layer metal and drain electrode top layer metal which are arranged in a stacking mode, the grid electrode test pad comprises grid electrode bottom layer metal and grid electrode top layer metal which are arranged in a stacking mode, dielectric layers are arranged between the drain electrode bottom layer metal and the drain electrode top layer metal, between the grid electrode bottom layer metal and the grid electrode top layer metal, and the grid electrode bottom layer metal and the drain electrode bottom layer metal are connected with the source electrode test pad through conducting structures.
Optionally, the source test pad includes a source bottom metal and a source top metal stacked on each other, and the source bottom metal is connected to the gate bottom metal and the drain bottom metal through conductive structures, respectively.
Optionally, a dielectric layer is disposed between the source bottom layer metal and the source top layer metal.
Optionally, the conductive structure crosses the scribe line on the semiconductor layer.
Optionally, ohmic metal is respectively disposed between the gate bottom metal and the semiconductor layer, and between the drain bottom metal and the semiconductor layer, the conductive structure includes a two-dimensional electron gas resistor located in the passive region of the semiconductor layer, and the gate bottom metal and the drain bottom metal are respectively electrically connected to the source test pad through the two-dimensional electron gas resistor.
Optionally, the conductive structure further includes a first fold inductance and a second fold inductance, the gate bottom metal is connected in series with the source electrode test pad through the two-dimensional electron gas resistance and the first fold inductance, and the drain bottom metal is connected in series with the source electrode test pad through the two-dimensional electron gas resistance and the second fold inductance.
Optionally, the conductive structure includes a thin film resistor disposed in the semiconductor layer passive region, and the gate bottom metal and the drain bottom metal are electrically connected to the source test pad through the thin film resistor, respectively.
Optionally, the resistor is a meander line resistor.
Optionally, the resistor is made of tantalum nitride or nickel-chromium alloy.
Optionally, a gate routing pad is further arranged in the semiconductor layer passive region, and the gate routing pad is connected with the gate top layer metal in series through a connecting metal and a thin film resistor in sequence; and a drain routing bonding pad is also arranged in the semiconductor layer passive region and is connected with the drain bottom layer metal in series through connecting metal.
Optionally, the connection metal crosses the scribe line on the semiconductor layer.
The beneficial effect of this application includes:
the application provides a semiconductor device, including: a substrate; the semiconductor layer is arranged on the substrate and comprises an active region and a passive region positioned at the periphery of the active region; the source electrode test pad, the drain electrode test pad and the grid electrode test pad which are arranged in the semiconductor layer passive region can form a capacitance structure in the drain electrode test pad through drain electrode bottom layer metal, a dielectric layer and drain electrode top layer metal, and similarly, the capacitance structure can also be formed in the grid electrode test pad through the grid electrode bottom layer metal, the dielectric layer and the grid electrode top layer metal, and then the grid electrode bottom layer metal and the drain electrode bottom layer metal are respectively connected with the source electrode test pad through a conductive structure. Therefore, in the direct current test process, a circuit with a resistor (a self resistor of a conductive structure) and a capacitor connected in series can be formed between the source electrode test pad and the drain electrode test pad and between the source electrode test pad and the grid electrode test pad to form a leakage channel for grounding an alternating current signal, and an alternating current noise signal introduced by an external test circuit can be grounded in time by using the circuit, so that the self-excitation problem of the semiconductor device in the direct current test is inhibited.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;
FIG. 2 is an enlarged view of a portion of A-A' of FIG. 1;
FIG. 3 is one of the cross-sectional views A-A' of FIG. 2;
FIG. 4 is an enlarged view of a portion B-B' of FIG. 1;
FIG. 5 is one of the cross-sectional views B-B' of FIG. 4;
FIG. 6 is an enlarged view of a portion of C-C' of FIG. 1;
FIG. 7 is one of the cross-sectional views C-C' of FIG. 6;
FIG. 8 is a second cross-sectional view taken along line A-A' of FIG. 2;
FIG. 9 is a second cross-sectional view of B-B' of FIG. 4;
FIG. 10 is a second cross-sectional view of C-C' of FIG. 6;
fig. 11 is a second schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;
FIG. 12 is an enlarged view of a portion of A-A' of FIG. 11;
FIG. 13 is a cross-sectional view A-A' of FIG. 12;
FIG. 14 is an enlarged view of a portion B-B' of FIG. 11;
FIG. 15 is a cross-sectional view B-B' of FIG. 14;
FIG. 16 is an enlarged view of a portion of C-C' of FIG. 11;
fig. 17 is a cross-sectional view of C-C' of fig. 16.
Icon: 8-a semiconductor layer; 9-a substrate; 10-cutting a channel; 11-a gate test pad; 21-source test pad; 31-drain test pad; 12-grid routing bonding pads; 32-drain wire bonding pad; 14-a first plate capacitor; 24-a third plate capacitor; 34-a second plate capacitor; 41-first thin film resistance; 42-a second sheet resistance; 43-third film resistance; 44-two-dimensional electron gas resistance; 411 — first foldline inductance; 412 — second fold inductance; 441-implant region boundary; 51-a first interconnect metal; 52-second interconnect metal; 53-ohm metal; 61-passive region; 62-an active region; 71-a first passivation layer; 72-a second passivation layer; 73-a dielectric layer; 732-third passivation layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto "another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In an aspect of the embodiments of the present application, there is provided a semiconductor device, as shown in fig. 1 or fig. 11, including: substrate 9, substrate 9 may be a base material for carrying semiconductor integrated circuit components, such as GaN, GaAs, SiC, or the like. The semiconductor layer 8 is arranged on the substrate 9, the semiconductor layer 8 can be formed on the substrate 9 through processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), the adopted processes are not limited in the application, and the reasonable selection can be specifically carried out according to actual requirements. The semiconductor layer 8 may be a layer or a stack of semiconductor layers, and should be set with a reasonable selection of device types, for example, a selection according to an insulated gate field effect transistor (MIS FET), a High Electron Mobility Transistor (HEMT), and the like, which is not limited in this application, when the semiconductor device is a HEMT device, the semiconductor layer 8 may include a channel layer and a barrier layer, and in an embodiment, the channel layer may be a GaN layer, and the barrier layer may be an AlGaN layer; in another embodiment, the channel layer may be an AlGaAs layer, the barrier layer may be an InGaP layer, etc., and the semiconductor layer 8 may further include a buffer layer, an insertion layer, etc., to provide better performance of the semiconductor device.
As shown in fig. 1, the semiconductor layer 8 includes an active region 62 and an inactive region 61 located at the periphery of the active region 62, and may be formed by defining the inactive region 61 and the active region 62 on the semiconductor layer 8 by mesa isolation or insulation ion implantation.
Active devices (not shown) may be formed in the active region 62 of the semiconductor layer 8, for example, a source electrode, a drain electrode and a gate electrode are disposed on the active region 62, wherein the gate electrode is located between the source electrode and the drain electrode, thereby enabling the gate electrode to form an active structure having a gate control function over a channel between the source electrode and the drain electrode.
The inactive area 61 of the semiconductor layer 8 may be used to manufacture the source test pad 21, the drain test pad 31, and the gate test pad 11, a dc test of the semiconductor device may be implemented through the source test pad 21, the drain test pad 31, and the gate test pad 11, and the source test pad 21, the drain test pad 31, and the gate test pad 11 are disposed in the inactive area 61, so that an influence of the test pads on the active device of the active area 62 may be effectively reduced. In some embodiments, the source test pad 21 may be connected to a source electrode of an active device disposed in the source region 62, and similarly, the drain test pad 31 may be connected to a drain electrode of an active device disposed in the source region 62, and the gate test pad 11 may be connected to a gate electrode of an active device disposed in the source region 62. The number of active devices provided by active region 62 is not limited by the present application.
As shown in fig. 1, 2 and 3, the drain test pad 31 may include a drain bottom layer metal and a drain top layer metal which are stacked, and as shown in fig. 1, 4 and 5, the gate test pad 11 includes a gate bottom layer metal and a gate top layer metal which are stacked. In some embodiments, the drain underlayer metal and the gate underlayer metal may be the same layer of metal fabricated in the same process step, e.g., both belonging to different parts of the first interconnection metal 51, i.e., the first interconnection metal 51 includes the drain underlayer metal and the gate underlayer metal; similarly, the drain top layer metal and the gate top layer metal may also be the same layer metal fabricated in the same process step, for example, both belonging to different parts of the second interconnect metal 52, i.e., the second interconnect metal 52 may include the drain top layer metal and the gate top layer metal. The first interconnection metal 51 and the second interconnection metal 52 may be interconnection metal layers of active devices forming the active region 62, which are simultaneously formed in the passive region 61, and the dielectric layer 73 is the same.
In order to realize insulation isolation, as shown in fig. 3 and 5, a dielectric layer 73 may be further disposed between the drain bottom metal and the drain top metal, and a dielectric layer 73 is also disposed between the gate bottom metal and the gate top metal, so that the gate test pad 11 may form the first plate capacitor 14 through the gate bottom metal, the dielectric layer 73, and the gate top metal, and similarly, the drain test pad 31 may form the second plate capacitor 34 through the drain bottom metal, the dielectric layer 73, and the drain top metal, that is, a passive device such as a capacitor is added to the drain test pad 31 and the gate test pad 11.
As shown in fig. 1, the source test pad 21 and the gate bottom metal are electrically connected through the conductive structure, and the source test pad 21 and the drain bottom metal are electrically connected through the conductive structure, so that a circuit in which a resistor (the self-resistor of the conductive structure) and a capacitor are connected in series can be formed between the source test pad 21 and the drain test pad 31, and between the source test pad 21 and the gate test pad 11 during the dc test, and a leakage channel for grounding an ac signal is formed.
Optionally, as shown in fig. 1, 6 and 7, the source test pad 21 includes a source bottom metal and a source top metal which are stacked, and in some embodiments, the first interconnection metal 51 may further include the source bottom metal, and the second interconnection metal 52 may further include the source top metal.
The source test pad 21 and the drain test pad 31 may be connected in such a manner that: the source electrode bottom layer metal is connected with the drain electrode bottom layer metal through a conductive structure; the source test pad 21 and the gate test pad 11 may be connected in such a manner that: the source bottom layer metal is connected with the grid bottom layer metal through the conductive structure.
In some embodiments, as shown in fig. 7, the stacked source bottom layer metal and the stacked source top layer metal may be in direct contact for source dc testing. During formation, before the second metal is manufactured, the dielectric layer 73 covering the first interconnection metal 51 is etched to form an opening, the position of the opening corresponds to the position of the source bottom metal, namely, the source bottom metal is exposed in the opening, and the source top metal is formed in the opening through the processes of photoetching, evaporation, metal stripping and the like, so that the contact between the source top metal and the source bottom metal is realized.
In some embodiments, as shown in fig. 10, a dielectric layer 73 may also be disposed between the stacked source bottom layer metal and the source top layer metal. During manufacturing, after the dielectric layer 73 is formed on the first interconnection metal 51, the second interconnection metal 52 is directly formed on the dielectric layer 73 without opening a hole on the dielectric layer 73 on the source bottom metal and is used as the source top metal, so that the insulation isolation of the source bottom metal and the source top metal is realized, namely the third flat capacitor 24 is also formed in the source test pad 21, and thus, a circuit in which the first flat capacitor 14 and the third flat capacitor 24 are connected in series through a conductive structure is formed between the source and the gate, and a circuit in which the second flat capacitor 34 and the third flat capacitor 24 are connected in series through a conductive structure is formed between the source and the drain, so that the suppression effect of an alternating current noise signal introduced by an external test circuit can be further improved.
Optionally, as shown in fig. 1, a dicing street 10 is disposed on the wafer, and in a subsequent process after the dc test is finished, the wafer may be diced along the dicing street 10, so as to form a plurality of independent chips. When the source test pad 21 is connected to the drain test pad 31 and the gate test pad 11 through the conductive structure, the conductive structure may cross the scribe line 10, that is, one section of the circuit connected between the source test pad 21 and the gate test pad 11 is completely outside the scribe line 10, and one section of the circuit connected between the source test pad 21 and the drain test pad 31 is completely outside the scribe line 10, so that, during dicing, the circuit connected between the source test pad 21 and the drain test pad 31 may be completely disconnected by cutting along the scribe line 10, so that the circuit connected between the source test pad 21 and the gate test pad 11 is completely disconnected, and normal use of the chip is prevented from being affected by the conductive structure.
Alternatively, as shown in fig. 1 to 10, the conductive structure includes a thin film resistor located in the inactive region 61 of the semiconductor layer 8, and for convenience of description, the thin film resistor connected between the source test pad 21 and the gate test pad 11 is referred to as a first thin film resistor 41, and the thin film resistor connected between the source test pad 21 and the drain test pad 31 is referred to as a third thin film resistor 43, thereby electrically connecting the source test pad 21 to the gate test pad 11 and the drain test pad 31, respectively. By adding the thin film resistor, the first thin film resistor 41 can be connected in series between the source test pad 21 and the gate test pad 11 to form a series circuit of the first flat capacitor 14, the first thin film resistor 41 and the third flat capacitor 24, or to form a series circuit of the first flat capacitor 14, the first thin film resistor 41 and the source test pad 21; similarly, the third thin-film resistor 43 may be connected in series between the source test pad 21 and the drain test pad 31 to form a series circuit of the second flat capacitor 34, the third thin-film resistor 43, and the third flat capacitor 24, or a series circuit of the second flat capacitor 34, the third thin-film resistor 43, and the source test pad 21, thereby further improving the effect of suppressing the ac noise signal introduced from the external test circuit by the circuit.
In some embodiments, as shown in fig. 1 to 10, the first thin-film resistor 41 and the third thin-film resistor 43 may be configured as a meander-line resistor, i.e., the resistor has a serpentine shape or a wave shape, and the current conducting path between the source test pad 21 and the gate test pad 11 and between the source test pad 21 and the drain test pad 31 also has a serpentine shape, so that the first thin-film resistor 41 and the third thin-film resistor 43 can also function as an inductor, i.e., the thin-film resistor and the inductor are integrated into the same element structure. By adding the inductor, the inductor can be connected in series between the source test pad 21 and the gate test pad 11 to form a series circuit of the first plate capacitor 14, the first thin-film resistor 41, the inductor and the third plate capacitor 24, or form a series circuit of the first plate capacitor 14, the first thin-film resistor 41, the inductor and the source test pad 21; similarly, an inductor may be connected in series between the source test pad 21 and the drain test pad 31 to form a series circuit of the second plate capacitor 34, the third thin-film resistor 43, the inductor, and the third plate capacitor 24, or a series circuit of the second plate capacitor 34, the third thin-film resistor 43, the inductor, and the source test pad 21, thereby further improving the effect of suppressing the ac noise signal introduced by the circuit to the external test circuit.
In some embodiments, the material of the thin film resistor may be TaN, NiCr, or the like.
Optionally, the semiconductor device may further include a first passivation layer 71 and a second passivation layer 72, which may be arranged in the form of: referring to fig. 1 to 7, after the semiconductor layer 8 is formed, an entire first passivation layer 71 is formed on the semiconductor layer 8, and then a thin film resistor is formed on the first passivation layer 71, and the thin film resistor and the semiconductor layer 8 may be insulated and isolated by the first passivation layer 71. Next, an entire layer of the second passivation layer 72 is formed on the thin film resistors, the second passivation layer 72 covers the first thin film resistors 41 and the third thin film resistors 43, then, holes are formed on the first thin film resistors 41 and the third thin film resistors 43, and the first interconnection metal 51 is formed on the second passivation layer 72, so that the drain electrode bottom metal and the source electrode bottom metal are respectively connected to the thin film resistors through the holes on the second passivation layer 72. Then, a dielectric layer 73 is formed on the first interconnection metal 51 in an integral layer, and a second interconnection metal 52 is formed on the dielectric layer 73, so that the gate top metal and the gate bottom metal, the drain top metal and the drain bottom metal, and the source top metal and the source bottom metal are separated by the dielectric layer 73, and the first plate capacitor 14, the second plate capacitor 34, and the third plate capacitor 24 are formed. In some embodiments, the first passivation layer 71, the second passivation layer 72, and the dielectric layer 73 may be made of SiN or SiO2、Al2O3AlN and the like.
Of course, in some embodiments, as shown in fig. 7 to 10, when the source test pad 21 does not serve as a capacitor structure, the dielectric layer 73 on the source bottom metal may be opened before the second interconnection metal 52 is formed, and then the second interconnection metal 52 is formed, so that the source top metal is in contact with the source bottom metal.
In some embodiments, as shown in fig. 8 and 9, before forming the second interconnection metal 52, a hole may be opened in the dielectric layer 73 above the gate bottom metal and the drain bottom metal, then a third passivation layer 732 is filled in the hole, and then the second interconnection metal 52 is formed, so that the dielectric layer 73 between the first plate capacitor 14 and the second plate capacitor 34 is replaced by the third passivation layer 732, and the dielectric constant of the third passivation layer 732 is different from that of the dielectric layer 73, thereby being able to be aligned with the first plate capacitor 14 and the second plate capacitor 34, and thus being able to be aligned with the first plate capacitor 732The capacitance between the plate capacitor 14 and the second plate capacitor 34 is flexibly adjusted. In some embodiments, the dielectric constant of the third passivation layer 732 may be greater than the dielectric constant of the dielectric layer 73, for example, BaTiO may be used for the third passivation layer 7323、SrTiO3、TiO2And a dielectric material with a high dielectric constant.
Alternatively, as shown in fig. 11 to 17, the conductive structure includes a two-dimensional electron gas resistor 44 located in the passive region 61 of the semiconductor layer 8, and when the two-dimensional electron gas resistor 44 is formed, the two-dimensional electron gas of the semiconductor layer 8 located between the source test pad 21 and the drain test pad 31 and between the source test pad 21 and the gate test pad 11 may be retained in the passive region 61 when the definition of the active region 62 and the passive region 61 is implemented in the foregoing manner. For example, as shown in fig. 11 and 13, when the active region 62 and the passive region 61 are defined by the insulating ion implantation, a mask layer may be used to block the two-dimensional electron gas to be retained in the passive region 61 on the semiconductor layer 8, thereby forming a non-implanted region, which is bounded by a non-implanted region boundary 441 shown in fig. 13. Note that, as shown in fig. 13, the ohmic metal 53 should be located in the non-implanted region.
In addition, in order to achieve good electrical connection, after the semiconductor layer 8 is formed, ohmic metals 53 may be formed in advance at positions where the source test pad 21, the drain test pad 31 and the gate test pad 11 are to be formed in the inactive area 61 of the semiconductor layer 8, and the ohmic metals 53 formed in the inactive area 61 may be formed in the same process step as the ohmic metals 53 of the active devices in the active area 62. Then, a first passivation layer 71, a thin film resistor, a second passivation layer 72, a first interconnection metal 51 and a second interconnection metal 52 are formed. It should be noted that before the first interconnection metal 51 is fabricated, openings may be formed in the first passivation layer 71 and the second passivation layer 72, so that the first interconnection metal 51 is in contact with the ohmic metal 53. The ohmic metal 53 is formed so that the first interconnection metal 51 is electrically connected to the semiconductor layer 8 through the ohmic metal 53.
In this way, as shown in fig. 13, by adding the two-dimensional electron gas resistor 44, the source test pad 21 can be electrically connected to the gate test pad 11 through the two-dimensional electron gas resistor 44, and the source test pad 21 can be electrically connected to the drain test pad 31 through the two-dimensional electron gas resistor 44.
Alternatively, as shown in fig. 11 to 17, the conductive structure further includes a first tab inductance 411 and a second tab inductance 412, that is, the first tab inductance 411 is connected in series in a connection circuit between the gate test pad 11 and the source test pad 21 to form a series circuit of the first plate capacitor 14, the two-dimensional electron gas resistor 44, the first tab inductance 411, and the third plate capacitor 24, or to form a series circuit of the first plate capacitor 14, the two-dimensional electron gas resistor 44, the first tab inductance 411, and the source test pad 21. A second tab inductance 412 is connected in series in the connection circuit between the drain test pad 31 and the source test pad 21, forming a series circuit of the second plate capacitor 34, the two-dimensional electric resistance 44, the second tab inductance 412, and the third plate capacitor 24, or forming a series circuit of the second plate capacitor 34, the two-dimensional electric resistance 44, the second tab inductance 412, and the source test pad 21. Therefore, the suppression effect of the circuit on alternating current noise signals introduced by an external test circuit is further improved.
Alternatively, as shown in fig. 1 to 17, a gate bonding pad 12 and a drain bonding pad 32 are further disposed on the inactive area 61 of the semiconductor layer 8, the gate bonding pad 12 can be electrically connected to the gate testing pad 11 through a connecting metal and a thin film resistor (for convenience of distinguishing, the second thin film resistor 42 will be described below), and the drain bonding pad 32 can be electrically connected to the drain testing pad 31 through a connecting metal. The connection metal may be a part of the first interconnection metal 51, and the second thin-film resistor 42 may be fabricated in the same process step as the first thin-film resistor 41 and the third thin-film resistor 43.
As shown in fig. 4, 5, 14 and 15, the gate bonding pad 12 can be electrically connected to the gate top metal through the connecting metal and the second thin film resistor 42. As shown in fig. 1 and 11, the drain wire bonding pad 32 can be electrically connected to the drain bottom metal through a connecting metal.
In some embodiments, as shown in fig. 1 and 11, the first interconnection metal 51 connected between the gate bonding pad 12 and the gate top metal may cross the scribe line 10 on the semiconductor layer 8, i.e., a segment of the circuit connecting the gate bonding pad 12 and the gate test pad 11 is completely outside the scribe line 10. The first interconnect metal 51 connecting between the drain wire bond pad 32 and the drain top layer metal may cross the scribe line 10 on the semiconductor layer 8, i.e. a section of the circuit connecting the drain wire bond pad 32 and the drain test pad 31 is completely outside the scribe line 10. Therefore, when the chip is cut, the connection metal between the gate routing pad 12 and the gate testing pad 11 is disconnected in a manner of cutting along the cutting channel 10, so that the disconnection between the gate testing pad 11 and the gate routing pad 12 is realized, the connection metal between the drain routing pad 32 and the drain testing pad 31 is disconnected, the disconnection between the drain testing pad 31 and the drain routing pad 32 is realized, and the influence on the normal use of the chip caused by the electrical connection between the gate testing pad 11 and the gate routing pad 12 and the electrical connection between the drain routing pad 32 and the drain testing pad 31 is avoided.
In some embodiments, during the dc test, the test pads at two ends of the device may be used simultaneously, that is, as shown in fig. 1 and 11, the source test pad 21, the gate test pad 11, and the drain test pad 31 are respectively disposed at two opposite ends of the device, so that the voltage drop caused by the distance inside the device can be reduced, the device test accuracy is improved, and the abnormal rate of poor contact in the mass production test is reduced.
In some embodiments, the first interconnect metal 51 and the second interconnect metal 52 may be in the form of Au, Pt, Ti/Au, Ti/Pt/Au, Ti/Pd/Au, or a combination or alloy of one or more thereof. In some embodiments, the ohmic metal 53 may use Ti/Al/Au, Ti/Al/Ti, Ti/Al/Ni/Au, Ti/Au/Ti, or the like.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A semiconductor device, comprising:
a substrate;
the semiconductor layer is arranged on the substrate and comprises an active region and a passive region positioned at the periphery of the active region;
a source test pad, a drain test pad and a gate test pad disposed at the semiconductor layer inactive region,
the drain test pad comprises a drain bottom metal and a drain top metal which are arranged in a stacked mode, the gate test pad comprises a gate bottom metal and a gate top metal which are arranged in a stacked mode,
dielectric layers are respectively arranged between the drain electrode bottom layer metal and the drain electrode top layer metal, and between the grid electrode bottom layer metal and the grid electrode top layer metal, and the grid electrode bottom layer metal and the drain electrode bottom layer metal are respectively connected with the source electrode test pad through a conductive structure.
2. The semiconductor device of claim 1, wherein the source test pad comprises a source bottom metal and a source top metal arranged in a stack, the source bottom metal being connected to the gate bottom metal and the drain bottom metal through the conductive structure, respectively.
3. The semiconductor device of claim 2, wherein a dielectric layer is disposed between the source bottom metal and the source top metal.
4. The semiconductor device of claim 1, wherein the conductive structure crosses a scribe line on the semiconductor layer.
5. The semiconductor device according to any one of claims 1 to 4, wherein ohmic metals are respectively provided between the gate underlayer metal and the semiconductor layer and between the drain underlayer metal and the semiconductor layer, the conductive structure includes a two-dimensional electron gas resistor located in a passive region of the semiconductor layer, and the gate underlayer metal and the drain underlayer metal are respectively electrically connected to the source test pad through the two-dimensional electron gas resistor.
6. The semiconductor device of claim 5, wherein the conductive structure further comprises a first tab inductance and a second tab inductance, the gate underlayer metal being in series with the source test pad through the two-dimensional electron gas resistance and the first tab inductance, and the drain underlayer metal being in series with the source test pad through the two-dimensional electron gas resistance and the second tab inductance.
7. The semiconductor device according to any one of claims 1 to 4, wherein the conductive structure includes a thin film resistor provided in the semiconductor layer inactive region, and the gate underlayer metal and the drain underlayer metal are electrically connected to the source test pad through the thin film resistor, respectively.
8. The semiconductor device according to claim 7, wherein the resistor is a meander line resistor.
9. The semiconductor device according to claim 1, wherein a gate bonding pad is further disposed in the semiconductor layer passive region, and the gate bonding pad is connected in series with the gate top layer metal sequentially through a connecting metal and a thin film resistor; and the passive region of the semiconductor layer is also provided with a drain routing bonding pad which is connected with the drain bottom layer metal in series through connecting metal.
10. The semiconductor device of claim 9, wherein the connecting metal crosses a scribe line on the semiconductor layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20080073577A (en) * | 2007-02-06 | 2008-08-11 | 삼성전자주식회사 | Semiconductor substrate |
| CN103337468A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Testing structure |
| CN103633046A (en) * | 2013-12-13 | 2014-03-12 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN104733438A (en) * | 2013-12-19 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Wafer accept test structure |
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| JP5142145B2 (en) * | 2008-03-27 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method, semiconductor wafer, and test method |
| US20130299947A1 (en) * | 2012-05-14 | 2013-11-14 | Freescale Semiconductor, Inc. | Passivated test structures to enable saw singulation of wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080073577A (en) * | 2007-02-06 | 2008-08-11 | 삼성전자주식회사 | Semiconductor substrate |
| CN103337468A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Testing structure |
| CN103633046A (en) * | 2013-12-13 | 2014-03-12 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN104733438A (en) * | 2013-12-19 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Wafer accept test structure |
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