CN114068711A

CN114068711A - Semiconductor device and operation circuit

Info

Publication number: CN114068711A
Application number: CN202010786970.4A
Authority: CN
Inventors: 黄晔仁; 林文新; 邱俊榕; 林鑫成; 李建兴
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2022-02-18

Abstract

The invention provides a semiconductor device and an operating circuit, the semiconductor device comprises a substrate, a seed crystal layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source-drain structure, a second source-drain structure and a first contact. The seed layer is on the substrate. A buffer layer is on the seed layer. The channel layer is located on the buffer layer. The barrier layer is located on the channel layer. The gate structure is located on the barrier layer and has a first edge and a second edge. The first and second source-drain structures are located on both sides of the gate structure. The first contact contacts the first source-drain structure and has a third edge and a fourth edge. The first, second, third and fourth edges are parallel to each other. The second and third edges are located between the first and fourth edges. The distance between the second and third edges is between about 0.5 microns and about 30 microns.

Description

Semiconductor device and operation circuit

Technical Field

The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices having III-V materials.

Background

Device damage due to Electrostatic Discharge (ESD) has become one of the most significant reliability issues for integrated circuit products. Particularly, as the size of the integrated circuit is continuously reduced to a deep sub-micron level, the gate oxide layer of the mos becomes thinner and thinner, and the integrated circuit is more likely to be damaged by the electrostatic discharge phenomenon. In general industry standards, input/output pins (I/O pins) of an integrated circuit product must pass human mode esd tests of 2000 volts or more and mechanical mode esd tests of 200 volts or more. Therefore, in the integrated circuit product, the esd protection device must be disposed near all the input/output pads (pads) to protect the internal core circuit (core circuit) from the esd current.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device, which includes a substrate, a seed layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source-drain structure, a second source-drain structure, a dielectric layer, a first contact, a second contact, and a third contact. The seed layer is on the substrate. A buffer layer is on the seed layer. The channel layer is located on the buffer layer. The barrier layer is located on the channel layer. The gate structure is located on the barrier layer and has a first edge and a second edge. The first source-drain structure is located at one side of the gate structure. The second source-drain structure is located on the other side of the gate structure. The dielectric layer covers the first source-drain structure, the second source-drain structure and the gate structure. The first contact penetrates through the dielectric layer, contacts the first source-drain structure, and has a third edge and a fourth edge. The second contact penetrates through the dielectric layer and contacts the gate structure. The third contact penetrates through the dielectric layer and contacts the second source-drain structure. The first, second, third and fourth edges are parallel to each other. The second and third edges are located between the first and fourth edges. A first distance between the second edge and the third edge is between about 0.5 microns and about 30 microns.

The invention further provides an operating circuit, which comprises a core circuit and an electrostatic discharge protection circuit. The core circuit is coupled between a first power supply terminal and a second power supply terminal. The ESD protection circuit includes a discharge element and a control circuit coupled between the first and second power terminals. The release element or control circuit comprises: a gate structure, a first source-drain structure, and a first contact. The gate structure has a first edge and a second edge. The first contact contacts the first source-drain structure and has a third edge and a fourth edge. The control circuit is used for detecting whether an electrostatic discharge event occurs. When an ESD event occurs, the control circuit turns on the discharge element, so that an ESD current flows from the first power terminal to the second power terminal, or from the second power terminal to the first power terminal. The first, second, third and fourth edges are parallel to each other. The second and third edges are located between the first and fourth edges. A first distance between the second edge and the third edge is between about 0.5 microns and about 30 microns.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device according to the present invention.

Fig. 2 is another structural diagram of the semiconductor device of the present invention.

Fig. 3A to 3C are schematic views illustrating a method of manufacturing the semiconductor device of fig. 1.

FIG. 4 is a schematic diagram of an application of the semiconductor device of the present invention.

Reference numerals:

100. 200: semiconductor device with a plurality of semiconductor chips

102. 202: channel layer

103: seed layer

104. 106, 204, 206: source-drain structure

108. 208: two-dimensional electron gas

110. 210: barrier layer

112. 212, and (3): cover layer

114. 214: grid structure

116. 216: contact layer

118: dielectric layer

311. 312: semiconductor layer

120. 122, 124, 220, 222, 2224: contact element

126. 128, 130, 226, 228, 230: electrode for electrochemical cell

310: patterned mask layer

E11-E18, E21-E28: edge of a container

S1-S4: surface of

C1, C2: capacitor with a capacitor element

400: operating circuit

402: electrostatic discharge protection circuit

404: core circuit

406. 408: power supply terminal

410: control circuit

412: release element

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of the elements in the embodiments is for illustration and not for limitation. In addition, the reference numerals in the embodiments are partially repeated, and the relevance between different embodiments is not intended for the sake of simplifying the description. As used herein, the terms "about", "approximately", "substantially" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, i.e., the meanings of "about", "about" and "about" can be implied without specifying "about", "about" and "about".

Fig. 1 is a schematic structural diagram of a semiconductor device according to the present invention. As shown, the semiconductor device 100 includes a substrate 101, a seed layer 103, a buffer layer 105, a channel layer 102, source-

drain structures

104, 106, a barrier layer 110, a cap layer 112, and a gate structure 114. In some embodiments, the substrate 101 may be a Silicon On Insulator (SOI) substrate. In some embodiments, the substrate 101 may also include a ceramic substrate and a pair of barrier layers (not shown) respectively disposed on the upper and lower surfaces of the ceramic substrate. In some embodiments, the ceramic substrate comprises a ceramic material. The ceramic material comprises a metallic inorganic material. In some embodiments, the ceramic substrate may comprise silicon carbide, aluminum nitride (AlN), a sapphire substrate, or other suitable material. The sapphire substrate may be alumina. In some embodiments, the barrier layer on the upper and lower surfaces of the ceramic substrate may comprise one or more layers of insulating material and/or other suitable material layers, such as semiconductor layers. The layer of insulating material may be an oxide, nitride, oxynitride, or other suitable insulating material. The semiconductor layer may be polysilicon. The barrier layer can prevent the diffusion of the ceramic substrate and also can prevent the interaction of the ceramic substrate and other film layers or process machines. In some embodiments, the barrier layer may also seal (encapsulate) the ceramic substrate. In this case, the barrier layer covers not only the upper and lower surfaces but also both side surfaces.

A seed layer 103 is located on the substrate 101. A buffer layer 105 is on the seed layer 103. The seed layer 103 may mitigate lattice differences between the substrate 101 and overlying layers to improve crystalline quality. The seed layer 103 is selective. In other embodiments, the semiconductor device 100 does not have the seed layer 103. In some embodiments, the material of the seed layer 103 may be or include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or combinations thereof.

The buffer layer 105 may relieve strain (strain) of the channel layer 102 subsequently formed over the buffer layer 105 to prevent defects from forming in the channel layer 102 above. In some embodiments, as mentioned above, the buffer layer 105 may be formed directly on the substrate 101 without disposing the seed layer 103 in the semiconductor device 100, so as to simplify the process steps and achieve the improved effect. In some embodiments, the material of the buffer layer 105 may comprise a III-V compound semiconductor material, such as a III-nitride. For example, the material of the buffer layer 105 may be or include Gallium Nitride (GaN), aluminum Nitride (AlN), aluminum Gallium Nitride (AlGaN), aluminum indium Nitride (AlInN), other suitable materials, or combinations thereof.

The channel layer 102 is on the buffer layer 105 and has a III-V material, such as a III-nitride. For example, the channel layer 102 includes gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), other suitable materials, or combinations thereof. In some embodiments, the channel layer 102 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.

Source-

drain structures

104 and 106 are located in channel layer 102. In some embodiments, the material of the source-

drain structures

104 and 106 may be or include a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination thereof. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), similar materials, alloys thereof, multi-layered structures thereof, or combinations thereof, and the semiconductor material may be polycrystalline silicon (poly-Si) or polycrystalline germanium (poly-Ge).

The barrier layer 110 is located in the channel layer 102 and between the source-

drain structures

104 and 106. The material of the barrier layer 110 may comprise one or more group III-V compound semiconductor materials, such as group III nitrides. For example, the material of the barrier layer 110 may be or include GaN, AlGaN, AlInN, InGaN, InAlGaN, other suitable materials, or combinations thereof. In some embodiments, the barrier layer 110 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.

Since the channel layer 102 and the barrier layer 110 comprise dissimilar materials, a heterogeneous interface is formed between the channel layer 102 and the barrier layer 110. A two-dimensional electron gas (2 DEG)108 is formed on the hetero-interface by the band gap of the hetero-material. In one embodiment, the two-dimensional electron gas 108 is used as a conductive carrier of the semiconductor device 100.

A cap layer 112 is disposed over the channel layer 102 and overlaps the barrier layer 110. The cap layer 112 is used to suppress the generation of the two-dimensional electron gas 108 to achieve a normally-off (normal-off) state of the semiconductor device 100. In other embodiments, the cap layer 112 may consume the two-dimensional electron gas 108 underneath without interrupting the conductive path of the two-dimensional electron gas 108, thereby increasing the breakdown voltage of the semiconductor device 100 and thus improving the reliability of the semiconductor device 100. In the present embodiment, the cap layer 112 has edges E17 and E18. Edge E17 is parallel to edge E18 and perpendicular to surface S1 of barrier layer 110. In this example, the edge E17 does not contact the source-drain structure 106, and the edge E18 does not contact the source-drain structure 104. In some embodiments, the cap layer 112 may be gallium nitride (GaN) doped p-type or n-type.

The gate structure 114 is located on the cap layer 112 and has edges E11 and E12. Edge E11 is parallel to edge E12 and perpendicular to surface S1 of barrier layer 110. In the present embodiment, edge E11 aligns with edge E17 and edge E12 aligns with edge E18. In some embodiments, the material of the gate structure 114 may be or include a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination thereof. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), similar materials, alloys thereof, multi-layered structures thereof, or combinations thereof, and the semiconductor material may be polycrystalline silicon (poly-Si) or polycrystalline germanium (poly-Ge).

In other embodiments, a contact layer 116 is formed between the gate structure 114 and the cap layer 112. For example, the contact layer 116 may include a metal nitride containing a refractory metal, and the refractory metal may be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, technetium, rhenium, ruthenium, osmium, rhodium, and iridium. According to an embodiment of the present disclosure, the material of the contact layer 116 may be titanium nitride (TiN). In other embodiments, the contact layer 116 may be omitted to simplify the process.

A dielectric layer 118 covers the source-

drain structures

104, 106, the barrier layer 110, the cap layer 112, and the gate structure 114. The dielectric layer 118 may comprise or be one or more layers of silicon dioxide, low-k dielectric materials such as silicon oxynitride, phosphosilicate Glass (PSG), borosilicate Glass (BSG), borophosphosilicate Glass (BPSG), Undoped Silicate Glass (USG), fluorine-doped silicate Glass (FSG), organosilicate Glass (OSG), SiOxCy, Spin-On-Glass (Spin-On-Polymers), carbon-silicon materials, compounds thereof (compound), composites thereof (compound), the like, or combinations thereof.

Contacts

120, 122, and 124 extend through dielectric layer 118. In the present embodiment, the contact 120 contacts the source-drain structure 104. Contact 122 contacts gate structure 114. Contact 124 contacts source-drain structure 106. In one possible embodiment, the area of the source-drain structure 104 that projects vertically into the channel layer 102 is larger than the area of the contact 120 that projects vertically into the channel layer 102. In this example, the area of the gate structure 114 that is vertically projected onto the channel layer 102 is greater than the area of the contact 122 that is vertically projected onto the channel layer 102, and the area of the source-drain structure 106 that is vertically projected onto the channel layer 102 is greater than the area of the contact 124 that is vertically projected onto the channel layer 102. In some embodiments, the material of the

contacts

120, 122, and 124 may be a metal material, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), a combination thereof, or a multilayer thereof.

In one embodiment, the contact 120 has edges E13, E14 and a surface S2, the contact 122 has a surface S3, the contact 124 has edges E15, E16 and a surface S4. Surfaces S2-S4 are parallel to surface S1 and perpendicular to edges E11-E18. In the present embodiment, the surface S2 is flush with the surfaces S3 and S4.

In addition, the edges E13-E16 are parallel to each other and perpendicular to the surface S1 of the barrier layer 110. As shown, edge E16 is located between edges E11 and E15, and edge E11 is located between edges E12 and E16. In one possible embodiment, the distance between edges E11 and E16 is between about 0.5 microns and about 30 microns. In addition, edge E12 is located between edges E11 and E13, and edge E13 is located between edges E12 and E14. The distance between edges E12 and E13 is between about 0.5 microns and about 30 microns. In some embodiments, the distance between edges E12 and E13 is equal to the distance between edges E11 and E16. In other embodiments, since edge E11 is aligned with edge E17, the distance between edge E17 to edge E16 is also equal to the distance between edges E11 and E16. Likewise, edge E12 is aligned with edge E, so the distance from edge E13 to edge E18 is also equal to the distance between edges E12 and E13.

A capacitance C2 is provided between the gate structure 114 and the contact 124. The capacitance value of the capacitor C2 is related to the distance between the edges E11 and E16. For example, the capacitance value of the capacitor C2 is larger when the distance between the edges E11 and E16 is larger. The smaller the distance between the edges E11 and E16, the smaller the capacitance value of the capacitor C2. In one possible embodiment, the distance between edges E11 and E16 is 0.75 micrometers (um). In addition, a capacitor C1 is formed between the gate structure 114 and the contact 120. The capacitance value of the capacitor C1 is related to the distance between the edges E12 and E13. In one possible embodiment, the distance between edges E12 and E13 is 0.75 micrometers (um). Since the characteristics of the capacitor C1 are similar to those of the capacitor C2, further description is omitted.

In other embodiments, the capacitance values of the capacitors C1 and C2 are calculated using miller ratio (miller ratio), and the distance between the edges E12 and E13 and the distance between the edges E11 and E16 are determined according to the calculation results. The relationship between the miller ratio and the capacitance values of the capacitances C1 and C2 is as follows:

wherein Cgd is the capacitance of the capacitor C2, and Cgs is the capacitance of the capacitor C1.

In one possible embodiment, the Miller ratio is between about 0.3 and about 0.55. In other embodiments, the semiconductor device 100 further comprises

electrodes

126, 128, and 130. The electrode 126 is electrically connected to the contact 120. The electrode 128 is electrically connected to the contact 122. The electrode 130 is used to electrically connect the contact 124. In one embodiment, the electrode 126 does not overlap the gate structure 114. In another possible embodiment, the area of the electrode 126 that projects perpendicularly into the channel layer 102 is outside the area of the electrode 128 that projects perpendicularly into the channel layer 102. In other words, the area of the electrode 126 perpendicularly projected to the channel layer 102 does not overlap the area of the electrode 128 perpendicularly projected to the channel layer 102.

In some embodiments, the semiconductor device 100 is implemented as an electrostatic discharge device that can withstand high transient voltages. For example, when the voltage of the electrode 128 is large enough, the semiconductor device 100 is turned on. Therefore, an electrostatic discharge current may flow into the semiconductor device 100 from the electrode 130 and flow out from the electrode 126. In another possible embodiment, when the semiconductor device 100 is turned on, an ESD current flows into the semiconductor device 100 from the electrode 126 and flows out from the electrode 130. In the present embodiment, the semiconductor device 100 may be implemented as a High Electron Mobility Transistor (HEMT) due to the high electron mobility of the two-dimensional electron gas 108. In this example, the electrode 126 may serve as a source or a drain of the hemt, the electrode 128 may serve as a gate of the hemt, and the electrode 130 may serve as a drain or a source of the hemt. For example, when the electrode 126 serves as a source of the high electron mobility transistor, the electrode 130 serves as a drain of the high electron mobility transistor. When the electrode 126 serves as a drain of the high electron mobility transistor, the electrode 130 serves as a source of the high electron mobility transistor.

In the present embodiment, since the contact 120 and the electrode 126 do not overlap the gate structure 114 through a field plate (field plate), the capacitance value of the capacitor C1 between the source-drain structure 104 and the gate structure 114 can be reduced, thereby reducing the trigger voltage (trigger voltage) of the semiconductor device 100 and increasing the ESD tolerance of the semiconductor device 100. For example, when the esd voltage is greater than the trigger voltage of the semiconductor device 100, the semiconductor device 100 may be turned on to discharge the esd current. Moreover, when two side edges of the gate structure 114 are aligned with two side edges of the cap layer 112, the capacitance of the parasitic capacitance between the gate and the two-dimensional electron gas 108 can be further reduced.

FIG. 2 is another schematic diagram of a semiconductor device according to the present invention. Fig. 2 is similar to fig. 1 except that edge E27 of the cap layer 212 of fig. 2 is not aligned with edge E21 of the gate structure 214, and edge E28 of the cap layer 212 is not aligned with edge E22 of the gate structure 214. Since the characteristics of the channel layer 202, the source-

drain structures

204, 206, the barrier layer 210, the cap layer 212, the gate structure 214, the dielectric layer 218, the

contacts

220, 222, 224, and the

electrodes

226, 228, 230 of fig. 2 are similar to the characteristics of the channel layer 102, the source-

drain structures

104, 106, the barrier layer 110, the cap layer 112, the gate structure 114, the dielectric layer 118, the

contacts

120, 122, 124, and the

electrodes

126, 128, 130 of fig. 1, further description is omitted.

In the present embodiment, the distance between edge E27 of cap layer 212 and edge E26 of contact 224 is less than the distance between edge E21 of gate structure 214 and edge E26 of contact 224. In addition, the distance between the edge E28 of the cap layer 212 and the edge E23 of the contact 220 is less than the distance between the edge E22 of the gate structure 214 and the edge E23 of the contact 220.

Fig. 3A to 3C are schematic diagrams illustrating a method for manufacturing the semiconductor device 100 of fig. 1. First, referring to fig. 3A, a substrate 101 is provided. Next, a seed layer 103 is formed on the substrate 101. A buffer layer 105 is formed on the seed layer 103. A channel layer 102 is formed over the buffer layer 105, and a barrier layer 110 is formed over the channel layer 102. In some embodiments, the seed Layer 103, the buffer Layer 105, the channel Layer 102, and the barrier Layer 110 may be formed by a Deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or a combination thereof.

Since the channel layer 102 and the barrier layer 110 comprise dissimilar materials, a heterogeneous interface is formed between the channel layer 102 and the barrier layer 110. Two-dimensional electron gas (2 DEG)108 is formed at the hetero-interface by the band gap of the hetero-material. The two-dimensional electron gas 108 serves as a conductive carrier for the high electron mobility transistor.

Next, a cap layer 112 and a contact layer 116 are formed on the barrier layer 110. In some embodiments, the cap layer 112 and the contact layer 116 may be formed by a deposition process and a patterning process. For example, the compound semiconductor material layers 311 and 312 may be formed on the barrier layer 110 by a deposition process. In some embodiments, the patterning process includes forming a patterned masking layer 310 on the compound semiconductor material layer 312, and then etching portions of the compound semiconductor material layers 311 and 312 not covered by the patterned masking layer 310, thereby forming the cap layer 112 and the contact layer 116. In some embodiments, the deposition process may comprise Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), similar processes, or combinations of the foregoing.

In some embodiments, the patterned mask layer 310 may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned masking layer 310 may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or combinations thereof. In some embodiments, the patterned mask layer 310 may be formed by spin-on coating (spin-on coating), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), other suitable processes, or combinations thereof.

In some embodiments, the deposited material layer may be etched by a dry etch process, a wet etch process, or a combination of the foregoing. For example, etching of the deposited material layer includes Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching, Neutron Beam Etching (NBE), electron cyclotron resonance (ERC) etching, other suitable etching processes, or a combination thereof.

Referring to fig. 3B, a gate structure 114 is formed on the contact layer 116. In some embodiments, the step of forming the gate structure 114 may include comprehensively depositing a conductive material layer (not shown) for the gate structure 114 over the channel layer 102, and performing a patterning process on the conductive material layer to form the gate structure 114 over the contact layer 116. The deposition process to form the conductive material may be Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) (e.g., sputtering), combinations of the foregoing, or the like.

Source-

drain structures

104 and 106 are then disposed on either side of gate structure 114. The source-

drain structures

104 and 106 extend through the barrier layer 110 and the two-dimensional electron gas 108. In some embodiments, the formation of the source-

drain structures

104 and 106 includes performing a patterning process to recess the barrier layer 110 and the two-dimensional electron gas 108 and a portion of the channel layer 102 on both sides of the gate structure 114, forming a pair of recesses through the barrier layer 110 and extending into the channel layer 102, then depositing a conductive material over the pair of recesses, and performing a patterning process on the deposited conductive material to form the source-

drain structures

104 and 106 at desired locations. In other embodiments, the depth to which the source-

drain structures

104 and 106 extend may be adjusted according to the characteristics required for the actual product. Additionally, the deposition processes and materials used to form the source-

drain structures

104 and 106 may be similar to those of the gate structure 114, and thus are not described again.

Although the source-

drain structures

104 and 106 and the gate structure 114 are described as being formed in different steps, the invention is not limited thereto. For example, the recess for the source-

drain structures

104 and 106 may be formed before the gate structure 114 is formed, and then the source-

drain structures

104 and 106 and the gate structure 114 may be simultaneously formed by a deposition process and a patterning process. In some embodiments, the formation of the source-

drain structures

104 and 106 and the gate structure 114 may independently comprise the same or different processes and materials. In addition, the shapes of the source-

drain structures

104 and 106 and the gate structure 114 are not limited to the vertical sidewalls in the drawings, and may be sloped sidewalls or have other features.

Referring to fig. 3C, a dielectric layer 118 is formed over the source-

drain structures

104 and 106, the gate structure 114, and the barrier layer 110, covering the source-

drain structures

104 and 106, the gate structure 114, and the barrier layer 110. A contact 120 connected to the source-drain structure 104, a contact 122 connected to the gate structure 114, and a contact 130 connected to the source-drain structure 106 are formed in the dielectric layer 118. In some embodiments, the dielectric layer 118 may be deposited by any suitable process, such as Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), the like, or combinations thereof.

In other examples, the step of forming the

contacts

126, 128, and 130 may include forming openings (not shown) corresponding to the source-drain structures 104, the gate structures 114, and the source-drain structures 106, respectively, through the dielectric layer 118 and exposing the source-drain structures 104, the gate structures 114, and the source-drain structures 106, respectively, by a patterning process, depositing a metal material (not shown) on the dielectric layer 118 and filling the openings.

Electrodes

126, 128 and 130 are then formed over

contacts

126, 128 and 130. In some embodiments, a metal material (not shown) may be deposited on the

contacts

126, 128, and 130 and a planarization process is performed to remove portions of the metal material above the dielectric layer 118, thereby forming the

electrodes

126, 128, and 130.

In the present embodiment, the source-

drain structures

104 and 106 are not electrically connected to any field plate, so that the gate and other metal layers (such as field plates) can be prevented from forming a capacitor. Furthermore, by controlling the distance between the gate structure 114 and the

contacts

120 and 124, the trigger voltage of the semiconductor device 100 can be properly adjusted, and the second breakdown current of the semiconductor device 100 can be optimized to improve the ESD protection capability of the semiconductor device 100.

FIG. 4 is a schematic diagram of an application of the semiconductor device of the present invention. In the present embodiment, the operation circuit 400 includes an esd protection circuit 402 and a core circuit 404. The ESD protection circuit 402 and the core circuit 404 are coupled between the

power source terminals

402 and 404. When an ESD event occurs, the operation circuit 400 enters a protection mode. In the protection mode, the ESD protection circuit 402 is activated to discharge ESD current from the power source 406 to the power source 408, or from the power source 408 to the power source 406. Therefore, the esd current does not enter the core circuit 404. At this time, the core circuit 404 stops operating. When the ESD event does not occur, the operation circuit 400 enters a normal mode. In the normal mode, the esd protection circuit 402 stops operating. At this time, the core circuit 404 operates according to the voltages of the

power source terminals

406 and 408. In the normal mode, the power source terminal 406 receives a first operating voltage (e.g., 5V), and the power source terminal 408 receives a second operating voltage (e.g., 0V).

In one embodiment, the esd protection circuit 402 comprises a control circuit 410 and a release element 412. The control circuit 410 is used for determining whether an esd event occurs. When an ESD event occurs on one of the

power terminals

406 and 408 and the other of the

power terminals

406 and 408 is coupled to ground, the control circuit 410 turns on the release element 412. Therefore, the ESD current flows from the power source terminal 406 to the power source terminal 408 through the discharging device 412, or flows from the power source terminal 408 to the power source terminal 406 through the discharging device 412. Since no electrostatic current flows into the core circuit 404, the electrostatic discharge current can be prevented from damaging the components inside the core circuit 404.

In this embodiment, the semiconductor device 100 of fig. 1 and the semiconductor device 200 of fig. 2 can be used as the release element 412. For example, in the semiconductor device 100, the electrode 126 may be coupled to the power source terminal 406 through a trace (not shown), the electrode 130 may be coupled to the power source terminal 408 through a trace (not shown), and the electrode 128 may be coupled to the control circuit 410 through a trace (not shown). Since the semiconductor device 100 does not have the field plate structure, the parasitic capacitance between the gate and the source and the parasitic capacitance between the gate and the drain can be reduced. In one embodiment, the control circuit 410 and the release element 412 may include the semiconductor device 100 of fig. 1 and the semiconductor device 200 of fig. 2, respectively.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments in hardware, software, or a combination of hardware and software. Therefore, the scope of the present invention is to be defined by the appended claims.

Claims

1. A semiconductor device, comprising:

a substrate;

a seed layer on the substrate;

a buffer layer on the seed layer;

a channel layer located on the buffer layer;

a barrier layer on the channel layer;

a gate structure on the barrier layer and having a first edge and a second edge;

a first source-drain structure located at one side of the gate structure;

a second source-drain structure located on the other side of the gate structure;

a dielectric layer covering the first source-drain structure, the second source-drain structure and the gate structure;

a first contact penetrating the dielectric layer and contacting the first source-drain structure, and having a third edge and a fourth edge;

a second contact penetrating the dielectric layer and contacting the gate structure; and

a third contact penetrating the dielectric layer and contacting the second source-drain structure;

wherein the first edge, the second edge, the third edge and the fourth edge are parallel to each other, and the second edge and the third edge are located between the first edge and the fourth edge;

wherein a first distance between the second edge and the third edge is between about 0.5 micron and about 30 microns.

2. The semiconductor device of claim 1, wherein the third contact has a fifth edge and a sixth edge, the fifth edge and the sixth edge being parallel to the first edge, the first edge and the sixth edge being between the second edge and the fifth edge, a second distance between the first edge and the sixth edge being between about 0.5 microns and about 30 microns.

3. The semiconductor device of claim 2, wherein the first distance is equal to the second distance.

4. The semiconductor device according to claim 2, further comprising:

a cap layer (112) disposed between the barrier layer and the gate structure and including a seventh edge and an eighth edge;

the seventh edge and the eighth edge are parallel to the third edge and located between the third edge and the sixth edge, a third distance between the third edge and the eighth edge is the same as the first distance, and a fourth distance between the seventh edge and the sixth edge is the same as the second distance.

5. The semiconductor device according to claim 2, further comprising:

a cap layer located between the barrier layer and the gate structure and including a seventh edge and an eighth edge;

the seventh edge and the eighth edge are parallel to the third edge and located between the third edge and the sixth edge, a third distance between the third edge and the eighth edge is smaller than the first distance, and a fourth distance between the seventh edge and the sixth edge is smaller than the second distance.

6. The semiconductor device according to claim 1, further comprising:

a first electrode electrically connected to the first contact;

a second electrode electrically connected to the second contact; and

a third electrode electrically connected to the third contact;

wherein the area of the first electrode vertically projected to the channel layer is located outside the area of the second electrode vertically projected to the channel layer.

7. The semiconductor device of claim 6, wherein the first electrode does not overlap the gate structure.

8. The semiconductor device of claim 1, wherein a first capacitance is between the gate structure and the first contact, a second capacitance is between the gate structure and the third contact, and a value of the second capacitance divided by a total capacitance of the first and second capacitances is between about 0.3 and about 0.55.

9. An operating circuit, comprising:

a core circuit coupled between a first power source terminal and a second power source terminal; and

an ESD protection circuit, comprising a release element and a control circuit, respectively coupled between the first and second power terminals, wherein the release element or the control circuit comprises:

a gate structure having a first edge and a second edge;

a first source-drain structure; and

a first contact contacting the first source-drain structure and having a third edge and a fourth edge;

the control circuit is used for detecting whether an electrostatic discharge event occurs or not, and when the electrostatic discharge event occurs, the control circuit conducts the release element to enable an electrostatic discharge current to flow from the first power end to the second power end or from the second power end to the first power end;

10. The operating circuit of claim 9, wherein the core circuit is deactivated when the release element is turned on.

11. The operating circuit according to claim 10, wherein when the first power terminal receives a first operating voltage and the second power terminal receives a second operating voltage, the control circuit turns off the release element, and the core circuit operates according to the first operating voltage and the second operating voltage.

12. The operating circuit of claim 9, wherein the release element or the control circuit further comprises:

a second source-drain structure located at one side of the gate structure;

a second contact contacting the gate structure; and

a third contact contacting the second source-drain structure and having a fifth edge and a sixth edge;

wherein the fifth edge and the sixth edge are parallel to the first edge, the first edge and the sixth edge are between the second edge and the fifth edge, and a second distance between the first edge and the sixth edge is between about 0.5 microns and about 30 microns.

13. The operational circuit of claim 12, wherein the first distance is equal to the second distance.

14. The operational circuit of claim 12, wherein the release element further comprises:

a cap layer located under the gate structure and including a seventh edge and an eighth edge,

15. The operational circuit of claim 12, wherein the release element further comprises:

16. The operating circuit of claim 12, wherein a first capacitance is between the gate structure and the first contact, a second capacitance is between the gate structure and the third contact, and a capacitance of the second capacitance divided by a total capacitance of the first and second capacitances is between about 0.3 and about 0.55.

17. The operating circuit of claim 12, wherein the first contact is electrically connected to the first power terminal, the second contact is electrically connected to the control circuit, and the third contact is electrically connected to the second power terminal.