CN113437025A - Manufacturing method for array substrate side routing and spliced display panel - Google Patents
Manufacturing method for array substrate side routing and spliced display panel Download PDFInfo
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- CN113437025A CN113437025A CN202110648585.8A CN202110648585A CN113437025A CN 113437025 A CN113437025 A CN 113437025A CN 202110648585 A CN202110648585 A CN 202110648585A CN 113437025 A CN113437025 A CN 113437025A
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- 239000000758 substrate Substances 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000010410 layer Substances 0.000 claims abstract description 53
- 239000011241 protective layer Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 230000007704 transition Effects 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000002791 soaking Methods 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 2
- 238000002161 passivation Methods 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000010023 transfer printing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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Abstract
The embodiment of the application discloses a manufacturing method for array substrate side wiring and a spliced display panel, wherein the manufacturing method for array substrate side wiring comprises the following steps: step S100: providing a substrate to be processed, wherein a first connecting terminal is arranged on the first surface, and a second connecting terminal is arranged on the second surface; step S200: forming a first protective layer on the first surface, wherein the first protective layer is arranged to avoid the first connecting terminal, and forming a second protective layer on the second surface, wherein the second protective layer is arranged to avoid the second connecting terminal; step S300: forming a connecting metal layer on the side surface of the substrate to be processed; step S400: patterning the connecting metal layer to form connecting wires; step S500: the protective layer is removed after step S300 or step S400. The manufacturing method for the array substrate side wiring in the embodiment of the application has the advantages of simple process, low cost, strong bonding force between the side wiring and the substrate, and difficulty in falling off of the side wiring.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate side routing manufacturing method and a spliced display panel.
Background
Micro light emitting diodes (minileds or micro leds) have been used for display panels, for example, the minileds are used as a backlight source of a liquid crystal display panel, or the micro led display panel is used for outdoor display, however, the micro light emitting diode display panel is limited by a micro light emitting diode transfer technology, and it is difficult for the micro light emitting diode display panel to achieve single large-size display, and a large-size display panel needs to be spliced by a plurality of small-size micro light emitting diode display modules.
When the miniature LED display module is spliced into a large-size display panel, the splicing gap can seriously reduce the picture integrity of the display panel, a side silver paste transfer printing technology is developed for realizing seamless splicing, and the side transfer printing silver paste of the miniature LED display module forms a driving circuit which is electrically connected with a wiring circuit, however, the side transfer printing silver paste technology has higher difficulty and higher cost, and the silver paste is easy to fall off.
Disclosure of Invention
The embodiment of the application provides an array substrate side routing manufacturing method and a spliced display panel, wherein the array substrate side routing manufacturing method comprises the following steps: step S100: providing a substrate to be processed, wherein the substrate to be processed comprises a first surface and a second surface, a first connecting terminal is arranged on the first surface, and a second connecting terminal is arranged on the second surface; step S200: forming a protective layer, forming a first protective layer on the first surface, the first protective layer being disposed so as to avoid the first connection terminals, and forming a second protective layer on the second surface, the second protective layer being disposed so as to avoid the second connection terminals; step S300: forming a connection metal layer connecting the first connection terminal and the second connection terminal, the connection metal layer being formed on a side surface; step S400: forming a connecting wire, processing the connecting metal layer to form the connecting wire, wherein one end of the connecting wire is electrically connected with the first connecting terminal, and the other end of the connecting wire is electrically connected with the second connecting terminal; step S500: removing the protective layer after the step S300 or the step S400. The manufacturing method for the array substrate side routing can solve the problems that the process difficulty is high, the cost is high, and the side routing is easy to fall off. The display panel manufactured by the manufacturing method for the array substrate side routing can solve the problem of large splicing gap.
The embodiment of the application provides a manufacturing method for routing on the side surface of an array substrate, which comprises the following steps:
step S100: providing a substrate to be processed, wherein the substrate to be processed comprises a first surface and a second surface, the first surface is provided with a first connecting terminal, and the second surface is provided with a second connecting terminal;
step S200: forming a protective layer, forming a first protective layer on the first surface, the first protective layer being disposed so as to avoid the first connection terminals, and forming a second protective layer on the second surface, the second protective layer being disposed so as to avoid the second connection terminals;
step S300: forming a connection metal layer, wherein the connection metal layer is formed on the side surface of the substrate to be processed and is connected with the first connection terminal and the second connection terminal;
step S400: forming a connecting wire, and forming the connecting wire by patterning the connecting metal layer, wherein one end of the connecting wire is electrically connected with the first connecting terminal, and the other opposite end of the connecting wire is electrically connected with the second connecting terminal;
step S500: removing the protective layer after the step S300 or the step S400.
Optionally, in some embodiments of the present application, the method for forming the connection metal layer in step S300 includes: and forming the connecting metal layer by a physical vapor deposition or magnetron sputtering method.
Optionally, in some embodiments of the application, the method for forming the connection trace in step S400 includes: and laser is carried out on the connecting metal layer through laser to form the connecting wiring.
Optionally, in some embodiments of the present application, the method for forming the protective layer in step S200 includes: the protective layer is formed by coating a photoresist or soaking a photoresist.
Optionally, in some embodiments of the present application, the method for removing the protective layer in step S500 includes: and removing the protective layer by using a photoresist stripping liquid.
Optionally, in some embodiments of the present application, after the step S200, the following step is further included:
step S10: chamfering the connection part of the first surface and the side surface to form a transition surface; and chamfering the joint of the second surface and the side surface to form a transition surface.
Optionally, in some embodiments of the present application, the substrate to be processed further includes: and a thin film transistor and a wiring provided on the first surface, wherein the wiring includes a scan line and a data line, and the first connection terminal is electrically connected to any one of the wirings.
Alternatively, in some embodiments of the present application, a width of the wiring electrically connected to the first connection terminal is smaller than a width of the first connection terminal.
Correspondingly, the embodiment of the application also provides a spliced display panel, which comprises a first array substrate and a second array substrate which are spliced, wherein the first array substrate is manufactured by adopting the array substrate side routing manufacturing method according to any one of the above items, and the second connecting terminal of the first array substrate is electrically connected with the driving chip.
Optionally, in some embodiments of the present application, the light emitting device further includes micro light emitting diodes arranged in an array on the first array substrate and the second array substrate.
In the embodiment of the application, the manufacturing method of the array substrate side routing and the spliced display panel are provided, the manufacturing method of the array substrate side routing is simple in process, low in cost, strong in binding force between the side routing and the substrate, and not prone to falling off of the side routing. The display panel manufactured by the manufacturing method for the array substrate side wiring in the embodiment of the application has small splicing gap and can realize seamless splicing.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a first step of a method for manufacturing a side trace of an array substrate according to an embodiment of the present application;
fig. 2 is a flowchart illustrating a second step of a method for manufacturing a lateral trace of an array substrate according to an embodiment of the present application;
fig. 3 is a flowchart illustrating a third step of a method for manufacturing side traces of an array substrate according to an embodiment of the present application;
fig. 4 to 9 are variation processes of the array substrate in the manufacturing process of the array substrate side traces according to an embodiment of the present application;
fig. 10 is a schematic view of a micro light emitting diode array substrate according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a first structure of a tiled display panel according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a second tiled display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides an array substrate side routing manufacturing method and a spliced display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The first embodiment,
Referring to fig. 1, fig. 2, and fig. 4 to fig. 9, fig. 1 is a flowchart illustrating a first step of a method for manufacturing a side trace of an array substrate according to an embodiment of the present disclosure, fig. 2 is a flowchart illustrating a second step of the method for manufacturing the side trace of the array substrate according to the embodiment of the present disclosure, and fig. 4 to fig. 9 illustrate a variation process of the array substrate during the manufacturing process of the side trace of the array substrate according to the embodiment of the present disclosure. The method for manufacturing the array substrate side routing in the embodiment of the application includes the following steps S100, S200, S300, S400 and S500.
Step S100: as shown in fig. 4, a substrate to be processed 10 is provided, the substrate to be processed 10 includes a first surface 11 and a second surface 12, the first surface 11 is provided with a first connection terminal 110, and the second surface 12 is provided with a second connection terminal 120.
Specifically, the plurality of first connection terminals 110 are arranged on the first surface 11, and the plurality of second connection terminals 120 are arranged on the second surface 12.
Specifically, the first surface 11 is a front surface of the substrate 10 to be processed, and the second surface 12 is a back surface of the substrate 10 to be processed.
Step S200: as shown in fig. 5, a passivation layer is formed, a first passivation layer 210 is formed on the first surface 11, the first passivation layer 210 is disposed to avoid the first connection terminal 110, a second passivation layer 220 is formed on the second surface 12, and the second passivation layer 220 is disposed to avoid the second connection terminal 120.
Specifically, the first protection layer 210 covers the first surface 11 and exposes the first connection terminal 110, and the first protection layer 210 covers the first surface 11 and exposes at least a partial region of the first connection terminal 110; the second passivation layer 220 covers the second surface 12 and exposes the second connection terminal 120, and the second passivation layer 220 covers the second surface 12 and exposes at least a partial region of the second connection terminal 120.
Step S300: as shown in fig. 7, a connection metal layer 300 is formed, and the connection metal layer 300 is formed on the side surface 13 of the substrate 10 to be processed, and the connection metal layer 300 connects the first connection terminal 110 and the second connection terminal 120.
Specifically, the connection metal layer 300 is electrically connected between the first connection terminal 110 and the second connection terminal 120 from the side surface 13; or the connection metal layer 300 is continuously distributed on the first surface 11 partial region, the side surface 13, and the second surface 12 partial region, and is electrically connected between the first connection terminal 110 and the second connection terminal 120. A general way of electrically connecting the connection metal layer 300 between the first connection terminal 110 and the second connection terminal 120 is physical direct bonding. The connection metal layer 300 may overlap the first connection terminal 110 and the second connection terminal 120.
Step S400: as shown in fig. 9, a connection trace 310 is formed, the connection metal layer 300 is patterned to form the connection trace 310, one end of the connection trace 310 is electrically connected to the first connection terminal 110, and the other end of the connection trace 310 is electrically connected to the second connection terminal 120.
Step S500: the protective layer is removed after step S300 or step S400.
Specifically, fig. 1 shows the removal of the passivation layer after step S400, and fig. 2 shows the removal of the passivation layer after step S300.
Specifically, as shown in fig. 8, when the protective layer is removed, if the metal layer 300 is simultaneously distributed on the surface of the protective layer, the metal layer portion on the surface of the protective layer is removed together, and only the metal layer portion electrically connected between the first connection terminal 110 and the second connection terminal 120 remains.
In some embodiments, the method of forming the connection metal layer 300 in step S300 includes: the connection metal layer 300 is formed by a physical vapor deposition or magnetron sputtering method.
Specifically, the connection metal layer 300 is formed by a Physical Vapor Deposition (PVD) or magnetron sputtering method, so that the connection metal layer 300 and the subsequent connection trace 310 form a dense strong bonding force with the side 13 of the substrate 10 to be processed, and the metal layer 300 and the connection trace 310 are not easy to fall off, thereby having high reliability and high reliability.
In some embodiments, the method of forming the connection trace 310 in step S400 includes: the connection trace 310 is formed by laser connecting the metal layer 300.
Specifically, the metal layer 300 is manufactured into the connection trace 310 by laser lithography, the connection trace 310 has a predetermined width, and each connection trace 310 connects the predetermined first connection terminal 110 to the corresponding second connection terminal 120.
In some embodiments, the method of forming the protective layer in step S200 includes: the protective layer is formed by coating a photoresist or soaking a photoresist.
Specifically, the protective layer includes a first protective layer 210 and a second protective layer 220. A protective layer may be formed only in the region except the first connection terminal 110 and the second connection terminal 120 by coating a photoresist or soaking a photoresist; alternatively, a protective layer may be formed by coating a photoresist or soaking a photoresist on the entire surface of the first surface 11 and the entire surface of the second surface 12, and then the first protective layer 210 and the second protective layer 220 may be exposed to the first connection terminal 110 and the second connection terminal 120 by exposure, development, and the like.
In some embodiments, the method for removing the protective layer in step S500 includes: and removing the protective layer by using a photoresist stripping solution.
In some embodiments, step S10 is also included after step S200.
Step S10: referring to fig. 3, the junction between the first surface 11 and the side surface 13 is chamfered to form a transition surface; the junction of the second surface 12 and the side surface 13 is chamfered to form a transition surface.
Specifically, referring to fig. 6, a joint between the first surface 11 and the side surface 13 is chamfered to form a first transition surface 131, and a joint between the second surface 12 and the side surface 13 is chamfered to form a second transition surface 132. The transition surface is formed through chamfering treatment, so that the metal layer 300 and the connecting wire 310 are not bent at a right angle, the bonding force between the metal layer 300 and the connecting wire 310 and the side surface 13 of the substrate 10 to be processed is further improved, the connecting wire 310 is not easy to fall off, and the reliability is improved.
In some embodiments, the substrate to be processed 10 further includes: and a thin film transistor and a wiring including a scan line and a data line provided on the first surface 11, and the first connection terminal 110 is electrically connected to any one of the wirings.
Specifically, the substrate to be processed may be an array substrate, and the array substrate includes thin film transistors and wires arranged in an array, and may further include a driving circuit, which is not limited herein.
In some embodiments, the width of the wiring electrically connected to the first connection terminal 110 is smaller than the width of the first connection terminal 110.
Specifically, the width of the first connection terminal 110 is increased, so that the connection strength between the connection trace 310 and the first connection terminal 110 can be improved, and the reliability can be improved. The width of the second connection terminal 120 can be increased, the connection strength between the connection trace 310 and the second connection terminal 120 can be improved, and the reliability can be improved.
The manufacturing of the array substrate side routing is completed in the manufacturing steps. In some embodiments, the micro light emitting diodes may also be fabricated on the array substrate, as shown in fig. 10, and the micro light emitting diodes 500 are transferred onto the array substrate to complete the fabrication of the micro light emitting diode array substrate 20.
In the embodiment of the present application, the connection metal layer 300 is formed by a Physical Vapor Deposition (PVD) or magnetron sputtering method, so that a dense strong bonding force can be formed between the connection metal layer 300 and the subsequent connection trace 310 and the side surface 13 of the substrate 10 to be processed, and the metal layer 300 and the connection trace 310 are not easy to fall off, and have high reliability and high reliability.
In the embodiment of the application, the junction of the first surface 11 and the side surface 13 is chamfered to form a transition surface; carry out the chamfer with the junction of second surface 12 and side 13 and handle and form the transition face, handle through the chamfer and form the transition face for metal level 300 and connection are walked line 310 and can not the right angle and buckle, further promote metal level 300 and connect the cohesion of walking line 310 and pending side 13 of base plate 10, make to connect to walk line 310 and be difficult to drop, improve the reliability.
Example II,
As shown in fig. 11, an embodiment of the present application further provides a tiled display panel 30, where the tiled display panel 30 includes a first array substrate 21 and a second array substrate 22 that are tiled, the first array substrate 21 is manufactured by using the method for manufacturing the array substrate side trace according to any of the above embodiments, and the second connection terminal 120 of the first array substrate 21 is electrically connected to the driving chip.
Specifically, the tiled display panel 30 includes a first array substrate 21 and a second array substrate 22 that are tiled, the first array substrate 21 is manufactured by the method for manufacturing the array substrate side traces according to any of the above embodiments, the first array substrate 21 includes a first connection terminal 110 and a second connection terminal 120, the connection trace 310 is electrically connected between the first connection terminal 110 and the second connection terminal 120, the first surface 11 is provided with a thin film transistor and a wiring, the wiring includes a scan line and a data line, the wiring on the first surface 11 (front surface) of the first array substrate 21 is conducted to the second surface 12 (back surface) through the first connection terminal 110, the connection trace 310 and the second connection terminal 120, and then the driving systems such as driving chips are electrically connected through the second connection terminal 120, so that the width of the non-display area of the first array substrate 21 at the tiled position can be reduced, thereby reducing the splicing gap and even realizing seamless splicing.
In some embodiments, as shown in fig. 11, the tiled display panel 30 may further include micro light emitting diodes 500 arranged in an array on the first array substrate 21 and the second array substrate 22.
Specifically, when the tiled display panel 30 includes micro light emitting diodes (minileds or micro leds), the tiled display panel 30 may be used as a backlight of a liquid crystal display panel, and the tiled display panel 30 may also use the micro light emitting diodes as display pixels to directly display images, which is not limited herein.
As shown in fig. 12, it is illustrated that the tiled display panel 30 includes a plurality of first array substrates 21 and a plurality of second array substrates 22. The first array substrate 21 may be manufactured by the method for manufacturing the array substrate side traces according to any one of the above embodiments, and the second array substrate 22 may also be manufactured by the method for manufacturing the array substrate side traces according to any one of the above embodiments, which is not limited herein. When the first array substrate 21 and the second array substrate 22 are manufactured by the array substrate side routing manufacturing method according to any one of the above embodiments, both the first array substrate 21 and the second array substrate 22 may have a narrow non-display area width, so as to reduce a splicing gap, and also may reduce a frame width of the first array substrate 21 and the second array substrate 22, so as to implement large-size display, seamless splicing, and narrow-frame display of the spliced display panel 30.
The method for manufacturing the array substrate side routing and the tiled display panel provided by the embodiment of the application are described in detail above, a specific example is applied in the description to explain the principle and the implementation manner of the application, and the description of the embodiment is only used to help understand the method and the core idea of the application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A manufacturing method for routing on the side surface of an array substrate is characterized by comprising the following steps:
step S100: providing a substrate to be processed, wherein the substrate to be processed comprises a first surface and a second surface, the first surface is provided with a first connecting terminal, and the second surface is provided with a second connecting terminal;
step S200: forming a protective layer, forming a first protective layer on the first surface, the first protective layer being disposed so as to avoid the first connection terminals, and forming a second protective layer on the second surface, the second protective layer being disposed so as to avoid the second connection terminals;
step S300: forming a connection metal layer, wherein the connection metal layer is formed on the side surface of the substrate to be processed and is connected with the first connection terminal and the second connection terminal;
step S400: forming a connecting wire, and forming the connecting wire by patterning the connecting metal layer, wherein one end of the connecting wire is electrically connected with the first connecting terminal, and the other opposite end of the connecting wire is electrically connected with the second connecting terminal;
step S500: removing the protective layer after the step S300 or the step S400.
2. The method for manufacturing array substrate side trace according to claim 1, wherein the method for forming the connection metal layer in step S300 includes: and forming the connecting metal layer by a physical vapor deposition or magnetron sputtering method.
3. The method for manufacturing array substrate side traces according to claim 2, wherein the method for forming the connection traces in the step S400 includes: and laser is carried out on the connecting metal layer through laser to form the connecting wiring.
4. The method for manufacturing array substrate side trace according to claim 1, wherein the method for forming the protection layer in the step S200 includes: the protective layer is formed by coating a photoresist or soaking a photoresist.
5. The method for manufacturing array substrate side trace according to claim 4, wherein the step S500 of removing the protection layer includes: and removing the protective layer by using a photoresist stripping liquid.
6. The method for manufacturing side traces of an array substrate according to claim 1, further comprising the following steps after the step S200:
step S10: chamfering the connection part of the first surface and the side surface to form a transition surface; and chamfering the joint of the second surface and the side surface to form a transition surface.
7. The method for manufacturing side traces of an array substrate according to claim 1, wherein the substrate to be processed further comprises:
and a thin film transistor and a wiring provided on the first surface, wherein the wiring includes a scan line and a data line, and the first connection terminal is electrically connected to any one of the wirings.
8. The method for manufacturing the array substrate side trace according to claim 7, wherein a width of the wire electrically connected to the first connection terminal is smaller than a width of the first connection terminal.
9. A tiled display panel comprising a first array substrate and a second array substrate arranged in a tiled manner, wherein the first array substrate is manufactured by the method for manufacturing the side traces of the array substrate according to any of claims 1 to 8, and the second connection terminals of the first array substrate are electrically connected to a driving chip.
10. The tiled display panel of claim 9 further comprising micro light emitting diodes arranged in an array on the first array substrate and the second array substrate.
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| CN202110648585.8A CN113437025A (en) | 2021-06-10 | 2021-06-10 | Manufacturing method for array substrate side routing and spliced display panel |
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| CN202110648585.8A CN113437025A (en) | 2021-06-10 | 2021-06-10 | Manufacturing method for array substrate side routing and spliced display panel |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113990209A (en) * | 2021-10-22 | 2022-01-28 | Tcl华星光电技术有限公司 | Display module assembly and seamless splicing display device |
| CN114141806A (en) * | 2021-11-26 | 2022-03-04 | 深圳市华星光电半导体显示技术有限公司 | Conductive paste, preparation method of array substrate side routing and display panel |
| CN114594624A (en) * | 2022-01-27 | 2022-06-07 | 业成科技（成都）有限公司 | Display module, manufacturing method thereof, touch display module, display and electronic equipment |
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