CN113422595B - Electronic switch for processing negative voltage AC signal and control method thereof - Google Patents
Electronic switch for processing negative voltage AC signal and control method thereof Download PDFInfo
- Publication number
- CN113422595B CN113422595B CN202110971997.5A CN202110971997A CN113422595B CN 113422595 B CN113422595 B CN 113422595B CN 202110971997 A CN202110971997 A CN 202110971997A CN 113422595 B CN113422595 B CN 113422595B
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- diode
- node
- isolated nmos
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
Abstract
The invention provides a novel electronic switch for processing negative-pressure AC signals and a control method thereof, wherein the electronic switch comprises: the device comprises an isolated NMOS tube QT1, an isolated NMOS tube QT2, a first clamping circuit, a second clamping circuit, a first control circuit and a second control circuit; the node T1 and the node T2 bias the node MID through a body diode, when the electronic switch is disconnected, if the AC signal at the T1 is positive voltage, the blocking of the electronic switch is completed by the turn-off of QT2, if the AC signal at the T1 is negative voltage, the blocking of the electronic switch is completed by the turn-off of QT1, meanwhile, because the negative voltage at the node T1 is isolated in an independent P trap by an n-type buried layer, the substrate and other potentials of the electronic switch chip can not be influenced by the negative voltage, and the substrate of the electronic switch chip is connected with the ground of the chip. The invention can completely turn off the electronic switch for processing the negative voltage AC signal, and effectively process the negative voltage through the P trap isolated by the n-type buried layer.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a novel electronic switch for processing a negative-pressure AC signal and a control method thereof.
Background
At present, more and more applications need to use an electronic switch for processing a negative voltage AC signal (alternating current signal), which is a special power switch, and the difference from a conventional electronic switch is that a voltage at one end of the electronic switch reaches a negative voltage in an off state, which brings a great challenge to complete turn-off of the electronic switch, and the traditional CMOS bulk silicon process is also difficult to process the negative voltage of a chip.
Disclosure of Invention
The invention aims to provide a novel electronic switch for processing a negative-pressure AC signal and a control method thereof, and aims to solve the problems that the voltage at one end of the switch can reach negative pressure in a turn-off state, so that the electronic switch is difficult to be completely turned off under the negative pressure, and the negative pressure of a chip is difficult to process in the traditional CMOS bulk silicon process.
The invention provides a novel electronic switch for processing negative-pressure AC signals, which comprises:
the device comprises an isolated NMOS tube QT1, an isolated NMOS tube QT2, a first clamping circuit, a second clamping circuit, a first control circuit and a second control circuit;
the drain electrode of the isolated NMOS tube QT1 is connected with the drain electrode of the isolated NMOS tube QT 2; the source electrode of the isolated NMOS tube QT2 is connected with the input end of the clamping circuit II; the output end of the clamping circuit II is connected with the input end of the clamping circuit I on the one hand, and is connected with the input end of the control circuit II on the other hand; the output end of the second control circuit is connected to the grid and the source of the isolated NMOS tube QT2 respectively; the output end of the first clamping circuit is connected with the source electrode of an isolated NMOS tube QT 1; the input end of the first control circuit is connected with the two ends of the first clamping circuit respectively, and the output end of the first control circuit is connected with the grid electrode of an NMOS tube QT 1;
the n-type buried layers in the isolated NMOS transistor QT1 and the isolated NMOS transistor QT2 are connected with respective drains, the P wells isolated by the n-type buried layers are connected with respective sources, and the P wells are also connected with the respective drains through a body diode.
Further, the clamping circuit two comprises a diode D1, a diode D2, a clamping diode Z2, a capacitor cpump and a capacitor CT 2; the control circuit II comprises a switch T2_ on and a switch T2_ off; the source electrode of the isolated NMOS tube QT2 is sequentially connected with the anode and the cathode of the diode D1 and the anode and the cathode of the diode D2; the electrical connection point between the diode D1 and the diode D2 is grounded via the capacitor cpump; two ends of the capacitor CT2 and two ends of the clamping diode Z2 are connected in parallel between the anode of the diode D1 and the cathode of the diode D2; the cathode of the diode D2 is connected with the input end of the first clamping circuit on one hand, and is connected to the source electrode of the isolated NMOS tube QT2 through a switch T2_ on and a switch T2_ off in sequence on the other hand; the electrical connection point between the switch T2_ on and the switch T2_ off is connected to the gate of the isolated NMOS transistor QT 2.
Further, the clamping circuit one comprises a diode D3, a clamping diode Z1 and a capacitor CT 1; the first control circuit comprises a switch T1_ on and a switch T1_ off; the anode of the diode D1 is connected with the cathode of the diode D2, the cathode of the diode D1 passes through one end of the clamping diode Z1, and the electrical connection point between the diode D3 and the clamping diode Z1 is connected with the gate of an isolated NMOS tube QT1 through a switch T1_ on; the other end of the diode Z1 is connected with the source electrode of an isolated NMOS tube QT1 on one hand, and is connected with the gate electrode of an isolated NMOS tube QT1 through a switch T1_ off on the other hand; a capacitor CT1 is connected in parallel across the clamping diode Z1.
The invention also provides a control method of the novel electronic switch for processing the negative voltage AC signal, which is characterized in that a source electrode of an isolated NMOS tube QT1 is set as a node T1, a source electrode of an isolated NMOS tube QT2 is set as a node T2, and an electrical connection point between a drain electrode of the isolated NMOS tube QT1 and a drain electrode of an isolated NMOS tube QT2 is set as a node MID; the control method comprises the following steps:
(1) the electronic switch is turned on: the input end of the first control circuit controls the first clamping circuit to be communicated with the grid electrode of the isolated NMOS tube QT1, and the output end of the first clamping circuit is disconnected with the grid electrode of the isolated NMOS tube QT1, namely the grid electrode and the source electrode of the isolated NMOS tube QT1 are disconnected; the output end of the second control clamping circuit is communicated with the grid electrode of the isolated NMOS tube QT2, and the grid electrode and the source electrode of the isolated NMOS tube QT2 are disconnected; the voltage of two pairs of nodes T2 of the clamping circuit is clamped to form a (T2+ X) V power domain and is output to the grid electrodes of an isolated NMOS tube QT1 and an isolated NMOS tube QT 2; at the moment, the isolated NMOS tube QT1 and the isolated NMOS tube QT2 are conducted, a low-impedance path is formed from the node T1, the node MID to the node T2, and the voltages of the node T1 and the node T2 are approximately equal; wherein, X represents the highest safe working voltage value between the grid and the source of the isolated NMOS tube QT1 and QT 2;
(2) the electronic switch is turned off: the input end of the first control circuit controls the first clamping circuit to be disconnected with the grid electrode of the isolated NMOS tube QT1, and the output end of the first clamping circuit is communicated with the grid electrode of the isolated NMOS tube QT1, namely the grid electrode and the source electrode of the isolated NMOS tube QT1 are communicated; the output end of the second control clamping circuit is disconnected with the grid electrode of the isolated NMOS tube QT2, and the grid electrode of the isolated NMOS tube QT2 is communicated with the source electrode;
when the voltage at the node T1 is greater than the voltage at the node T2, the (T2+ X) V power domain serves as a power supply of the isolated NMOS tube QT2, and as the grid electrode and the source electrode of the isolated NMOS tube QT2 are communicated, the voltage between the grid electrode and the source electrode of the isolated NMOS tube QT2 is 0V, namely the isolated NMOS tube QT2 is turned off;
when the voltage at the node T1 is lower than the voltage at the node T2, the (T2+ X) V power domain generates a (T1+ X) V power domain with reference to the floating of the node T1, and the (T1+ X) V power domain serves as a power supply of the isolated NMOS transistor QT1, and since the gate and the source of the isolated NMOS transistor QT1 are communicated, the voltage between the gate and the source of the isolated NMOS transistor QT1 is 0V, that is, the isolated NMOS transistor QT1 is turned off.
Further, the method for forming the (T2+ X) V power domain by clamping the voltage of the two pairs of nodes T2 by the clamping circuit is as follows:
when the AC signal at node T2 is high, the AC signal at T2 charges the capacitor cpump through diode D1; when the AC signal at node T2 is low, capacitor cpump charges capacitor CT2 through diode D2; the electrical connection point between the diode D2 and the capacitor CT2 is the node CAP, and the voltage between the node CAP and the node T2 is clamped to XV by the clamping diode Z2, so that the voltage of the clamping node CAP is (T2+ X) V, i.e., a (T2+ X) V power domain is formed.
Further, the method for floating the (T2+ X) V power domain reference node T1 to generate the (T1+ X) V power domain is as follows:
when the AC signal at the node T1 is negative, the voltage at the node T1 is lower than the voltage at the node T2, and the (T2+ X) V power domain charges the capacitor CT1 through the diode D3, and the voltage between the cathode of the diode D3 and the node T1 is clamped to XV through the clamping diode Z1, so that the voltage at the cathode of the diode D3 is (T1+ X) V, that is, the (T1+ X) V power domain is formed.
Typically, X = 5.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention can completely turn off the electronic switch for processing the negative voltage AC signal, and effectively process the negative voltage through the P trap isolated by the n-type buried layer of the isolated NMOS tube.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a structural diagram of a novel electronic switch for processing negative voltage AC signals according to an embodiment of the present invention.
Fig. 2a is a simulation diagram one of the novel electronic switch for processing negative voltage AC signal according to the embodiment of the present invention. The diagram shows the relative differential pressure waveform of the power domain and the voltage at the node T1 in the off state of the electronic switch (T1+5V), which is determined by the simulation model of the first clamping circuit to be that the highest relative differential pressure at the node T1 and the power domain (T1+5V) is 5.88V.
Fig. 2b is a simulation diagram of the novel electronic switch for processing negative voltage AC signals according to the embodiment of the present invention. The voltage of the power domain and the voltage at node T1 are shown in the off state of the electronic switch (T1+5V), and it can be seen that node T1 oscillates between negative 30V and positive 50V in the off state of the electronic switch, and the (T1+5V) power domain oscillates with reference to the voltage at node T1.
Fig. 2c is a simulation diagram of the novel electronic switch for processing negative voltage AC signals according to the embodiment of the present invention. The diagram shows the waveform of the relative voltage difference between the power domain and the voltage at the node T2 in the off state of the electronic switch (T2+5V), and the waveform of the relative voltage difference is determined by a simulation model of the clamp circuit two that the highest relative voltage difference between the power domain and the voltage at the node T2 is 6.09V.
Fig. 2d is a simulation diagram of the novel electronic switch for processing negative voltage AC signals according to the embodiment of the present invention. The voltage at the node T2 and the power domain of the electronic switch in the off state (T2+5V) are illustrated, and it can be seen that the voltage at the node T2 is an AC signal between 0V and positive 15V in the off state of the electronic switch, and that the (T2+5V) power domain is an AC signal that is referenced to the voltage at the node T2.
Fig. 2e is a simulation diagram of the novel electronic switch for processing negative-voltage AC signals according to the embodiment of the present invention. The figure illustrates the electronic switch conducting current in the off state. It can be seen that the electronic switch has no dc current path in the off state.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
As shown in fig. 1, the present embodiment provides a novel electronic switch for processing negative voltage AC signals, which includes:
the device comprises an isolated NMOS tube QT1, an isolated NMOS tube QT2, a first clamping circuit, a second clamping circuit, a first control circuit and a second control circuit;
the drain electrode of the isolated NMOS tube QT1 is connected with the drain electrode of the isolated NMOS tube QT 2; the source electrode of the isolated NMOS tube QT2 is connected with the input end of the clamping circuit II; the output end of the clamping circuit II is connected with the input end of the clamping circuit I on the one hand, and is connected with the input end of the control circuit II on the other hand; the output end of the second control circuit is connected to the grid and the source of the isolated NMOS tube QT2 respectively; the output end of the first clamping circuit is connected with the source electrode of an isolated NMOS tube QT 1; the input end of the first control circuit is connected with the two ends of the first clamping circuit respectively, and the output end of the first control circuit is connected with the grid electrode of an NMOS tube QT 1;
the n-type buried layers (NBL) in the isolated NMOS transistor QT1 and the isolated NMOS transistor QT2 are connected with respective drains, the P Wells (PWELL) isolated by the n-type buried layers are connected with respective sources, and the P wells are also connected with the respective drains through a body diode.
Specifically, the method comprises the following steps:
the second clamping circuit comprises a diode D1, a diode D2, a clamping diode Z2, a capacitor cpump and a capacitor CT 2; the control circuit II comprises a switch T2_ on and a switch T2_ off; the source electrode of the isolated NMOS tube QT2 is sequentially connected with the anode and the cathode of the diode D1 and the anode and the cathode of the diode D2; the electrical connection point between the diode D1 and the diode D2 is grounded via the capacitor cpump; two ends of the capacitor CT2 and two ends of the clamping diode Z2 are connected in parallel between the anode of the diode D1 and the cathode of the diode D2; the cathode of the diode D2 is connected with the input end of the first clamping circuit on one hand, and is connected to the source electrode of the isolated NMOS tube QT2 through a switch T2_ on and a switch T2_ off in sequence on the other hand; an electrical connection point between the switch T2_ on and the switch T2_ off is connected to the gate of the isolated NMOS transistor QT 2.
The first clamping circuit comprises a diode D3, a clamping diode Z1 and a capacitor CT 1; the first control circuit comprises a switch T1_ on and a switch T1_ off; the anode of the diode D1 is connected with the cathode of the diode D2, the cathode of the diode D1 passes through one end of the clamping diode Z1, and the electrical connection point between the diode D3 and the clamping diode Z1 is connected with the gate of an isolated NMOS tube QT1 through a switch T1_ on; the other end of the diode Z1 is connected with the source electrode of an isolated NMOS tube QT1 on one hand, and is connected with the gate electrode of an isolated NMOS tube QT1 through a switch T1_ off on the other hand; a capacitor CT1 is connected in parallel across the clamping diode Z1.
The switches T1_ on and T1_ off, and the switches T2_ on and T2_ off are control signals provided by the system to be controlled by the level shifter to generate control signals to control the switches T1_ on and T1_ off, and the switches T2_ on and T2_ off, respectively. Setting the source electrode of an isolated NMOS tube QT1 as a node T1, the source electrode of an isolated NMOS tube QT2 as a node T2, and an electrical connection point between the drain electrode of the isolated NMOS tube QT1 and the drain electrode of the isolated NMOS tube QT2 as a node MID; the novel control method of the electronic switch for processing the negative-pressure AC signal comprises the following steps:
(1) the electronic switch is turned on: the input end of the first control circuit controls the first clamping circuit to be communicated with the grid electrode of the isolated NMOS tube QT1, and the output end of the first clamping circuit is disconnected with the grid electrode of the isolated NMOS tube QT1, namely the grid electrode and the source electrode of the isolated NMOS tube QT1 are disconnected; the output end of the second control clamping circuit is communicated with the grid electrode of the isolated NMOS tube QT2, and the grid electrode and the source electrode of the isolated NMOS tube QT2 are disconnected; the clamp circuit clamps the voltage of the two pairs of nodes T2 to form a (T2+ X) V power domain, and outputs the V power domain to the isolated NMOS tube QT1 and the grid electrodes (GATET 1 and GATET 2) of the isolated NMOS tube QT 2; at the moment, the isolated NMOS tube QT1 and the isolated NMOS tube QT2 are conducted, a low-impedance path is formed from the node T1, the node MID to the node T2, and the voltages of the node T1 and the node T2 are approximately equal; wherein, X represents the highest safe working voltage value between the gate and the source of the isolated NMOS QT1 and QT2, and the highest safe working voltage between the gate and the source of the isolated NMOS QT1 and QT2 is 5V, so X =5 is generally adopted;
the method for clamping the voltage of the two pairs of nodes T2 by the clamping circuit to form a (T2+ X) V power domain comprises the following steps: when the AC signal at node T2 is high, the AC signal at T2 charges the capacitor cpump through diode D1; when the AC signal at node T2 is low, capacitor cpump charges capacitor CT2 through diode D2; the electrical connection point between the diode D2 and the capacitor CT2 is the node CAP, and the voltage between the node CAP and the node T2 is clamped to XV by the clamping diode Z2, so that the voltage of the clamping node CAP is (T2+ X) V, i.e., a (T2+ X) V power domain is formed.
(2) The electronic switch is turned off: the input end of the first control circuit controls the first clamping circuit to be disconnected with the grid electrode of the isolated NMOS tube QT1, and the output end of the first clamping circuit is communicated with the grid electrode of the isolated NMOS tube QT1, namely the grid electrode and the source electrode of the isolated NMOS tube QT1 are communicated; the output end of the second control clamping circuit is disconnected with the grid electrode of the isolated NMOS tube QT2, and the grid electrode of the isolated NMOS tube QT2 is communicated with the source electrode;
when the voltage at the node T1 is greater than the voltage at the node T2 (corresponding to when the AC signal is positive voltage), (T2+ X) V power domain serves as a power supply of the isolated NMOS transistor QT2, since the gate and the source of the isolated NMOS transistor QT2 are connected, the voltage between the gate and the source of the isolated NMOS transistor QT2 is 0V, that is, the isolated NMOS transistor QT2 is turned off;
when the voltage at the node T1 is less than the voltage at the node T2 (which may correspond to the AC signal being positive or negative), the (T2+ X) V power domain generates the (T1+ X) V power domain with reference to the floating of the node T1, and the (T1+ X) V power domain serves as a power supply of the isolated NMOS QT1, since the gate and the source of the isolated NMOS QT1 are connected, the voltage between the gate and the source of the isolated NMOS QT1 is 0V, i.e., the isolated NMOS QT1 is turned off.
The method for generating the (T1+ X) V power domain by floating the (T2+ X) V power domain reference node T1 is as follows: when the AC signal at the node T1 is negative, the voltage at the node T1 is lower than the voltage at the node T2, and the (T2+ X) V power domain charges the capacitor CT1 through the diode D3, and the voltage between the cathode of the diode D3 and the node T1 is clamped to XV through the clamping diode Z1, so that the voltage at the cathode of the diode D3 is (T1+ X) V, that is, the (T1+ X) V power domain is formed.
That is, the node T1 and the node T2 bias the node MID through the body diode, when the electronic switch is turned off, if the AC signal at the node T1 is positive voltage, the blocking of the electronic switch is completed by turning off the QT2 (the body diode of QT1 is forward biased), and if the AC signal at the node T1 is negative voltage, the blocking of the electronic switch is completed by turning off the QT1 (the body diode of QT2 is forward biased), and meanwhile, since the negative voltage of the node T1 is isolated in an independent P-well by the n-type buried layer, the negative voltage does not affect the substrate and other potentials of the electronic switch chip, and the substrate of the electronic switch chip is connected to the Ground (GND) of the chip. Therefore, the electronic switch for processing the negative voltage AC signal can be completely turned off, and the negative voltage is effectively processed through the P well isolated by the n-type buried layer of the isolated NMOS tube. As shown in fig. 2a, 2b, 2c, 2d, and 2e, when the novel electronic switch for processing negative voltage AC signal Is simulated, it can be seen that the node T2 Is a square wave AC signal of 0-5V, a T2+5V power domain Is generated, and a T1+5V power domain Is further generated, the signal at the node T1 Is an AC signal of-16V, and it can be seen that there Is no dc current path from the node T1 to the node T2 in the off state of the two isolated NMOS transistors through the current Is (Qt 1 signal) flowing through the node T1.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. An electronic switch for processing a negative voltage AC signal, comprising:
the device comprises an isolated NMOS tube QT1, an isolated NMOS tube QT2, a first clamping circuit, a second clamping circuit, a first control circuit and a second control circuit;
the drain electrode of the isolated NMOS tube QT1 is connected with the drain electrode of the isolated NMOS tube QT 2; the source electrode of the isolated NMOS tube QT2 is connected with the input end of the clamping circuit II; the output end of the clamping circuit II is connected with the input end of the clamping circuit I on the one hand, and is connected with the input end of the control circuit II on the other hand; the output end of the second control circuit is connected to the grid and the source of the isolated NMOS tube QT2 respectively; the output end of the first clamping circuit is connected with the source electrode of an isolated NMOS tube QT 1; the input end of the first control circuit is connected with the two ends of the first clamping circuit respectively, and the output end of the first control circuit is connected with the grid electrode of an NMOS tube QT 1;
the n-type buried layers in the isolated NMOS tube QT1 and the isolated NMOS tube QT2 are connected with respective drains, the P wells isolated by the n-type buried layers are connected with respective sources, and the P wells are also connected with the respective drains through an individual diode;
the second clamping circuit comprises a diode D1, a diode D2, a clamping diode Z2, a capacitor cpump and a capacitor CT 2; the control circuit II comprises a switch T2_ on and a switch T2_ off; the source electrode of the isolated NMOS tube QT2 is sequentially connected with the anode and the cathode of the diode D1 and the anode and the cathode of the diode D2; the electrical connection point between the diode D1 and the diode D2 is grounded via the capacitor cpump; two ends of the capacitor CT2 and two ends of the clamping diode Z2 are connected in parallel between the anode of the diode D1 and the cathode of the diode D2; the cathode of the diode D2 is connected with the input end of the first clamping circuit on one hand, and is connected to the source electrode of the isolated NMOS tube QT2 through a switch T2_ on and a switch T2_ off in sequence on the other hand; the electrical connection point between the switch T2_ on and the switch T2_ off is connected with the grid electrode of an isolated NMOS tube QT 2;
the first clamping circuit comprises a diode D3, a clamping diode Z1 and a capacitor CT 1; the first control circuit comprises a switch T1_ on and a switch T1_ off; the anode of the diode D1 is connected with the cathode of the diode D2, the cathode of the diode D1 passes through one end of the clamping diode Z1, and the electrical connection point between the diode D3 and the clamping diode Z1 is connected with the gate of an isolated NMOS tube QT1 through a switch T1_ on; the other end of the diode Z1 is connected with the source electrode of an isolated NMOS tube QT1 on one hand, and is connected with the gate electrode of an isolated NMOS tube QT1 through a switch T1_ off on the other hand; a capacitor CT1 is connected in parallel across the clamping diode Z1.
2. The method for controlling the electronic switch for processing the negative voltage AC signal according to claim 1, wherein the source of the isolated NMOS transistor QT1 is set as a node T1, the source of the isolated NMOS transistor QT2 is set as a node T2, and an electrical connection point between the drain of the isolated NMOS transistor QT1 and the drain of the isolated NMOS transistor QT2 is set as a node MID; the control method comprises the following steps:
(1) the electronic switch is turned on: the input end of the first control circuit controls the first clamping circuit to be communicated with the grid electrode of the isolated NMOS tube QT1, and the output end of the first clamping circuit is disconnected with the grid electrode of the isolated NMOS tube QT1, namely the grid electrode and the source electrode of the isolated NMOS tube QT1 are disconnected; the output end of the second control clamping circuit is communicated with the grid electrode of the isolated NMOS tube QT2, and the grid electrode and the source electrode of the isolated NMOS tube QT2 are disconnected; the voltage of two pairs of nodes T2 of the clamping circuit is clamped to form a (T2+ X) V power domain and is output to the grid electrodes of an isolated NMOS tube QT1 and an isolated NMOS tube QT 2; at the moment, the isolated NMOS tube QT1 and the isolated NMOS tube QT2 are conducted, a low-impedance path is formed from the node T1, the node MID to the node T2, and the voltages of the node T1 and the node T2 are approximately equal; wherein, X represents the highest safe working voltage value between the grid and the source of the isolated NMOS tube QT1 and QT 2;
(2) the electronic switch is turned off: the input end of the first control circuit controls the first clamping circuit to be disconnected with the grid electrode of the isolated NMOS tube QT1, and the output end of the first clamping circuit is communicated with the grid electrode of the isolated NMOS tube QT1, namely the grid electrode and the source electrode of the isolated NMOS tube QT1 are communicated; the output end of the second control clamping circuit is disconnected with the grid electrode of the isolated NMOS tube QT2, and the grid electrode of the isolated NMOS tube QT2 is communicated with the source electrode;
when the voltage at the node T1 is greater than the voltage at the node T2, the (T2+ X) V power domain serves as a power supply of the isolated NMOS tube QT2, and as the grid electrode and the source electrode of the isolated NMOS tube QT2 are communicated, the voltage between the grid electrode and the source electrode of the isolated NMOS tube QT2 is 0V, namely the isolated NMOS tube QT2 is turned off;
when the voltage at the node T1 is lower than the voltage at the node T2, the (T2+ X) V power domain generates a (T1+ X) V power domain with reference to the floating of the node T1, and the (T1+ X) V power domain serves as a power supply of the isolated NMOS transistor QT1, and since the gate and the source of the isolated NMOS transistor QT1 are communicated, the voltage between the gate and the source of the isolated NMOS transistor QT1 is 0V, that is, the isolated NMOS transistor QT1 is turned off.
3. The method of claim 2, wherein the clamping circuit clamps the voltage at node T2 to form a (T2+ X) V power domain by:
when the AC signal at node T2 is high, the AC signal at T2 charges the capacitor cpump through diode D1; when the AC signal at node T2 is low, capacitor cpump charges capacitor CT2 through diode D2; the electrical connection point between the diode D2 and the capacitor CT2 is the node CAP, and the voltage between the node CAP and the node T2 is clamped to XV by the clamping diode Z2, so that the voltage of the clamping node CAP is (T2+ X) V, i.e., a (T2+ X) V power domain is formed.
4. The method of claim 2, wherein the floating of the (T2+ X) V power domain reference node T1 generates the (T1+ X) V power domain by:
when the AC signal at the node T1 is negative, the voltage at the node T1 is lower than the voltage at the node T2, and the (T2+ X) V power domain charges the capacitor CT1 through the diode D3, and the voltage between the cathode of the diode D3 and the node T1 is clamped to XV through the clamping diode Z1, so that the voltage at the cathode of the diode D3 is (T1+ X) V, that is, the (T1+ X) V power domain is formed.
5. The method of controlling an electronic switch for processing negative voltage AC signals according to claim 2, wherein X = 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110971997.5A CN113422595B (en) | 2021-08-24 | 2021-08-24 | Electronic switch for processing negative voltage AC signal and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110971997.5A CN113422595B (en) | 2021-08-24 | 2021-08-24 | Electronic switch for processing negative voltage AC signal and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113422595A CN113422595A (en) | 2021-09-21 |
| CN113422595B true CN113422595B (en) | 2021-11-19 |
Family
ID=77719531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110971997.5A Active CN113422595B (en) | 2021-08-24 | 2021-08-24 | Electronic switch for processing negative voltage AC signal and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113422595B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201860486U (en) * | 2010-10-14 | 2011-06-08 | 英飞特电子（杭州）有限公司 | Multipath LED loaded open circuit protective circuit |
| CN102684657A (en) * | 2011-03-11 | 2012-09-19 | 西安龙飞软件有限公司 | Method for switching negative pressure signal by using ordinary analogue switch |
| CN103916111A (en) * | 2013-01-07 | 2014-07-09 | 国家电网公司 | Alternating-current switch and control method thereof |
| EP2770636A1 (en) * | 2013-02-25 | 2014-08-27 | Schneider Toshiba Inverter Europe SAS | Control device employed in a switched electrical power supply syetem |
| CN105765818A (en) * | 2013-09-30 | 2016-07-13 | 施耐德电气It公司 | Four segment AC MOSFET switch |
| CN109412398A (en) * | 2018-10-31 | 2019-03-01 | 京东方科技集团股份有限公司 | Dash current inhibits mould group, method and power supply device |
| CN210693763U (en) * | 2019-10-22 | 2020-06-05 | 南京国网电瑞电力科技有限责任公司 | Negative voltage driving circuit of switching tube |
| CN111384934A (en) * | 2020-05-29 | 2020-07-07 | 成都市易冲半导体有限公司 | Zero-voltage asynchronous control method and circuit for load modulation switch of wireless charging receiving end |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7288970B2 (en) * | 2004-06-18 | 2007-10-30 | Nantero, Inc. | Integrated nanotube and field effect switching device |
| CN106817038A (en) * | 2015-12-01 | 2017-06-09 | 艾默生网络能源有限公司 | A kind of control method and device of I types tri-level circuit |
| JP6950380B2 (en) * | 2017-09-05 | 2021-10-13 | 富士電機株式会社 | Semiconductor integrated circuit |
| CN209787139U (en) * | 2019-05-27 | 2019-12-13 | 重庆工业职业技术学院 | Switching circuit with overvoltage protection |
| CN112152288A (en) * | 2020-09-21 | 2020-12-29 | 深圳市创芯微微电子有限公司 | Battery protection circuit |
-
2021
- 2021-08-24 CN CN202110971997.5A patent/CN113422595B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201860486U (en) * | 2010-10-14 | 2011-06-08 | 英飞特电子（杭州）有限公司 | Multipath LED loaded open circuit protective circuit |
| CN102684657A (en) * | 2011-03-11 | 2012-09-19 | 西安龙飞软件有限公司 | Method for switching negative pressure signal by using ordinary analogue switch |
| CN103916111A (en) * | 2013-01-07 | 2014-07-09 | 国家电网公司 | Alternating-current switch and control method thereof |
| EP2770636A1 (en) * | 2013-02-25 | 2014-08-27 | Schneider Toshiba Inverter Europe SAS | Control device employed in a switched electrical power supply syetem |
| CN105765818A (en) * | 2013-09-30 | 2016-07-13 | 施耐德电气It公司 | Four segment AC MOSFET switch |
| CN109412398A (en) * | 2018-10-31 | 2019-03-01 | 京东方科技集团股份有限公司 | Dash current inhibits mould group, method and power supply device |
| CN210693763U (en) * | 2019-10-22 | 2020-06-05 | 南京国网电瑞电力科技有限责任公司 | Negative voltage driving circuit of switching tube |
| CN111384934A (en) * | 2020-05-29 | 2020-07-07 | 成都市易冲半导体有限公司 | Zero-voltage asynchronous control method and circuit for load modulation switch of wireless charging receiving end |
Non-Patent Citations (2)
| Title |
|---|
| Comprehensive Analysis and Experimental Validation of 240∘-Clamped Space Vector PWM Technique Eliminating Zero States for EV Traction Inverters With Dynamic DC Link;Deliang Wu 等;《IEEE Transactions on Power Electronics》;20200514;第35卷(第12期);13295-13307 * |
| 宇航高可靠宽占空比磁隔离MOSFET驱动电路研究;吴建超 等;《空间电子技术》;20191225;第16卷(第6期);54-63 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113422595A (en) | 2021-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104319275B (en) | Electrostatic discharge protection circuit | |
| KR100922681B1 (en) | Charge pump circuit | |
| TWI554032B (en) | Isolated bootstrapped switch | |
| TWI427930B (en) | Level-shifter circuit and method for implementing level-shifting | |
| CN105144584A (en) | Level shift circuit | |
| SE441559B (en) | FASTTILLSTANDSOMKOPPLARE | |
| WO2022057366A1 (en) | Negative voltage level conversion control circuit and method | |
| JP2008199607A (en) | Driver circuit with top level shifter for transmitting input signal and corresponding method | |
| CN102280872B (en) | Electrostatic-proof protection circuit | |
| CN103684379A (en) | Switch architecture at low supply voltages | |
| CN207458948U (en) | For improving the LDMOS device and related circuit of high-voltage starting circuit Electro-static Driven Comb ability | |
| US3889135A (en) | Bootstrap circuit employing insulated gate transistors | |
| CN109921779B (en) | Half-bridge circuit through protection circuit | |
| CN114400996A (en) | Direct drive circuit of depletion type power device | |
| JP5134908B2 (en) | Driving circuit having BOT level shifter for transmitting input signal and method attached thereto | |
| CN113422595B (en) | Electronic switch for processing negative voltage AC signal and control method thereof | |
| KR100611296B1 (en) | Transistor circuit and booster circuit | |
| CN103117740A (en) | Low-power-consumption level shift circuit | |
| CN104242909B (en) | A kind of level shifting circuit | |
| CN108880233A (en) | A kind of charge pump circuit | |
| CN115313809A (en) | SiC MOSFET driving method | |
| CN113885644A (en) | Substrate switching circuit for preventing LDO backflow | |
| CN108900081A (en) | A kind of circuit of control negative pressure output | |
| CN101515799B (en) | Auto-detecting CMOS input circuit for single-voltage-supply cmos | |
| CN106708149A (en) | Buffer circuit and voltage generator using same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |