CN113419366B - Clock signal circuit, gate drive circuit and display panel - Google Patents
Clock signal circuit, gate drive circuit and display panel Download PDFInfo
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- CN113419366B CN113419366B CN202110669997.XA CN202110669997A CN113419366B CN 113419366 B CN113419366 B CN 113419366B CN 202110669997 A CN202110669997 A CN 202110669997A CN 113419366 B CN113419366 B CN 113419366B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Crystallography & Structural Chemistry (AREA)
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- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a clock signal circuit, a gate driving circuit and a display panel, and relates to the technical field of display. The clock signal lines comprise M clock signal lines, each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line widths of the M main lines are gradually increased, and M is an integer larger than zero. The clock signal circuit provided by the invention can ensure the consistency of RC Delay among the clock signal lines so as to solve the problem of poor dense linear of a lighting picture.
Description
Technical Field
The invention relates to the technical field of display, in particular to a clock signal circuit, a grid driving circuit and a display panel.
Background
The Gate driving circuit is arranged on a TFT Array substrate (Gate Driver on Array, referred to as GOA for short), that is, the Gate driving circuit is manufactured on the TFT Array substrate by using the existing Array (Array) process to realize the driving method of scanning the Gate line by line. The GOA Circuit includes a GOA driving unit (Circuit) and a bus unit (busline), where the bus unit (busline) includes Clock (Clock, CK) signal lines and the like. Because the GOA technology has the advantages of low cost, low power consumption, narrow frame and the like, more and more panel manufacturers adopt the GOA technology to produce.
With the popularization of the liquid crystal panel GOA technology, the product resolution is changed from 4K to 8K, the number of CK signal lines of the GOA circuit is gradually increased (from 8 to 12), and after 4K and 8K products are gradually matured and introduced into Dual-Gate or Tri-Gate in the future, the number of CK signal lines of the GOA circuit is further increased. As the number of CK signal lines increases, the problem comes.
Referring to fig. 1, in the prior art, CK signal lines have the same material, the same line width, and the same resistance, and taking 8CK design as an example, it is assumed that the capacitances (capacitance due to other leads is not counted) of CK1 to CK8 are C1 to C8:
C1＝1×(N-1)×C 0 +8×C 0 ；
C2＝2×(N-1)×C 0 +7×C 0 ；
C3＝3×(N-1)×C 0 +6×C 0 ；
C4＝4×(N-1)×C 0 +5×C 0 ；
C5＝5×(N-1)×C 0 +4×C 0 ；
C6＝6×(N-1)×C 0 +3×C 0 ；
C7＝7×(N-1)×C 0 +2×C 0 ；
C8＝8×(N-1)×C 0 +1×C 0 ；
wherein, N is an integer larger than zero and represents the number of CK signal circuit groups; c 0 The capacitance at the overlapping position of the single main line 101 and the single branch line 102 of the CK signal line is shown, see the dashed block diagram part in fig. 1;
as can be seen from the above equation, in the nth CK signal line group, the capacitance difference between CK8 and CK1 is:
C8-C1＝7×(N-1)×C 0 -7×C 0 (ii) a And the larger the value of N, the larger the difference;
as can be seen from this, there is a gradient difference in the time of the RC Delay (RC Delay) of the CK signal line of the GOA circuit from the first to the last, and the RC Delay time difference causes a horizontally dense line defect in the lighting screen, as shown in fig. 2. Therefore, an optimized circuit is desired to improve the above problems.
Disclosure of Invention
The invention aims to provide a clock signal circuit which can ensure the consistency of RC Delay between clock signal lines so as to solve the problem of dense linear defects of a lighting picture.
Another objective of the present invention is to provide a gate driving circuit and a display panel.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
a clock signal line comprises M clock signal lines, each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line width of the M main lines is gradually increased, and M is an integer larger than zero.
Optionally, in some embodiments of the present invention, the main line includes a first line and a second line connected to each other, the line width of the first line of the M main lines gradually increases, and the second line is formed by a portion where the branch line and the main line intersect.
Optionally, in some embodiments of the invention, the width of each second line is equal, and the width of each branch line is equal.
Optionally, in some embodiments of the present invention, the line width of the main line is 0.2 to 2.1mm.
Optionally, in some embodiments of the present invention, a ratio of a line width of the yth main line to a line width of the first main line is a ratio of a total capacitance on the yth clock signal line to a total capacitance on the first clock signal line, where Y is an integer greater than zero, and Y is less than or equal to M.
Optionally, in some embodiments of the present invention, a ratio of a line width of the yth main line to a line width of the first main line is Y ± 0.5.
Optionally, in some embodiments of the present invention, a ratio of a line width of the yth main line to a line width of the first main line is
Where N represents the number of groups of clock signal lines, N is an integer greater than zero, C 0 The capacitance at the intersection of the branch and main lines is represented, and C represents the capacitance at the peripheral leads of the main line.
Optionally, in some embodiments of the present invention, when N is greater than 10, a ratio of a line width of the Y-th main line to a line width of the first main line is
In addition, the gate driving circuit comprises a gate driving unit and clock signal lines for providing clock signals for the gate driving unit, wherein the clock signal lines comprise M clock signal lines, each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line width of the M main lines is gradually increased, and M is an integer greater than zero.
In addition, the display panel comprises a gate driving circuit, wherein the gate driving circuit comprises a gate driving unit and a clock signal line for providing a clock signal for the gate driving unit, the clock signal line comprises M clock signal lines, each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line width of the M main lines is gradually increased, and M is an integer greater than zero.
Compared with the prior art, the invention has the following beneficial effects: the invention keeps the same capacitance of each branch line and the main line, and arranges the main line with gradually changed line width, which can keep the RC delay time between the clock signal lines consistent, thereby improving the problem of poor level dense line shape of the lighting picture.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a layout of multiple clock signal lines in the prior art;
FIG. 2 is a schematic view of a lighting picture occurring using a conventional clock signal line;
FIG. 3 is a layout diagram of multiple clock signal lines according to an embodiment of the present invention;
FIG. 4 is an enlarged view of section A of FIG. 3 according to an embodiment of the present invention;
fig. 5 is a partial schematic view of a peripheral lead of a main line according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solution provided by the present invention will be described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments. In addition, in the description of the present invention, the term "including" means "including but not limited to". The terms "first," "second," and the like are used merely as labels, and do not impose numerical requirements or an established order. Various embodiments of the invention may exist in a range of forms; it should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention; accordingly, the described range descriptions should be considered to have specifically disclosed all the possible sub-ranges as well as individual numerical values within that range.
Referring to fig. 3, a clock signal line according to an embodiment of the present invention includes M clock signal lines, each clock signal line includes a main line 101 and a branch line 102, each intersection of the branch line 102 and the main line 101 has an equal capacitance, and line widths of the M main lines 101 gradually increase, where M is an integer greater than zero. In this embodiment, M is 8, and in other embodiments, M may be other values, such as 10 and 12. The connection between the main line 101 and the branch line 102 is well known in the art, and therefore will not be described herein. In this embodiment, the main line 101 is a gate line of the TFT-LCD, and the branch line 102 is a source line and a drain line of the TFT-LCD.
The clock signal lines can be regarded as a group of clock signal lines, and during actual manufacturing, there are multiple groups of clock signal lines, and fig. 3 shows 3 groups of clock signal lines, each with N (n-1) 、N n 、N (n+1) Wherein n is an integer greater than 2. Thus, if N is 2, then N (n-1) 、N n 、N (n+1) Respectively, 1 st group, 2 nd group and 3 rd group.
The main line 101 includes a first line 1011 and a second line 1012 connected to each other, the line width of the first line 1011 of 8 main lines 101 is gradually increased, the second line 1012 is formed by the intersection of the branch line 102 and the main line 101, and all the intersections have equal capacitance. In fact, the arrangement of the first line 1011 and the second line 1012 can also be regarded as: the arrangement in which the line width of the main line 101 varies at the intersection of the main line 101 and the branch line 102, see fig. 4, presents different line widths of the first line 1011 and the second line 1012 at the intersection. As shown in fig. 3, in the same clock signal line, except for the first main line 101, the other main lines 101 include a plurality of first lines 1011 and a plurality of second lines 1012, the first lines 1011 and the second lines 1012 are disposed at intervals, and as shown in the figure, the capacitance at the intersection of each second line 1012 and the branch line 102 is the same. Regarding the length and number limitations of the first lines 1011 on each main line 101, the connection and arrangement of each first line 1011 and the second line 1012 are as follows, with respect to the intersection result of the main line 101 and the branch line 102, see fig. 3 and 4. The line widths of the second line 1012 on the single main line 101 and the second line 1012 on different main lines 101 are all equal. The branches 102 are shown as being of different lengths, but each branch 102 has an equal line width.
In this embodiment, the line width of the 8 main lines 101 ranges from 0.2 mm to 2.1mm. Of course, in other embodiments, other values may be taken.
Specifically, in the same clock signal line, the ratio of the line width of the yth main line 101 to the line width of the first main line 101 is the ratio of the total capacitance on the yth clock signal line to the total capacitance on the first clock signal line, where Y is an integer greater than zero, and Y is less than or equal to M, that is, Y is less than or equal to 8. It should be noted that, in addition to the 1 st group of clock signal lines, in the other groups of clock signal lines, the total capacitance referred to herein shall include the capacitance caused by the peripheral lead 103 of the main line 101, the capacitance of the clock signal line at which the clock signal line is located, and the capacitance of the clock signal line before the group number of the clock signal lines at which the clock signal line is located, and by way of example, CK3 in fig. 3, C3 denotes the total capacitance of CK3 (counting into the capacitance C caused by the peripheral lead 103, see fig. 5 for the line condition of the peripheral lead 103), then in the nth group of clock signal lines, C3=3 × (N-1) × C 0 +6×C 0 + C; wherein C is 0 Representing the capacitance at the intersection of the branch line 102 and the second line 1012.
As can be seen from calculation, the ratio of the line width of the Y-th main line 101 to the line width of the first main line 101 is Y ± 0.5.
Reference is made to the following:
since the number of clock signal lines is 8 in this embodiment, the total capacitance of CK1 to CK8 (including the capacitance due to the peripheral lead 103, which is a non-clock signal line) in each set of clock signal lines is C1 to C8, respectively, as calculated by 8 CK:
C1＝1×(N-1)×C 0 +8×C 0 +C；
C2＝2×(N-1)×C 0 +7×C 0 +C；
C3＝3×(N-1)×C 0 +6×C 0 +C；
C4＝4×(N-1)×C 0 +5×C 0 +C；
C5＝5×(N-1)×C 0 +4×C 0 +C；
C6＝6×(N-1)×C 0 +3×C 0 +C；
C7＝7×(N-1)×C 0 +2×C 0 +C；
C8＝8×(N-1)×C 0 +1×C 0 +C；
wherein N represents the number of groups of clock signal lines, N is an integer greater than zero, C 0 Representing the capacitance at the intersection of the branch line 102 and the second line 1012, C represents the capacitance at the peripheral lead 103 of the main line 101.
In this embodiment, N is 10, in the figure N (n-1) 、N n 、N (n+1) Respectively showing a 9 th group clock signal line, a 10 th group clock signal line and an 11 th group clock signal line.
In order to ensure the consistency of RC Delay between clock signal lines, the Delay time D = -R × C × In ((E-V)/E) is calculated based on the RC Delay calculation formula, and D is equal 1 ＝D Y Then R is 1 C 1 ＝R Y C Y Due to the fact that
r is equal in resistivity rho, length L and thickness H 1 C 1 ＝R Y C Y Namely:
therefore, the ratio of the line width of the Y-th main line 101 to the line width of the first main line 101 is
Since N is 10 in this example, (M-Y + 1). Times.C 0 、M×C 0 The value of (a) is small and can be ignored, and the ratio of the line width of the Y-th main line 101 to the line width of the first main line 101 is
As can be seen from fig. 3, in each group of clock signal lines, the resistances of CK1 to CK8 are R1 to R8, where R1 to R8 represent the resistances of the 1 st to 8 th main lines 101:
according to the RC time delay calculation formula, D1-D8 are as follows:
embodiments of the present invention further provide a gate driving circuit, which includes a gate driving unit and the clock signal line for providing a clock signal to the gate driving unit, and the connection between the gate driving unit and the clock signal line is well known in the art, and therefore, is not described herein again. In addition, the embodiment of the invention also provides a display panel comprising the clock signal circuit. The clock signal circuit provided by the embodiment of the invention has good lighting picture, and can effectively avoid the phenomenon of poor lighting picture level dense line shape caused by inconsistent RC Delay of the current 8K product.
The technical solutions provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are described herein by using specific examples, and the description of the embodiments is only used to help understanding the method and the core ideas of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as limiting the present invention.
Claims (8)
1. A clock signal line is characterized by comprising M clock signal lines, wherein each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line widths of the M main lines are gradually increased along the signal transmission direction, and M is an integer greater than zero;
in the same clock signal circuit, except a first main line, other main lines comprise a plurality of first lines and a plurality of second lines, the first lines and the second lines are arranged at intervals, and the capacitance of the intersection of each second line and a branch line is the same; the line widths of the second line on the main line and the second line on different main lines are equal; the branch lines are different in length, and the line width of each branch line is equal.
2. The clock signal line according to claim 1, wherein the line width of the main line is 0.2 to 2.1mm.
3. The clock signal line of claim 1, wherein a ratio of a line width of a yth one of the main lines to a line width of a first one of the main lines is a ratio of a total capacitance on the yth one of the clock signal lines to a total capacitance on the first one of the clock signal lines, wherein Y is an integer greater than zero and Y is less than or equal to M.
4. The clock signal line of claim 3, wherein a ratio of a line width of the Yth main line to a line width of the first main line is Y ± 0.5.
5. The clock signal line of claim 3, wherein the ratio of the line width of the Y-th main line to the line width of the first main line is
Wherein N represents the number of groups of the clock signal lines, N is an integer greater than zero, C 0 Representing the capacitance at the intersection of the branch line and the main line, C representing the capacitance at the peripheral lead of the main line.
6. The clock signal line of claim 5, wherein when N is greater than 10, the ratio of the line width of the Y-th main line to the line width of the first main line is
7. A gate driving circuit is characterized by comprising a gate driving unit and a clock signal line for providing a clock signal for the gate driving unit, wherein the clock signal line comprises M clock signal lines, each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line widths of the M main lines are gradually increased along the signal transmission direction, and M is an integer greater than zero;
in the same clock signal circuit, except a first main line, other main lines comprise a plurality of first lines and a plurality of second lines, the first lines and the second lines are arranged at intervals, and the capacitance of the intersection of each second line and a branch line is the same; the line widths of the second line on the main line and the second line on different main lines are equal; the branch lines are different in length, and the line width of each branch line is equal.
8. The display panel is characterized by comprising a gate driving circuit, wherein the gate driving circuit comprises a gate driving unit and clock signal lines for providing clock signals for the gate driving unit, the clock signal lines comprise M clock signal lines, each clock signal line comprises a main line and a branch line, the capacitance of each intersection of the branch line and the main line is equal, the line width of the M main lines is gradually increased along the signal transmission direction, and M is an integer greater than zero;
in the same clock signal circuit, except a first main line, other main lines comprise a plurality of first lines and a plurality of second lines, the first lines and the second lines are arranged at intervals, and the capacitance of the intersection of each second line and a branch line is the same; the line widths of the second line on the main line and the second line on different main lines are equal; the branch lines are different in length, and the line width of each branch line is equal.
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| CN109119039A (en) * | 2018-09-13 | 2019-01-01 | 惠科股份有限公司 | Display panel and display device |
| CN209571218U (en) * | 2018-11-06 | 2019-11-01 | 惠科股份有限公司 | Display panel and display device |
| CN111090202A (en) * | 2020-03-22 | 2020-05-01 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112433415A (en) * | 2020-12-02 | 2021-03-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and electronic equipment |
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| CN109119039A (en) * | 2018-09-13 | 2019-01-01 | 惠科股份有限公司 | Display panel and display device |
| CN209571218U (en) * | 2018-11-06 | 2019-11-01 | 惠科股份有限公司 | Display panel and display device |
| CN111090202A (en) * | 2020-03-22 | 2020-05-01 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112433415A (en) * | 2020-12-02 | 2021-03-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and electronic equipment |
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