CN113410385A - Low-voltage floating gate photoelectric memory and preparation method thereof - Google Patents
Low-voltage floating gate photoelectric memory and preparation method thereof Download PDFInfo
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- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
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- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
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Abstract
The invention provides a low-voltage floating gate photoelectric memory and a preparation method thereof. The solution process for preparing the first and second gate dielectric layers and the floating gate layer has the advantages of low cost, easy processing, large-area manufacture and good compatibility with a flexible substrate; the working voltage of the device is not higher than 5V.
Description
Technical Field
The invention relates to the field of memories, in particular to a low-voltage floating gate photoelectric memory and a preparation method thereof.
Background
The nonvolatile floating gate memory based on the organic field effect transistor structure has the advantages of light weight, low cost, easy processing, good compatibility with a flexible substrate and the like, thereby showing wide application prospect. In recent years, among nonvolatile floating gate memories, the photoelectric memory has attracted much attention as a new generation of storage device, not only having a large storage window, but also having a wide application prospect in the fields of image capture, optical information storage, optical computation, and the like. However, most conventional floating gate photo-memories are based on SiO2The gate dielectric layer, which is typically 50-300 nm thick, requires higher operating voltages (greater than 50V) for writing and erasing operations, which is not conducive to saving power consumption and market application requirements. The research on the low-voltage floating gate photoelectric memory to reduce the power consumption has great research value and application prospect.
Disclosure of Invention
The invention provides a low-voltage floating gate photoelectric memory and a preparation method thereof, which solve the problem that the conventional photoelectric memory needs higher operating voltage (more than 50V) to carry out writing and erasing operations.
The technical scheme for realizing the invention is as follows:
a low-voltage floating gate photoelectric memory sequentially comprises a substrate, a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a charge storage layer, a semiconductor layer and a drain-source electrode from bottom to top.
The first gate dielectric layer is any one of polymethyl methacrylate (PMMA), Polystyrene (PS) or poly (4-ethylphenol) (PVP).
The second gate dielectric layer is polyvinyl alcohol.
The charge storage layer is a mixed material of a colloidal quantum dot material and an organic polymer.
The colloid quantum dot material is perovskite, lead sulfide or cadmium selenide quantum dot material, and the organic polymer is PMMA, PS or PVP.
The semiconductor layer is pentacene or copper perfluorophthalocyanine and has the thickness of 25-80 nm, and the drain-source electrode is gold, silver, copper or aluminum and has the thickness of 25-150 nm.
The preparation method of the low-voltage floating gate photoelectric memory comprises the following specific steps:
a. substrate selection and cleaning;
the substrate can be glass, silicon chip or PET material, the substrate is cleaned in deionized water, acetone and isopropanol solution for 10-30 minutes by ultrasonic wave in turn, and then is dried by a nitrogen gun;
b. evaporating a grid electrode;
the grid electrode can be made of gold, silver, aluminum and copper materials, and the thickness is controlled to be 10-30 nm;
c. preparing a first gate dielectric layer
The material can be polymethyl methacrylate (PMMA), Polystyrene (PS) and poly (4-ethylphenol) (PVP), an organic polymer is dissolved in toluene or N, N-Dimethylformamide (DMF), the concentration is kept to be 8-15 mg/mL, the organic polymer is spin-coated on a substrate at 800-3000 rpm for 25-60 seconds, the thickness is controlled to be 20-50 nm, and then the substrate is annealed at 60-120 ℃ for 5-60 minutes to remove residual solvent and solidify the material;
d. preparing a second gate dielectric layer
The material is polyvinyl alcohol (PVA), the PVA is heated and dissolved in water, the concentration is controlled to be 1-10 mg/mL, the PVA is spin-coated on the first grid dielectric layer at 800-3000 rpm, the spin-coating time is 25-60 seconds, the thickness is controlled to be 3-20nm, and then the PVA is annealed at 60-120 ℃ for 20-120 minutes to remove residual solvent and solidified material;
e. preparation of a Charge storage layer
The charge storage layer is a mixture of colloidal quantum dot material and organic polymer, and the colloidal quantum dot material can be perovskite (such as cesium lead bromide CsPbBr)3) Lead sulfide (PbS) and cadmium selenide (CdSe) quantum dot materials, and the organic polymer can be PMMA, PS or PVP. Specifically, firstly preparing quantum dots and an organic polymer solution, controlling the concentration to be 1-20 mg/mL, and then preparing the quantum dots and the organic polymer solutionThe polymer solution is mixed by 10-40% by mass, and can be uniformly mixed by using a magnetic stirrer or ultrasound. Finally, spin-coating on the second gate dielectric layer at 800-;
f. vapor deposition of semiconductor layer and drain-source electrode
The semiconductor material can be pentacene or perfluorinated copper phthalocyanine, the thickness is controlled to be 25-80 nm, the drain-source electrode material can be gold, silver, copper and aluminum, and the thickness is controlled to be 25-150 nm. The vapor deposition electrode uses a mask plate to form a channel, the length of the channel is controlled to be 10-200 mu m, and the width of the channel is controlled to be 0.5-3 mm.
The invention has the beneficial effects that:
(1) the solution process for preparing the first and second gate dielectric layers and the floating gate layer has the advantages of low cost, easy processing, large-area manufacture and good compatibility with a flexible substrate;
the function of the second gate dielectric layer: 1. the insulativity of the grid dielectric layer is increased, and the grid leakage is further prevented; 2. the second grid dielectric layer solvent, the first grid dielectric layer solvent and the charge storage layer solvent are orthogonal solvents, so that the first grid dielectric layer can be prevented from being damaged when the charge storage layer is prepared;
(2) the operating voltage is as low as 5V or less, and the energy consumption is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an optoelectronic memory according to the present invention.
FIG. 2 shows the absence of CsPbBr3Transfer curve of quantum dot device.
FIG. 3 shows a sample containing CsPbBr3Memory characteristics of quantum dot devices.
Fig. 4 shows data retention characteristics of the photoelectric memory.
FIG. 5 shows the endurance characteristics of the optoelectronic memory.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
As shown in fig. 1, the low-voltage floating gate photo memory structure in embodiment 1 of the present invention includes: the semiconductor device comprises a substrate 1, a gate electrode 2, a first gate dielectric layer 3, a second gate dielectric layer 4, a charge storage layer 5, a semiconductor layer 6 and a drain-source electrode 7.
Example 1
The preparation method comprises the following specific steps:
(1) firstly, evaporating a 20nm aluminum gate electrode on a glass substrate;
(2) then, PMMA toluene and PVA aqueous solution are spin-coated to prepare a first dielectric layer and a second dielectric layer, the concentrations are respectively 10 mg/ml and 2.5 mg/ml, and the spin-coating conditions are as follows: annealing at 2000 rpm for 40 s and 80 deg.C for 30 min respectively to obtain thicknesses of 43nm and 5 nm;
(3) PS (2 mg/ml) and CsPbBr3Mixing the quantum dot solution (10 mg/ml) according to the volume ratio of 10:3, spin-coating at the rotating speed of 2000 rpm for 40 seconds, and heating at 80 ℃ for 30 min to remove residual solvent;
(4) finally, 50nm pentacene semiconductor material and a gold electrode with the thickness of 80nm are evaporated. The length of the mask channel is 50 micrometers, the width of the mask channel is 1 millimeter, and the mask channel is marked as a Cs-30 device. In addition, only the PS solution was spin-coated on the second gate dielectric layer as a comparative device, which was designated as a Cs-0 device.
FIG. 2 shows the absence of CsPbBr3Transfer curve of quantum dot device, i.e. spin coating only PS solution on the second gate dielectric layer with gate voltage as abscissaV GSOrdinate is 1/2 th power of drain-source current (non-conducting)I DS|1/2). FIG. 3 is a drawing showingContaining CsPbBr3Memory characteristics of quantum dot devices. Using a wavelength of 405nm, 1 mW/cm2The pulsed light of light intensity and 1 second pulse width is used as the optical writing operation. Compared with the original transfer curve, after the optical writing operation, the transfer curve of the Cs-30 device is obviously shifted to the positive direction, and the transfer curve of the Cs-0 device is not obviously changed, which indicates that electrons in the Cs-30 device are captured in the charge trapping layer. CsPbBr under 405nm illumination3Photogenerated electron-hole pairs are generated in the quantum dots, electrons are captured and retained in a conduction band of the quantum dots, and holes are transferred to pentacene along energy band bending. After applying a gate voltage of-5V for 1 second (erase operation), the transfer curve of the Cs-30 device reverts to the initial state, meaning that the trapped electrons are released. And obtaining a storage window of 1.39V according to the difference value of the threshold voltages of the writing state and the erasing state. It should be noted that the operating voltage of the device is no higher than 5V. Fig. 4 shows data retention of the photoelectric memory over 10000 s, and the trapped electrons can be retained in the charge storage layer for a longer time. As can be seen from fig. 5, after 200 write/erase cycles, the current after optical writing and electrical erasing does not change much, indicating that the device has good stability.
Example 2
The preparation method comprises the following specific steps:
(1) firstly, evaporating a 10nm aluminum gate electrode on a glass substrate;
(2) then spin-coating PVP toluene and PVA water solution to prepare a first dielectric layer and a second dielectric layer, wherein the concentrations are respectively 8 mg/ml and 1 mg/ml, and the spin-coating conditions are as follows: annealing at 800 rpm for 25 seconds and 60 ℃ for 5 minutes respectively;
(3) PS (1 mg/ml) and CsPbBr3Mixing the quantum dot solution (1 mg/ml) according to the volume ratio of 10:2, spin-coating at the rotating speed of 800 rpm for 25 seconds, and heating at 60 ℃ for 20min to remove residual solvent;
(4) finally, evaporating 25nm pentacene semiconductor material and a gold electrode with the thickness of 25 nm. The length of the mask channel is 50 micrometers, and the width of the mask channel is 1 millimeter.
Example 3
The preparation method comprises the following specific steps:
(1) firstly, evaporating a 30nm aluminum gate electrode on a glass substrate;
(2) then spin-coating PS toluene and PVA aqueous solution to prepare a first dielectric layer and a second dielectric layer, wherein the concentrations are respectively 15 mg/ml and 10 mg/ml, and the spin-coating conditions are as follows: annealing at 3000 rpm for 60 s and 120 deg.c for 60 min;
(3) PS (10 mg/ml) and CsPbBr3Mixing quantum dot solution (10 mg/ml) according to a volume ratio of 10:2, spin-coating at a rotating speed of 3000 rpm for 60 seconds, and heating at 100 ℃ for 60min to remove residual solvent;
(4) finally, 80nm pentacene semiconductor material and a gold electrode with the thickness of 150nm are evaporated. The length of the mask channel is 50 micrometers, and the width of the mask channel is 1 millimeter.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A low-voltage floating gate photoelectric memory is characterized in that: the grid electrode structure sequentially comprises a substrate (1), a grid electrode (2), a first grid dielectric layer (3), a second grid dielectric layer (4), a charge storage layer (5), a semiconductor layer (6) and a drain-source electrode (7) from bottom to top.
2. The low voltage floating gate flash memory of claim 1, wherein: the first gate dielectric layer (3) is any one of polymethyl methacrylate, polystyrene or poly (4-ethylphenol).
3. The low voltage floating gate flash memory of claim 1, wherein: the second gate dielectric layer (4) is polyvinyl alcohol.
4. The low voltage floating gate flash memory of claim 1, wherein: the charge storage layer (5) is a mixed material of a colloidal quantum dot material and an organic polymer.
5. The low voltage floating gate flash memory of claim 4, wherein: the colloid quantum dot material is perovskite, lead sulfide or cadmium selenide quantum dot material, and the organic polymer is PMMA, PS or PVP.
6. The low voltage floating gate flash memory of claim 1, wherein: the semiconductor layer (6) is pentacene or copper perfluorophthalocyanine and has the thickness of 25-80 nm, and the drain-source electrode (7) is made of gold, silver, copper or aluminum and has the thickness of 25-150 nm.
7. The method for preparing the low-voltage floating gate photoelectric memory of any one of claims 1 to 6, characterized by comprising the following steps:
a. substrate selection and cleaning;
b. a gate electrode (2) is evaporated;
c. preparing a first gate dielectric layer (3)
Dissolving an organic polymer in toluene or N, N-dimethylformamide, spin-coating on a substrate at 800-3000 rpm, and then annealing;
d. preparing a second gate dielectric layer (4)
Heating and dissolving PVA in water, spin-coating the PVA on the first grid dielectric layer (3) at 800-;
e. preparation of the Charge storage layer (5)
Firstly, preparing colloidal quantum dots and an organic polymer solution, then mixing the colloidal quantum dots and the organic polymer solution in proportion, spinning the mixture on a second grid dielectric layer (4) at 800-;
f. a semiconductor layer (6) and a drain-source electrode (7) are deposited.
8. The method of claim 7, wherein: the substrate in the step a is made of glass, silicon wafers or PET materials, the grid electrode (2) in the step b is made of gold, silver, aluminum or copper materials, and the thickness is controlled to be 10-30 nm.
9. The method of claim 7, wherein: in the step c, the concentration of the organic polymer is 8-15 mg/mL, the spin coating time is 25-60 seconds, the thickness is controlled to be 20-50 nm, the annealing temperature is 60-120 ℃, and the annealing time is 5-60 min; in the step d, the concentration of PVA is 1-10 mg/mL, the spin coating time is 25-60 seconds, the thickness is controlled to be 3-20nm, the annealing temperature is 60-120 ℃, and the annealing time is 20-120 min; in the step e, the concentrations of the colloidal quantum dots and the organic polymer solution are both 1-20 mg/mL, the proportion of the colloidal quantum dots and the organic polymer solution is 10% -40%, the spin-coating time is 25-60 seconds, the thickness is controlled to be 3-30nm, the annealing temperature is 60-100 ℃, and the annealing time is 20-60 min.
10. The method of claim 7, wherein: and f, forming a channel by using a mask plate when the drain-source electrode (7) is evaporated in the step f, wherein the length of the channel is controlled to be 10-200 mu m, and the width of the channel is controlled to be 0.5-3 mm.
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