CN113410196A - PROM and FPGA integrated structure based on silicon switching substrate and preparation method thereof - Google Patents

PROM and FPGA integrated structure based on silicon switching substrate and preparation method thereof Download PDF

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Publication number
CN113410196A
CN113410196A CN202110662033.2A CN202110662033A CN113410196A CN 113410196 A CN113410196 A CN 113410196A CN 202110662033 A CN202110662033 A CN 202110662033A CN 113410196 A CN113410196 A CN 113410196A
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China
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silicon
prom
substrate
fpga
integrated structure
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CN202110662033.2A
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Chinese (zh)
Inventor
周黎阳
王挥
吴道伟
杨芳
张辽辽
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Zhuhai Tiancheng Advanced Semiconductor Technology Co ltd
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Xian Microelectronics Technology Institute
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Priority to CN202110662033.2A priority Critical patent/CN113410196A/en
Publication of CN113410196A publication Critical patent/CN113410196A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention discloses a PROM and FPGA integrated structure based on a silicon transfer substrate and a preparation method thereof. An FPGA tube core, a transfer plate and a PROM tube core are sequentially stacked on the TSV silicon transfer substrate, and the TSV silicon transfer substrate, the FPGA tube core, the transfer plate and the PROM tube core are bonded by leads. The FPGA tube core, the transfer plate and the PROM tube core are sequentially stacked and bonded on the TSV silicon transfer substrate; and then a gold wire ball bonding process is adopted, and lead stitching is sequentially carried out on an FPGA chip Pad and a Pad on the TSV silicon transfer substrate, a PROM chip Pad and a Pad on the transfer plate, and a Pad on the transfer plate and a Pad on the TSV silicon transfer substrate, so that the preparation of the integrated structure is completed. The FPGA tube core and the PROM tube core are efficiently integrated on a silicon wafer, and the integrated structure has the advantages of small size, low power consumption and excellent performance.

Description

PROM and FPGA integrated structure based on silicon switching substrate and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor packaging, and relates to a PROM and FPGA integrated structure based on a silicon switching substrate and a preparation method thereof.
Background
FPGAs (field programmable gate arrays) have a rich set of routing resources. The method has the characteristics of high repeatable programming and integration level and low cost, and is widely applied to the field of digital circuit design. Usually, the FPGA must be assigned a PROM (programmable read only memory) to facilitate the moving of the program from the FPGA through the JTAG interface. The conventional PROM and FPGA device layout is mainly based on a PCB substrate, and adopts a tiled layout and a piece of devices, so that the conventional mode has large volume and low integration level and is not beneficial to application occasions with miniaturization requirements; in addition, because the PCB has low wiring density, the transmission speed between the PROM and the FPGA is limited, the operational performance is influenced by the incoming area, and the high-performance calculation is not facilitated.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a PROM and FPGA integrated structure based on a silicon transfer substrate and a preparation method thereof, wherein an FPGA tube core and a PROM tube core are efficiently integrated on a silicon chip, and the PROM and FPGA integrated structure has the advantages of small volume, low power consumption and excellent performance.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a PROM and FPGA integrated structure based on a silicon transfer substrate comprises a TSV silicon transfer substrate;
the TSV silicon transfer substrate, the FPGA tube core, the adapter plate and the PROM tube core are sequentially stacked, and lead bonding is adopted among the TSV silicon transfer substrate, the FPGA tube core, the adapter plate and the PROM tube core.
Preferably, the wiring line width is less than or equal to 10 mu m, and the line spacing is more than or equal to 10 mu m; the Pad size is more than or equal to 50 x 50 mu m; the distance between two corresponding adjacent pads of the same chip is more than or equal to 20 mu m; in the pads corresponding to different chips, the distance between two adjacent pads is more than or equal to 60 mu m; a plurality of silicon through holes are formed in the TSV silicon transfer substrate, and the diameter of each silicon through hole is less than or equal to 30 micrometers.
Preferably, epoxy glue is encapsulated outside the TSV silicon switch substrate, the FPGA die, the switch board and the PROM die.
Preferably, a plurality of solder balls are arranged at the bottom of the TSV silicon transfer substrate to form a BGA ball grid array.
Furthermore, the diameter of the solder ball is 400 μm, the distance between adjacent solder balls is 900 μm, and the distance between the ball center of the outermost solder ball and the side surface of the TSV silicon transfer substrate is more than or equal to 500 μm.
Preferably, gold wire bonding is adopted among the TSV silicon adapter substrate, the FPGA tube core, the adapter plate and the PROM tube core.
Preferably, the interposer is made of silicon and has a thickness of 200 μm.
A preparation method based on any one of the integrated structures comprises the steps that an FPGA (field programmable gate array) tube core, a patch board and a PROM (programmable read only memory) tube core are sequentially stacked and bonded on a TSV (through silicon Via) silicon transfer substrate; and then, adopting a gold wire ball bonding process to sequentially carry out lead stitching on the FPGA chip Pad and the Pad on the TSV silicon switching substrate, the PROM chip Pad and the Pad on the switching plate, and the Pad on the switching plate and the Pad on the TSV silicon switching substrate, so as to finish the preparation of the integrated structure.
Preferably, after the integrated structure is prepared, the integrated structure is filled with epoxy glue.
Preferably, after the integrated structure is prepared, the tin balls are manufactured at the bottom of the TSV silicon switching substrate, and the BGA ball grid array is formed.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the TSV silicon switching substrate is formed by performing high-density wiring on a silicon substrate by adopting a secondary wiring technology, so that secondary wiring can be performed on the TSV silicon switching substrate, the FPGA tube core and the PROM tube core bare chip can be laminated, and the interconnection and three-dimensional integration of the FPGA tube core and the PROM tube core are realized.
Furthermore, the epoxy glue can protect the stacked modules from being damaged in the processes of transportation and subsequent processes.
Furthermore, the solder balls form a BGA ball grid array, which is convenient for welding with a PCB in the subsequent process.
Furthermore, the adapter plate is made of silicon materials, and the problem that the lead bonding is unreliable due to the fact that the distance between the PROM tube core and the TSV silicon adapter substrate is too large is solved.
Drawings
FIG. 1 is a schematic diagram of an integrated structure according to the present invention;
FIG. 2 is a schematic view of the internal connections of the integrated structure of the present invention;
FIG. 3 is a schematic diagram of a TSV silicon interposer substrate of the present invention;
FIG. 4 is a schematic view of die attach of the present invention;
FIG. 5 is a schematic view of a wire bond of the present invention;
FIG. 6 is a schematic view of the epoxy glue encapsulation of the present invention;
FIG. 7 is a schematic view of bottom mounted balls according to the present invention.
Wherein: 1-gold wire; 2-PROM die; 3-a patch panel; 4-FPGA tube core; 5-TSV silicon transfer substrates; 6-through silicon vias; 7-solder ball; 8-epoxy glue.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1, in order to provide the PROM and FPGA integrated structure based on the silicon interposer substrate, an FPGA die 4, an interposer 3, and a PROM die 2 are sequentially stacked on a TSV silicon interposer substrate 5, and the TSV silicon interposer substrate 5, the FPGA die 4, the interposer 3, and the PROM die 2 are bonded by using a bonding adhesive, and then bonded by using gold wires 1, and then subjected to epoxy glue 8 encapsulation and bottom ball mounting.
The layout and wiring rules of the TSV silicon transfer substrate 5 are as follows: according to the chip information, module information interconnection, through holes and BGA design on the TSV silicon through-connection substrate 5 are carried out, and the design rule is as follows: the wiring line width is less than or equal to 10 mu m, and the line spacing is more than or equal to 10 mu m; the Pad size is more than or equal to 5050 μm; the distance between two corresponding adjacent pads of the same chip is more than or equal to 20 mu m; in the pads corresponding to different chips, the distance between two adjacent pads is more than or equal to 60 mu m; a plurality of through silicon holes 6 are formed in the TSV silicon transfer substrate 5, and the diameter of each through silicon hole 6 is less than or equal to 30 micrometers; the diameter of the solder ball 7 is 400 μm, the distance between the adjacent solder balls 7 is 900 μm, and the distance between the ball center of the outermost solder ball 7 and the side surface of the TSV silicon transfer substrate 5 is not less than 500 μm.
The TSV silicon switching substrate 5 achieves information interconnection between the FPGA and the PROM, through silicon vias 6 and BGA design on a silicon chip. The manufacturing process of the TSV silicon transfer substrate 5 in this embodiment is as follows: marking and cleaning a silicon chip, patterning a TSV hole, etching a TSV deep silicon hole, depositing a SiO2 insulating layer on the hole wall and the wafer surface, sputtering a Ti/Cu seed layer, filling the TSV with electroplated copper, CMP, stress relief annealing, preparing a front RDL1 layer (sputtering, electroplating and corrosion), a front PI layer, a front UBM layer (copper plating and nickel-gold surface treatment), temporarily bonding a Carrier sheet, thinning the back, exposing a TSV tail, depositing a SiO2 layer (2-3 mu m) on the back, exposing copper on the back CMP, exposing a back RDL1 layer, a back PI layer, a back UBM layer (copper plating/SnAg solder) (CP test), debonding and scribing.
The FPGA tube core 4 adopts a domestic BQR2V3000 tube core, has 300 ten thousand system gates, supports the maximum 300MHz system working frequency, adopts a 0.13 mu m 1P7M + RDL silicon gate CMOS process, and has the chip size: 16.05mm by 13.88mm, the thickness before thinning is 725 μm, and the thickness after thinning is 400 μm.
The adapter plate 3 is made of silicon and is used for solving the problem that the distance between the PROM tube core 2 and the TSV silicon adapter substrate 5 is too large, lead bonding is unreliable, and the thickness of the PROM tube core is 200 mu m.
The PROM tube core 2 is selected from a national micro SM32PV048 tube core and is used as a peripheral configuration device of the FPGA for storing logic loading files. The tube core is divided into a parallel loading mode and a serial loading mode, wherein the serial loading mode is selected.
As shown in fig. 2, a schematic diagram of the connections of the FPGA die 4 and the PROM die 2 is shown.
In this example, the diameter of the gold wire 1 is 18 μm.
The preparation method of the PROM and FPGA integrated structure based on the silicon switching substrate comprises the following process implementation steps:
(1) as shown in FIG. 3, the TSV silicon interposer substrate 5 is fabricated
And finishing through hole electroplating, thinning and surface rewiring manufacturing of the TSV silicon through-connection substrate 5 according to the TSV silicon through-connection substrate 5 process and the surface wiring design layout.
(2) As shown in FIG. 4, FPGA and PROM chip are stacked
Firstly, bonding the FPGA chip to a specific area of the TSV silicon switching substrate 5 by using a mounting adhesive according to the layout design.
Secondly, the adapter plate 3 and the FPGA chip are bonded together by using a mounting adhesive, and attention is paid to the fact that the size of the adapter plate 3 cannot exceed the Pad area of the chip and the bonding wire is not affected.
And bonding the PROM chip and the adapter plate 3 together by using mounting glue.
(3) As shown in fig. 5, wire bonding
Firstly, performing lead bonding on the FPGA chip Pad and the Pad on the TSV silicon switching substrate 5 by using a gold wire 1 with the diameter of 18 microns by using a gold wire ball bonding process;
secondly, performing lead bonding on a PROM chip Pad and a Pad on the adapter plate 3 by using a gold wire 1 with the diameter of 18 mu m by adopting a gold wire ball bonding process;
thirdly, conducting wire bonding on the Pad on the adapter plate 3 and the Pad on the TSV silicon adapter substrate 5 by using a gold wire 1 with the diameter of 18 microns by adopting a gold wire ball bonding process.
(4) As shown in FIG. 6, epoxy glue 8 potting
In order to protect the stacked modules from being damaged in the transportation and subsequent processes, the modules are protected by a glue pouring method, cofferdams are manufactured around the TSV silicon switching substrate 5 by using a specific mould and insulating glue before glue pouring so as to form regular glue pouring modules in the subsequent process, the height of the cofferdams around the TSV silicon switching substrate is kept consistent under the condition that the process requirements are met, and the size of the final glue pouring module is reduced as much as possible. After the cofferdam is manufactured, the laminated module is filled with epoxy glue 8, the gold threads are fixed and protected, and the glue filling surface is ensured to be on the same plane.
(5) As shown in fig. 7, the bottom is planted with balls
And manufacturing a solder ball 7 at the bottom of the TSV silicon switching substrate 5 to form a BGA ball grid array, wherein the solder ball 7 corresponds to the through silicon via 6, and the solder ball 7 is positioned at the end part of the through silicon via 6, so that the solder ball is convenient to weld with a PCB in the subsequent process.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (10)

1. A PROM and FPGA integrated structure based on a silicon switching substrate is characterized by comprising a TSV silicon switching substrate (5);
the TSV silicon transfer substrate (5) is sequentially stacked with the FPGA tube core (4), the adapter plate (3) and the PROM tube core (2), and lead bonding is adopted among the TSV silicon transfer substrate (5), the FPGA tube core (4), the adapter plate (3) and the PROM tube core (2).
2. The PROM and FPGA integrated structure based on silicon switch-over substrate as claimed in claim 1, wherein the wiring line width is not more than 10 μm, the line spacing is not less than 10 μm; the Pad size is more than or equal to 50 x 50 mu m; the distance between two corresponding adjacent pads of the same chip is more than or equal to 20 mu m; in the pads corresponding to different chips, the distance between two adjacent pads is more than or equal to 60 mu m; a plurality of through silicon holes (6) are formed in the TSV silicon transfer substrate (5), and the diameter of each through silicon hole (6) is less than or equal to 30 micrometers.
3. The PROM and FPGA integrated structure based on silicon switch substrate as claimed in claim 1, wherein the exterior of TSV silicon switch substrate (5), FPGA die (4), switch board (3) and PROM die (2) is encapsulated with epoxy glue (8).
4. The PROM and FPGA integrated structure based on silicon transition substrate of claim 1, wherein a plurality of solder balls (7) are disposed on the bottom of TSV silicon transition substrate (5) to form a BGA ball grid array.
5. The PROM and FPGA integrated structure based on silicon switch-over substrate as claimed in claim 4, wherein the ball diameter of the solder balls (7) is 400 μm, the distance between the adjacent solder balls (7) is 900 μm, and the distance between the ball center of the outermost solder ball (7) and the TSV silicon switch-over substrate (5) side is not less than 500 μm.
6. The PROM and FPGA integrated structure based on silicon switch substrate as claimed in claim 1, wherein, gold wires (1) are used for bonding among the TSV silicon switch substrate (5), the FPGA die (4), the switch board (3) and the PROM die (2).
7. The integrated PROM and FPGA structure based on a silicon interposer substrate as claimed in claim 1, wherein the interposer (3) is made of silicon and has a thickness of 200 μm.
8. A method for preparing an integrated structure based on any one of claims 1-7, characterized in that, an FPGA die (4), an adapter plate (3) and a PROM die (2) are stacked and bonded on a TSV silicon adapter substrate (5) in sequence; and then, carrying out lead stitching on the FPGA chip Pad and the Pad on the TSV silicon switching substrate (5), the PROM chip Pad and the Pad on the adapter plate (3), and the Pad on the adapter plate (3) and the Pad on the TSV silicon switching substrate (5) in sequence by adopting a gold wire ball bonding process to finish the preparation of the integrated structure.
9. The method for preparing the PROM and FPGA integrated structure based on the silicon switch-over substrate as recited in claim 8, wherein after the integrated structure is prepared, the integrated structure is filled with epoxy glue (8).
10. The method for preparing the PROM and FPGA integrated structure based on the silicon switch substrate as claimed in claim 8, wherein after the integrated structure is prepared, solder balls (7) are made on the bottom of the TSV silicon switch substrate (5) to form a BGA ball grid array.
CN202110662033.2A 2021-06-15 2021-06-15 PROM and FPGA integrated structure based on silicon switching substrate and preparation method thereof Pending CN113410196A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040150084A1 (en) * 2003-01-29 2004-08-05 Sharp Kabushiki Kaisha Semiconductor device
US20060055018A1 (en) * 2004-09-14 2006-03-16 Masahiro Sekiguchi Semiconductor device
CN101150120A (en) * 2006-09-20 2008-03-26 三星电子株式会社 Stacked semiconductor package, method of fabrication, and method of wire-bond monitoring
CN105428347A (en) * 2015-12-28 2016-03-23 中南大学 Improvement method for stacked package of three-dimensional chip of microsystem
US20190259695A1 (en) * 2018-02-22 2019-08-22 Xilinx, Inc. High density routing for heterogeneous package integration
CN112802834A (en) * 2020-11-23 2021-05-14 西安微电子技术研究所 SiP module based on silicon switching four-layer three-dimensional stacking and manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040150084A1 (en) * 2003-01-29 2004-08-05 Sharp Kabushiki Kaisha Semiconductor device
US20060055018A1 (en) * 2004-09-14 2006-03-16 Masahiro Sekiguchi Semiconductor device
CN101150120A (en) * 2006-09-20 2008-03-26 三星电子株式会社 Stacked semiconductor package, method of fabrication, and method of wire-bond monitoring
CN105428347A (en) * 2015-12-28 2016-03-23 中南大学 Improvement method for stacked package of three-dimensional chip of microsystem
US20190259695A1 (en) * 2018-02-22 2019-08-22 Xilinx, Inc. High density routing for heterogeneous package integration
CN112802834A (en) * 2020-11-23 2021-05-14 西安微电子技术研究所 SiP module based on silicon switching four-layer three-dimensional stacking and manufacturing method

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