CN113408229A - Method for comparing and observing FPGA internal signals based on observation hardware circuit - Google Patents

Method for comparing and observing FPGA internal signals based on observation hardware circuit Download PDF

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CN113408229A
CN113408229A CN202110685601.0A CN202110685601A CN113408229A CN 113408229 A CN113408229 A CN 113408229A CN 202110685601 A CN202110685601 A CN 202110685601A CN 113408229 A CN113408229 A CN 113408229A
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signal
observation
path
point
circuit
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CN113408229B (en
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单悦尔
井站
范继聪
徐彦峰
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a method for comparing and observing signals in an FPGA (field programmable gate array) based on an observation hardware circuit, which relates to the technical field of the FPGA and is realized by carrying out hardware improvement design on an FPGA chip and combining with corresponding software function configuration, an independent observation hardware circuit is added in the FPGA chip, and a configuration code stream is generated by taking the layout position of the observation hardware circuit as a constraint condition for the signals.

Description

Method for comparing and observing FPGA internal signals based on observation hardware circuit
Technical Field
The invention relates to the technical field of FPGA, in particular to a method for comparing and observing signals in FPGA based on an observation hardware circuit.
Background
When a user circuit is implemented on an FPGA and normally operates on the FPGA, in order to determine that an operation process of the user circuit on the FPGA is correct and conforms to a design concept, it is generally required to observe behaviors or waveforms of certain specific signals inside the user circuit.
At present, a user circuit is implemented on an FPGA and layout and routing are completed, and at this time, part of resources inside the FPGA are occupied by the user circuit, but part of the resources are still left unused. And then selecting a signal to be observed of the user circuit, wherein the signal to be observed corresponds to the internal layout wiring resource of the FPGA, and connecting the signal to be observed to an unoccupied pin as an observation pin through the unoccupied winding resource in the FPGA. And adding the selected winding path of the signal to be observed and the observation pin into the layout wiring of the user circuit to form new layout wiring, downloading a code stream generated by the new layout wiring to the FPGA for normal operation, and observing the signal to be observed by the observation pin at the moment.
However, in this method, if there is no unoccupied pin available after the FPGA implements the user circuit, or the signal to be observed cannot be connected to the corresponding pin by using the unoccupied winding resources, the above-mentioned functions cannot be implemented, so that the existing method is limited, and it cannot be guaranteed that the signal to be observed is successfully observed each time.
Disclosure of Invention
The invention provides a method for comparing and observing FPGA internal signals based on an observation hardware circuit aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
a method for comparing and observing internal signals of an FPGA (field programmable gate array) based on an observation hardware circuit comprises the following steps:
determining a user circuit running on an FPGA chip, wherein the FPGA chip internally comprises programmable logic resources and an observation hardware circuit, and the observation hardware circuit comprises an observation point and a first observation pin which are connected through a first observation path, and a reference point and a second observation pin which are connected through a second observation path; the observation point and the reference point are respectively an output port of the programmable logic resource in the FPGA chip; the first observation path and the second observation path respectively have corresponding preset time delay;
laying out a circuit structure of a signal to be observed generated in a user circuit at an observation point, laying out a circuit structure of a reference signal corresponding to the signal to be observed at the reference point as a constraint condition, generating a configuration code stream corresponding to the user circuit based on programmable logic resources in an FPGA chip under the constraint condition, and loading the configuration code stream onto the FPGA chip;
the FPGA chip forms a user circuit based on the configuration code stream, and in the operation process of the user circuit, a signal to be observed at an observation point is output through the first observation pin, a reference signal at a reference point is output through the second observation pin, and the reference signal and the signal to be observed are compared and observed.
The further technical scheme is that the observation hardware circuit further comprises a first path gating circuit, a first multi-bit selector and a first debugging pin, wherein each signal point connected with the input end of the first path gating circuit is connected to the first observation pin through different paths in the first path gating circuit, and a first multi-bit register is connected with and controls the connection and disconnection of different paths of the first path gating circuit;
the observation point is one of the signal points connected with the input end of the first path gating circuit, and the first multi-bit register controls to gate the path from the observation point to the first observation pin according to a first debugging instruction acquired from the first debugging pin.
The observation hardware circuit further comprises a second path gating circuit, a second multi-bit selector and a second debugging pin, wherein each signal point connected with the input end of the second path gating circuit is connected to the second observation pin through different paths in the second path gating circuit, and a second multi-bit register is connected with and controls the connection and disconnection of different paths of the second path gating circuit;
and the reference point is one of the signal points connected with the input end of the second path gating circuit, and the second multi-bit register controls a path from the gating reference point to the second observation pin according to a second debugging instruction acquired from the second debugging pin.
The method comprises the following steps that a first path selection circuit is connected with a first signal point through a first winding path, a second path selection circuit is connected with a second signal point through a second winding path, and the first path selection circuit and the second path selection circuit are connected with the same winding path; the signal point connected to the first path selection circuit in the group of signal points is the observation point, and the other signal point is the reference point.
The further technical scheme is that the input ends of the first path gating circuit and the second path gating circuit are connected with a plurality of same signal points, each signal point forms an H-shaped tree structure, so that the time delay from each signal point to the first path gating circuit is the same as that from each signal point to the second path gating circuit, and the observation point and the reference point are any two different signal points.
When the first path gating circuit gates a signal point as an observation point, the second path gating circuit gates different signal points as reference signals, and the same signal to be observed corresponds to a plurality of different reference signals;
when the first path gating circuit gates different signal points as observation points, the second path gating circuit gates the same signal point as a reference signal, and then different signals to be observed correspond to the same reference signal, or the second path gating circuit gates different signal points as reference signals, and then different signals to be observed correspond to different reference signals.
The further technical scheme is that a plurality of different reference signals are synchronous signals or asynchronous signals, and the frequencies of the plurality of different reference signals are the same or different.
The method further adopts the technical scheme that the reference point is the output end of the global clock buffer, the second observation path is provided with a time delay adjusting circuit, and the FPGA chip configures the time delay of the time delay adjusting circuit when forming the user circuit based on the configuration code stream so that the time delay difference value between any signal point at the input ends of the second observation path and the first path selection path and the path from the first observation pin is smaller than a preset threshold value.
The further technical scheme is that the reference point is arranged at a preset position, so that the time delay difference value between any signal point of the input ends of the second observation path and the first path gating circuit and the path from the first observation pin is smaller than a preset threshold value.
The further technical scheme is that a plurality of signal points connected with the input end of the first path gating circuit are distributed in a determinant manner, and a reference point is positioned at the central position of any row of signal points or any column of signal points; or, the plurality of signal points connected to the input end of the first path gating circuit are distributed in the signal point area with the predetermined range, and then the reference point is located at the center position of all the signal point areas.
The further technical scheme is that the reference signal and the signal to be observed corresponding to the reference signal are synchronous signals, or are common-frequency signals, or the frequency of the reference signal is integer multiple frequency of the signal to be observed.
The further technical scheme is that a reference signal corresponding to a signal to be observed is a main clock signal or a preset user clock signal.
The FPGA chip is a multi-die FPGA and comprises a plurality of FPGA dies with circuit connection relations inside, and a first observation pin and a second observation pin are respectively led out from each FPGA die.
The beneficial technical effects of the invention are as follows:
the method is realized by carrying out hardware improvement design on an FPGA chip and combining with corresponding software function configuration, and generates a configuration code stream by adding an independent observation hardware circuit in the FPGA chip and taking the layout position of the observation hardware circuit as a constraint condition for the signal.
Drawings
FIG. 1 is a circuit diagram of observation hardware circuitry according to one embodiment of the present application.
FIG. 2 is a circuit diagram of an observation hardware circuit of another embodiment of the present application.
FIG. 3 is a circuit diagram of an observation hardware circuit of another embodiment of the present application.
FIG. 4 is a circuit diagram of an observation hardware circuit of another embodiment of the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a method for observing internal signals of an FPGA based on observation hardware circuit comparison, which is realized based on hardware improved design of an FPGA chip and corresponding software function configuration, and is divided into two parts to be respectively introduced:
firstly, improving and designing the hardware of an FPGA chip.
Besides conventional programmable logic resources, the FPGA chip in the application also designs a special observation hardware circuit, namely, additionally adds hardware resources. The observation hardware circuit comprises an observation point 2 and a first observation pin 3 connected by a first observation path 1, and a reference point 5 and a second observation pin 6 connected by a second observation path 4.
The observation point 2 and the reference point 5 are respectively an output port of the programmable logic resource inside the FPGA chip. The programmable logic resources in the FPGA chip at least comprise a programmable module and an interconnection resource module, wherein the programmable module comprises a CLB (basic logic unit), a BRAM (branch-tree-based memory), an IOB (input/output bus), a DSP (digital signal processor), a PC (personal computer) and the like, the interconnection resource module comprises a winding box and an interconnection line, and optionally, an observation point 2/reference point 5 in an observation hardware circuit is an output port of the programmable module or an output port of the winding box in the interconnection resource module. As shown in fig. 1, the existing FPGA chip generally adopts a Column-Based architecture, and the programmable logic resources 7 are arranged in the FPGA chip according to a determinant structure, so that the observation points 2 and the reference points 5 of the hardware resources can be set at the output ports of the corresponding programmable logic resources 7 according to needs, and then are respectively connected to the corresponding observation pins through the special observation lines 3.
The first observation path 1 and the second observation path 4 respectively have respective corresponding predetermined time delays, and the time delays can be adjusted by adjusting the winding mode of the observation paths, so that the observation time delays meet the preset requirements. In the present application, the delay difference between the first observation path 1 and the second observation path 4 is generally configured to be smaller than a predetermined threshold, that is, the delays of the first observation path 1 and the second observation path 4 are ensured to be similar within an error range. For example, a typical layout is shown in fig. 1, the observation point 2 and the reference point 5 are disposed at a distance not exceeding a set value, and the first observation path 1 and the second observation path 4 are wound in the same manner.
The observation hardware circuit is a hardware resource manufactured and realized based on a conventional circuit component, so that the observation hardware circuit can be realized by adopting a conventional FPGA manufacturing process.
And secondly, correspondingly configuring software.
Based on the FPGA chip with the built-in special observation hardware circuit, the user circuit running on the FPGA chip is determined, and the user circuit is a circuit structure which needs to be realized by utilizing programmable logic resources in the FPGA chip and is used for realizing user design functions.
And laying out a circuit structure of a signal to be observed generated in the user circuit at an observation point 2, laying out a circuit structure of a reference signal corresponding to the signal to be observed at a reference point 5 as a constraint condition, generating a configuration code stream corresponding to the user circuit based on programmable logic resources in the FPGA chip under the constraint condition, and loading the configuration code stream onto the FPGA chip. The FPGA chip forms a corresponding user circuit based on the configuration code stream, a signal to be observed in the user circuit is realized by a programmable logic resource at the observation point 2, and a reference signal corresponding to the signal to be observed is realized by a reference point 5. Therefore, in the operation process of the user circuit, a signal to be observed is transmitted to the outside of the FPGA chip through the observation point 2 at the output port of the programmable logic resource where the signal to be observed is located and connected to the first observation pin 3 through the first observation path 1 to be observed, and simultaneously, a reference signal corresponding to the signal to be observed is transmitted to the outside of the FPGA chip through the reference point 5 at the output port of the programmable logic resource where the signal to be observed is located and connected to the second observation pin 6 through the second observation path 4 to be observed, that is, the signal to be observed and the reference signal corresponding to the signal to be observed can be simultaneously output and compared to be observed so as to determine the relative behavior of the signal to be observed with respect to the reference signal to meet the corresponding observation requirement, and the reference signal of the signal to be observed is a signal related to the signal to be observed and is configured according to actual requirements. Optionally, the reference signal and the signal to be observed corresponding to the reference signal are synchronization signals, or are common-frequency signals, or the frequency of the reference signal is an integer multiple frequency of the signal to be observed. When the signal type is selected, the reference signal corresponding to the signal to be observed is the main clock signal or the predetermined user clock signal. A typical application of comparison is that the specific timing of the signal to be observed can be determined by comparing the signal to be observed and its reference signal to the observation. A further typical application is that the outputs of two Clock trees can be used as the signal to be observed and its reference signal, respectively, to determine the Clock Skew (Clock Skew).
Further optionally, in another embodiment, the FPGA chip of the present application is a multi-die FPGA and includes a plurality of FPGA dies having a circuit connection relationship inside, and then a first observation pin and a second observation pin are respectively led out from each FPGA die, and the circuit is respectively formed inside each FPGA die, so that each FPGA die can be observed according to the method provided by the present application.
One implementation of the observation hardware circuit is to set a signal point as observation point 2 at only one output port of the programmable logic resource. The other implementation mode is that a plurality of signal points are arranged at output ports of a plurality of programmable logic resources, an observation point 2 is selected according to actual needs, and the observation hardware circuit is optional and further comprises a first path selection circuit, a first multi-bit selector and a first debugging pin, wherein each signal point connected with the input end of the first path selection circuit is connected to the first observation pin through different paths inside the first path selection circuit, a first multi-bit register is connected with and controls the connection and disconnection of different paths of the first path selection circuit, and the signal points are output ports of the programmable logic resources. In this embodiment, the observation point is one of the signal points connected to the input end of the first path gating circuit, and the first multi-bit register controls the path from the gating observation point to the first observation pin according to a first debug instruction SEL1 acquired from the first debug pin, where the signal point communicated with the first observation pin is the observation point.
When a plurality of signal points can be selected as observation points, the reference points can be realized in various ways, and can be mainly classified into the following two categories:
the first case: the reference point 5 corresponding to the observation point 2 can also be selected from signal points at the output ports of a plurality of programmable logic resources. In this embodiment, the observation hardware circuit further includes a second path gating circuit, a second multi-bit selector, and a second debug pin, each signal point connected to the input terminal of the second path gating circuit is connected to the second observation pin through a different path inside the second path gating circuit, and the second multi-bit register is connected to and controls on/off of a different path of the second path gating circuit. The reference point is one of the signal points connected with the input end of the second path gating circuit, the signal at the signal point selected as the reference point is the reference signal, and the second multi-bit register controls the path from the gating reference point to the second observation pin according to a second debugging instruction SEL2 acquired from the second debugging pin.
In this embodiment, it is necessary to ensure that the difference in time delay between a first observation path formed by the signal points selected as observation points 2 and a second observation path formed by the signal points selected as reference points 5 is less than a predetermined threshold, and there are two different implementations:
(1) the signal points selected to form the observation points are independent of the signal points selected to form the reference points. Each signal point connected with the input end of the first path gating circuit and each signal point connected with the input end of the second path gating circuit respectively form a group of signal points correspondingly, the arrangement distance between two signal points in the group of signal points does not exceed a preset distance, and the signal points are connected to corresponding observation pins through the same winding path. For example, in fig. 2, the signal point at a1 and the signal point at B1 form a group of signal points, the signal point at a2 and the signal point at B2 form a group of signal points, and so on. The signal point connected to the first path selection circuit in the group of signal points is an observation point, and the other signal point is a reference point, for example, when the signal point at a1 is selected as the observation point, the corresponding signal point at B1 is the reference point 5.
In this case, the first path selection circuit and the second path selection circuit may be implemented by the same circuit, for example, by using one or more multiplexers forming a cascade structure.
In this embodiment, since the signal points selected as the observation point and the reference point form a group of corresponding signal points, when the first path gating circuit gates one signal point as the observation point, the second path gating circuit needs to gate a corresponding signal point as the reference signal, and thus one signal to be observed usually corresponds to one reference signal, but the reference signals corresponding to different signals to be observed may be the same or different. For example, the signal to be observed at a1 corresponds to the reference signal at B1, the signal to be observed at a2 corresponds to the reference signal at B2, and the reference signal at B1 and the reference signal at B2 may be the same or different.
(2) The signal points for selecting to form the observation points and the signal points for selecting to form the reference points share a phenomenon, that is, one signal point may be selected as an observation point or may also be selected as a reference point. The input ends of the first path gating circuit and the second path gating circuit are connected to the same plurality of signal points, and each signal point forms an H-tree structure, so that the time delays from each signal point to the first path gating circuit and the second path gating circuit are the same, and the observation point and the reference point are any two different signal points. In this embodiment, the first path gating circuit and the second path gating circuit may be implemented by the same circuit, for example, by one or more multiplexers forming a cascade structure, and the connection mode with each signal point may be set according to actual conditions, and only needs to make each signal point form an H-tree structure, for example, fig. 3 shows a connection mode, which includes, for example, four first-stage multiplexers MUX1-1, MUX1-2, MUX1-3, and MUX1-4 respectively connected to each signal point, and then the four first-stage multiplexers are connected to the first observation pin through MUX2, and the second path gating circuit also adopts this circuit structure, which is not shown in the figure.
Because the time delays from any two signal points to the first path gating circuit and the second path gating circuit are the same, and the difference value between the time delay from the first path gating circuit to the first observation pin and the time delay from the second path gating circuit to the second observation pin is not more than the preset threshold value, when any two signal points are selected as the observation point and the reference point, the time delay difference value between the two formed observation paths is less than the preset threshold value.
In this embodiment, since any signal point can be selected as the observation point/reference point, when the first path gating circuit gates one signal point as the observation point, the second path gating circuit gates a different signal point as the reference signal, and the same signal to be observed corresponds to a plurality of different reference signals. When the first path gating circuit gates different signal points as observation points, the second path gating circuit gates the same signal point as a reference signal, and then different signals to be observed correspond to the same reference signal, or the second path gating circuit gates different signal points as reference signals, and then different signals to be observed correspond to different reference signals. Taking the signals at different signal points as an example, for example, when the signal point at K1 is selected as the observation point, the signal point at K2 may be gated as a reference point, or the signal point at K2 may be gated as a reference point, and then the corresponding signal to be observed at K1 may correspond to different signals. For another example, the signal point at K2 may be gated as the reference point when the signal point at K1 is selected as the observation point, and the signal point at K2 may also be gated as the reference point when the signal point at K3 is selected as the observation point, or the signal point at K4 may be gated as the reference point when the signal point at K3 is selected as the observation point.
In both cases, the multiple different reference signals are synchronous signals or asynchronous signals, and the frequencies of the multiple different reference signals are the same or different.
The second case: only one signal point is set as a reference point, in this case, it needs to be ensured that when different signal points are selected as observation points, the delay difference values between the first observation path and the second observation path are all smaller than a predetermined threshold, and there are two different implementation manners:
(1) if the reference point is the output end of the global clock buffer (GBUF), the second observation path is provided with the delay adjusting circuit, and as shown in fig. 4, the FPGA chip configures the delay of the delay adjusting circuit when forming the user circuit based on the configuration code stream, so that the delay difference between any signal point at the input end of the second observation path and the first path selection path and the path from the first observation pin is smaller than the predetermined threshold.
(2) The reference point is arranged at a preset position, so that the time delay difference value between any signal point of the input end of the second observation path and the first path selection circuit and the path from the first observation pin is smaller than a preset threshold value, and when any signal point of the input end of the first path selection circuit is selected as an observation point, the requirement that the time delay difference value between the two observation paths is smaller than the preset threshold value can be met. The reference point may be generally arranged at a central position of a number of signal points that may be selected as reference points to which the input terminals of the first path selection circuit are connected. Optionally, the plurality of signal points connected to the input end of the first path gating circuit are distributed in a determinant manner, and the reference point is located at the center position of any row of signal points or any column of signal points. Or, the plurality of signal points connected to the input end of the first path gating circuit are distributed in the signal point area with the predetermined range, and then the reference point is located at the center position of all the signal point areas.
Based on the second kind of situation, because only one signal point is set as the reference point, when different signal points are selected as observation points, different signals to be observed usually correspond to the same reference signal.
In practical applications, no matter the first kind of situation or the second kind of situation is adopted, a hardware circuit adopting a set of reference points outputs one reference signal as an example, but actually, a plurality of sets of circuits can be arranged so as to output a plurality of reference signals at the same time.

Claims (13)

1. A method for observing internal signals of an FPGA based on comparison of an observation hardware circuit is characterized by comprising the following steps:
determining a user circuit running on an FPGA chip, wherein the FPGA chip internally comprises programmable logic resources and an observation hardware circuit, and the observation hardware circuit comprises an observation point and a first observation pin which are connected through a first observation path, and a reference point and a second observation pin which are connected through a second observation path; the observation point and the reference point are respectively an output port of the programmable logic resource in the FPGA chip; the first observation path and the second observation path respectively have respective corresponding predetermined time delays;
laying out a circuit structure of a signal to be observed generated in the user circuit at the observation point, laying out a circuit structure of a reference signal corresponding to the signal to be observed at the reference point as a constraint condition, generating a configuration code stream corresponding to the user circuit based on programmable logic resources in the FPGA chip under the constraint condition, and loading the configuration code stream onto the FPGA chip;
and the FPGA chip forms the user circuit based on the configuration code stream, outputs a signal to be observed at the observation point through the first observation pin and outputs a reference signal at the reference point through the second observation pin in the operation process of the user circuit, and compares and observes the reference signal and the signal to be observed.
2. The method according to claim 1, wherein the observation hardware circuit further comprises a first path-selection circuit, a first multi-bit selector and a first debug pin, wherein each signal point connected to an input terminal of the first path-selection circuit is connected to the first observation pin through a different path inside the first path-selection circuit, and the first multi-bit register is connected to and controls the connection and disconnection of different paths of the first path-selection circuit;
and if the observation point is one of the signal points connected with the input end of the first path gating circuit, the first multi-bit register controls to gate the path from the observation point to the first observation pin according to a first debugging instruction acquired from the first debugging pin.
3. The method according to claim 2, wherein the observation hardware circuit further comprises a second path gating circuit, a second multi-bit selector and a second debug pin, wherein each signal point connected to the input terminal of the second path gating circuit is connected to the second observation pin through a different path inside the second path gating circuit, and the second multi-bit register is connected to and controls the connection and disconnection of different paths of the second path gating circuit;
and if the reference point is one of the signal points connected with the input end of the second path gating circuit, the second multi-bit register controls to gate the path from the reference point to the second observation pin according to a second debugging instruction acquired from the second debugging pin.
4. The method according to claim 3, wherein each signal point connected with the input end of the first path selection circuit and each signal point connected with the input end of the second path selection circuit respectively form a group of signal points correspondingly, and the arrangement distance between two signal points in the group of signal points does not exceed a preset distance and is connected to the corresponding observation pins through the same winding path; the signal point connected to the first path selection circuit in the group of signal points is an observation point, and the other signal point is a reference point.
5. The method of claim 3,
the input ends of the first path gating circuit and the second path gating circuit are connected with the same plurality of signal points, each signal point forms an H-shaped tree structure, so that the time delay from each signal point to the first path gating circuit is the same as that from each signal point to the second path gating circuit, and the observation point and the reference point are any two different signal points respectively.
6. The method of claim 5,
when the first path gating circuit gates one signal point as an observation point, the second path gating circuit gates different signal points as reference signals, and the same signal to be observed corresponds to a plurality of different reference signals;
when the first path gating circuit gates different signal points as observation points, the second path gating circuit gates the same signal point as a reference signal, and then different signals to be observed correspond to the same reference signal, or the second path gating circuit gates different signal points as reference signals, and then different signals to be observed correspond to different reference signals.
7. The method of claim 6, wherein the plurality of different reference signals are synchronous signals or asynchronous signals, and wherein the frequencies of the plurality of different reference signals are the same or different.
8. The method according to claim 2, wherein the reference point is an output end of a global clock buffer, a delay adjusting circuit is disposed in the second observation path, and the FPGA chip configures a delay of the delay adjusting circuit when forming the user circuit based on the configuration code stream, so that a delay difference between any signal point at an input end of the second observation path and the first path gating circuit and a path from the first observation pin is smaller than a predetermined threshold.
9. The method according to claim 2, wherein the reference point is arranged at a predetermined position such that a delay difference between the second observation path and a path from any signal point at the input of the first path gating circuit to the first observation pin is smaller than a predetermined threshold.
10. The method according to claim 9, wherein the signal points connected to the input end of the first path gating circuit are distributed in a determinant manner, and the reference point is located at the center position of any row of signal points or any column of signal points; or, the plurality of signal points connected to the input end of the first path gating circuit are distributed in a signal point area with a predetermined range, and then the reference point is located at the center position of all the signal point areas.
11. The method according to claim 1, wherein the reference signal and the corresponding signal to be observed are synchronous signals, or are common-frequency signals, or the frequency of the reference signal is an integer multiple of the frequency of the signal to be observed.
12. The method of claim 1, wherein the reference signal corresponding to the signal to be observed is a master clock signal or a predetermined user clock signal.
13. The method according to claim 1, wherein the FPGA chip is a multi-die FPGA and includes a plurality of FPGA dies having a circuit connection relationship therein, and each FPGA die leads out a first observation pin and a second observation pin respectively.
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CN104617928A (en) * 2015-01-13 2015-05-13 复旦大学 Clock network traversing testing method based on FPGA (Field Programmable Gate Array) hardware structure
CN110069827A (en) * 2019-03-28 2019-07-30 广东高云半导体科技股份有限公司 Placement-and-routing's method and apparatus of the online logic analyser of FPGA

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* Cited by examiner, † Cited by third party
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JP2007292492A (en) * 2006-04-21 2007-11-08 Aoi Electronics Co Ltd Circuit verification apparatus and circuit verification method
CN102541707A (en) * 2010-12-15 2012-07-04 中国科学院电子学研究所 Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method
CN104617928A (en) * 2015-01-13 2015-05-13 复旦大学 Clock network traversing testing method based on FPGA (Field Programmable Gate Array) hardware structure
CN110069827A (en) * 2019-03-28 2019-07-30 广东高云半导体科技股份有限公司 Placement-and-routing's method and apparatus of the online logic analyser of FPGA

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