CN113393557A

CN113393557A - Wafer map file generation method, device, equipment and storage medium

Info

Publication number: CN113393557A
Application number: CN202110606202.0A
Authority: CN
Inventors: 王英广; 王健; 孔晓琳; 栗伟斌; 李安平
Original assignee: Shenzhen Mifeitake Technology Co ltd
Current assignee: Shenzhen Mifeitake Technology Co ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2021-09-14

Abstract

The application provides a method, a device, equipment and a storage medium for generating a wafer map file, wherein the method is applied to transfer equipment, the transfer equipment is respectively connected with a probe station and test equipment, and the method comprises the following steps: the method comprises the steps of receiving a first test instruction which is sent by a probe station and comprises position information of a first chip to be tested on a wafer, sending a second test instruction to test equipment according to the first test instruction so as to instruct the test equipment to test the first chip, receiving a first test response instruction which is sent by the test equipment and comprises a test result of the first chip, and generating a wafer map file with preset file rules according to the first test instruction and the first test response instruction. Because the transfer equipment self-defines a preset file rule, no matter what type of probe station is used for wafer test, the transfer equipment can generate a wafer drawing file with uniform file rules, and production control and data statistics, analysis and processing are facilitated.

Description

Wafer map file generation method, device, equipment and storage medium

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a method, an apparatus, a device, and a storage medium for generating a wafer map file.

Background

Semiconductor manufacturing processes typically include wafer fabrication, wafer testing, packaging, and product testing. The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, and a plurality of chips (die) are provided on the wafer. Wafer testing refers to testing functions, current, voltage and the like of chips on a wafer, and after the testing is finished, a wafer map file is generated. The wafer map file includes the position information and test result of the tested chip on the wafer. The test result may be a classification attribute value or the like, and the classification attribute value is used to indicate whether the tested chip meets the product specification or does not meet the classification of the product specification. For example, the classification attribute value may be represented by BIN, such as BIN1 representing a pass chip, BIN2 representing a fail chip, BIN3 representing a leakage current fail chip, and so on.

In the related art, wafer testing can be realized by using a probe station and testing equipment. First, a wafer to be tested is placed on a probe station. And then, the probe station determines information such as the position of the chip to be tested on the wafer and sends the information to the testing equipment. And the testing equipment tests the chips to be tested on the wafer according to the received information, generates a corresponding test result and sends the test result to the probe station. And after receiving the test result, the probe station generates a wafer map file according to the information such as the position of the chip to be tested, the test result and the like, and finishes the wafer test.

However, since no universal standard for wafer map files is specified internationally, when wafer tests are performed using different types of probe stations in the related art, the different types of probe stations generate wafer map files with different file rules, which results in differences in the file rules of the wafer map files generated by the different types of probe stations, and the file rules include one or more of file formats, file contents, and naming rules, which is not favorable for production control and data statistics, analysis, and processing.

Disclosure of Invention

The application provides a method, a device, equipment and a storage medium for generating a wafer map file, which can solve the problems that in the related art, file rules of the wafer map file generated by different types of probe stations are different, and production control and data statistics, analysis and processing are not facilitated.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, a method for generating a wafer map file is provided, where the method is applied to a relay device, and the relay device is respectively connected to a probe station and a test device, and the method includes:

receiving a first test instruction sent by the probe station, wherein the first test instruction comprises position information of a first chip to be tested on a wafer;

sending a second test instruction to the test equipment according to the first test instruction, wherein the second test instruction is used for indicating the test equipment to test the first chip;

receiving a first test response instruction sent by the test equipment, wherein the first test response instruction comprises a test result of the first chip;

and generating a wafer map file with preset file rules according to the first test instruction and the first test response instruction, wherein the wafer map file comprises the position information and the test result of the first chip.

In one embodiment, the instruction format of the first test instruction is a first instruction format supported by the probe station;

the sending a second test instruction to the test equipment according to the first test instruction comprises:

determining a second instruction format supported by the test equipment;

if the first instruction format is the same as the second instruction format, the first test instruction is used as the second test instruction and sent to the test equipment;

if the first instruction format is different from the second instruction format, converting the first test instruction into a second test instruction in the second instruction format, and sending the second test instruction serving as the second test instruction to the test equipment.

In an embodiment, the generating a wafer map file with a preset file rule according to the first test instruction and the first test response instruction includes:

if the wafer map file with the preset file rule is not created currently, creating the wafer map file with the preset file rule; extracting first information from the first test instruction and second information from the first test response instruction, wherein the first information comprises position information of the first chip, and the second information comprises a test result of the first chip; adding the first information and the second information to the wafer map file according to the preset file rule;

if the wafer map file with the preset file rule is created currently, extracting first information from the first test instruction, and extracting second information from the first test response instruction; and adding the first information and the second information into the wafer map file according to the preset file rule.

In one embodiment, after receiving the first test response instruction sent by the test device, the method further includes:

generating a second test response instruction, wherein the second test response instruction is used for indicating that the first chip test is completed;

and sending the second test response instruction to the probe station.

In one embodiment, the probe station supports a first instruction format, and the instruction format of the first test response instruction is a second instruction format supported by the test equipment;

the generating of the second test response instruction includes:

if the first instruction format is the same as the second instruction format, determining the first test response instruction as the second test response instruction;

and if the first instruction format is different from the second instruction format, converting the first test response instruction into a second test response instruction in the first instruction format.

In one embodiment, the relay device and the probe station communicate by using a first communication protocol; the transfer equipment and the test equipment are communicated by adopting a second communication protocol; wherein the first communication protocol is the same as or different from the second communication protocol.

In one embodiment, after receiving the first test instruction sent by the probe station, the method further includes:

determining the initial test time of the first chip according to the first test instruction, wherein the initial test time is the receiving time of the first test instruction or the first time included by the first test instruction;

after receiving the first test response instruction sent by the test equipment, the method further includes:

determining the cutoff test time of the first chip according to the first test response instruction, wherein the cutoff test time is the receiving time of the first test response instruction or the second time included by the first test response instruction;

the generating a wafer map file with preset file rules according to the first test instruction and the first test response instruction includes:

and generating the wafer map file with the preset file rule according to the first test instruction, the first test response instruction, and the initial test time and the ending test time of the first chip.

In a second aspect, an apparatus for generating a wafer map file is provided, the apparatus comprising:

the first receiving module is used for receiving a first test instruction sent by the probe station, wherein the first test instruction comprises position information of a first chip to be tested on a wafer;

a first sending module, configured to send a second test instruction to the test device according to the first test instruction, where the second test instruction is used to instruct the test device to test the first chip;

a second receiving module, configured to receive a first test response instruction sent by the test device, where the first test response instruction includes a test result of the first chip;

and the first generating module is used for generating a wafer map file with preset file rules according to the first test instruction and the first test response instruction, wherein the wafer map file comprises the position information and the test result of the first chip.

In one embodiment, the instruction format of the first test instruction is a first instruction format supported by the probe station, and the first sending module is configured to:

determining a second instruction format supported by the test equipment;

In one embodiment, the first generating module is configured to:

In one embodiment, the apparatus further comprises:

a second generating module, configured to generate a second test response instruction, where the second test response instruction is used to indicate that the first chip test is completed;

and the second sending module is used for sending the second test response instruction to the probe station.

In one embodiment, the probe station supports a first instruction format, the instruction format of the first test response instruction is a second instruction format supported by the test equipment, and the second generation module is configured to:

In one embodiment, the apparatus further comprises:

a first determining module, configured to determine, according to the first test instruction, an initial test time of the first chip, where the initial test time is a reception time of the first test instruction or a first time included in the first test instruction;

a second determining module, configured to determine an expiration test time of the first chip according to the first test response instruction, where the expiration test time is a receiving time of the first test response instruction or a second time included in the first test response instruction;

the first generation module is used for generating the wafer map file with the preset file rule according to the first test instruction, the first test response instruction, and the initial test time and the ending test time of the first chip.

In a third aspect, a computer device is provided, which includes an interface, a memory, a processor, and a wafer map file generation method program stored in the memory and executable on the processor, where one interface is used to connect a probe station, and one interface is used to connect a test apparatus, and when the processor executes the wafer map file generation method, the steps of any one of the wafer map file generation methods are implemented.

In a fourth aspect, a computer-readable storage medium is provided, where a wafer map file generation method program is stored on the computer-readable storage medium, and when the wafer map file generation method program is executed by a processor, the steps of any one of the above wafer map file generation methods are implemented.

The technical scheme provided by the embodiment of the application has the following beneficial effects:

in the embodiment of the application, the transfer equipment is additionally arranged between the probe station and the test equipment, and the transfer equipment is respectively connected with the probe station and the test equipment and can respectively communicate with the probe station and the test equipment. The transfer equipment can receive a first test instruction which is sent by the probe station and comprises position information of a first chip to be tested on the wafer, then sends a second test instruction to the test equipment according to the first test instruction to indicate the test equipment to test the first chip, then can receive a first test response instruction which is sent by the test equipment and comprises a test result of the first chip, and generates a wafer map file with preset file rules according to the first test instruction and the first test response instruction. Because the transfer equipment self-defines a preset file rule, no matter what type of probe station is used for wafer test, the transfer equipment can generate a wafer drawing file with uniform file rules, and production control and data statistics, analysis and processing are facilitated.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a system diagram illustrating a wafer map file generating method according to an embodiment of the present disclosure;

fig. 2 is a flowchart of a method for generating a wafer map file according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating a wafer testing method according to an embodiment of the present disclosure;

fig. 4 is a wafer map file generating apparatus according to an embodiment of the present application;

fig. 5 is a block diagram of a computer device according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Fig. 1 shows a schematic system diagram of a wafer map file generating method provided by the present application, where the system includes a probe station 10, a testing apparatus 20, and a transfer apparatus 30. The relay device 30 is connected to the probe station 10 and the test device 20 through a wired network or a wireless network, and is capable of communicating with the probe station 10 and the test device 20, respectively.

The probe station 10 is configured to fix a wafer to be tested, traverse all chips to be tested on the wafer, and generate position information of the traversed chips.

The testing device 20 is configured to test a chip to be tested according to position information of the chip to be tested on the wafer, and generate a test result. For example, the test apparatus 20 may apply, through programming, an excitation signal to a chip to be tested on the wafer by using the peripheral test circuit, and simultaneously sample an output of the chip under specific excitation, and compare the output with a preset standard to generate a test result of the chip traversed by the probe station 10.

The relay device 30 may receive information sent by the probe station, receive information sent by the testing device, and generate a wafer map file with preset file rules according to the received information. For example, the relay device may receive a first test instruction including position information of a first chip to be tested on the wafer, which is sent by the probe station, send a second test instruction to the test device according to the first test instruction to instruct the test device to test the first chip, receive a first test response instruction including a test result of the first chip, which is sent by the test device, and generate a wafer map file with a preset file rule according to the first test instruction and the first test response instruction.

As an example, the relay device 30 may be a device with dual interfaces, one interface is connected to the probe station 10, the other interface is connected to the testing device 20, and the connection manner of the interfaces may be a wired network connection or a wireless network connection.

As an example, the relay device 30 communicates with the probe station 10 using a first communication protocol, and the test device 20 communicates with the relay device 30 using a second communication protocol, which may be the same or different.

For example, the first communication protocol may be RS232(Recommended Standard 232) communication protocol or GPIB (General Purpose Interface Bus) communication protocol, and the second communication protocol may also be RS232 or GPIB, which is not limited in this embodiment of the present invention.

As an example, the probe station 10 supports a first instruction format and the test equipment 20 supports a second instruction format, which may be the same or different.

For example, the first and second instruction formats may be "TSX x Y" or "STARTXPOS, YPOS". Where ts (test START) and START denote the START of the test, "X × Y" and "XPOS", YPOS "denotes the coordinates of the chip to be tested. "TSX x Y" or "startpos YPOS" is used to indicate that the chips at the corresponding coordinates are tested.

Alternatively, the first instruction format and the second instruction may be "TC" or "BIN, EOT". Wherein, tc (test complete) and eot (end of test) indicate that the chip test is completed, and "") and "BIN" indicate the classification attribute values of the test results of the chips. "TC" or "BIN, EOT" is used to indicate that the test result for the chip is a classification attribute value, and different classification attribute values indicate different test results, for example, "1" indicates a qualified chip, "2" indicates a functional failure chip, "3" indicates a leakage current failure chip, and so on.

Of course, the first instruction format and the second instruction format may also be other instruction formats, which is not limited in this embodiment of the present application.

The transfer device 30 defines a preset file rule, where the preset file rule includes at least one of a file format, a file content, and a naming rule. For example, the preset file rules include file format, file content and naming rules.

Before the relay device 30 is added, in the related art, wafer testing can be performed by using the probe station 10 and the testing device 20, since there is a difference in file rules of wafer map files generated by using different types of probe stations 10, the file rules include one or more of file formats, file contents, and naming rules, which is not favorable for production control and data statistics, analysis, and processing.

In the embodiment of the present application, the transit device 30 defines a wafer map file with a preset file rule by itself, so that no matter what type of probe station 10 the transit device performs a wafer test, the transit device 30 can generate the wafer map file with a uniform file format, file content and naming rules according to the preset file rule, thereby avoiding the difference in the file rules of the wafer map files generated by different types of probe stations 10, and facilitating production control and data statistics, analysis and processing.

As an example, the file format of the preset file rule may be any one of binary, txt, or Execl file formats, the file content of the preset file rule may include location information and a test result of a chip to be tested on a wafer, the layout of the file content of the preset file rule may be in any simple and easy-to-see manner, and the naming rule of the preset file rule may be an initial test time — an end test time, and of course, the file format, the file content, and the naming rule of the preset file rule may also be other, which is not limited in this application example.

A method for generating a wafer map file according to an embodiment of the present application will be described in detail with reference to the accompanying drawings. Please refer to fig. 2, which is a flowchart illustrating a wafer map file generating method according to an embodiment of the present application, the method is applied to the system shown in fig. 1, and the method includes the following steps:

step 201, a probe station generates a first test instruction, where the first test instruction includes position information of a first chip.

The probe station fixes a wafer to be tested, detects a first chip to be tested on the wafer, determines position information of the first chip, and generates a first test instruction of the first chip, wherein the first test instruction comprises the position information of the first chip detected by the probe station.

As an example, the instruction format of the first test instruction is a first instruction format supported by the probe station.

For example, the first test command may be "TSX 5Y 8" or "startpos 5, YPOS 8" for indicating that the first chip with the abscissa of 5 and the ordinate of 8 is to be tested. Wherein "X5Y 8" or "XPOS 5, YPOS 8" represents position information of the first chip. Of course, the first instruction format of the first test instruction may be other instruction formats, which is not limited in this embodiment of the application.

As one example, the first test instruction may further include one or more of a size of the first chip, a first time, a total number of chips tested, and a first test status value.

The first time is used to indicate a start test time of the first chip, for example, the test time of the first chip may be used as the start test time of the first chip. The total number of chips tested is used to indicate the number of chips tested on the wafer. The first test state value is used for indicating whether all the chips on the wafer are tested. For example, the first test status value may be a first status value or a second status value, where the first status value is used to indicate that the chips on the wafer are not completely tested, and the second status value is used to indicate that the chips on the wafer are completely tested.

In addition, if the probe station detects that all the chips on the wafer are tested, the position information of the first chip included in the first test instruction generated by the probe station is invalid position information, and the first test state value is the second state value. For example, the invalid location information may use the coordinates "X! Y! "or" XPOS! YPOS! "means.

As one example, the first test instruction may further include one or more of a wafer identification, a total number of tests, an operator identification, and a probe station identification detected by the probe station.

The wafer identifier is used for uniquely identifying the wafer, and may include one or more of a wafer lot number, a wafer sheet number, a wafer model number, and a wafer size. The total number of tests is the number of all chips to be tested on the wafer. The operator ID is used to uniquely identify the wafer, for example, the operator representation may be an operator name or an operator ID (Identity document). The probe station identification is used for uniquely identifying the probe station, for example, the probe station identification may include one or both of a probe station model number and a probe station number.

In step 202, the probe station sends a first test instruction to the relay device.

For example, the probe station sends the first test instruction to the relay device through a wired network or a wireless network by using a first communication protocol. In addition, the instruction format of the first test instruction may be the first instruction format supported by the probe station, that is, the instruction format of the instruction transmitted between the relay device and the probe station is the first instruction format.

In step 203, the relay device receives a first test instruction sent by the probe station.

As an example, after receiving the first test instruction sent by the probe station, the relay device may further determine an initial test time of the first chip according to the first test instruction.

The starting test time may be a receiving time of the first test instruction or a first time in the first test instruction. That is, after receiving the first test instruction sent by the probe station, the relay device may determine the receiving time of the first test instruction, and use the receiving time of the first test instruction as the initial test time of the first chip. Alternatively, the first test instruction includes a first time, and the transfer device may use the first time in the first test instruction as the start test time.

And step 204, the transfer equipment sends a second test instruction to the test equipment according to the first test instruction.

And the second test instruction is generated according to the first test instruction, and the second test instruction is used for instructing the test equipment to test the first chip.

As an example, the relay device may send the second test instruction to the test device via a wired network or a wireless network using the second communication protocol. In addition, the test device supports a second instruction format, that is, the instruction format of the instruction transmitted between the transfer device and the test device is the second instruction format. Accordingly, the instruction format of the second test instruction is the second instruction format.

The second communication protocol used between the transfer device and the test device may be set by the test device by default, or may be set by the user as needed, which is not limited in the embodiments of the present application.

As an example, the transfer device may generate a second test instruction according to the first test instruction, and then send the second test instruction to the test device.

As an example, the first test instruction is a first instruction format supported by the probe station, and in order to enable an instruction format of a second test instruction generated according to the first test instruction to be recognized by the transfer device, the operation of the transfer device sending the second test instruction to the test device according to the first test instruction may include the following steps:

step 2041, determine the second instruction format supported by the test equipment.

The second instruction format supported by the test device may be set by the test device by default, or may be set by the user as needed, which is not limited in the embodiment of the present application.

Step 2042, if the first instruction format is the same as the second instruction format, the first test instruction is sent to the test equipment as the second test instruction.

As another example, the transfer device may further extract the position information of the first chip from the first test instruction, use an instruction corresponding to the position information of the first chip as a second test instruction, and send the second test instruction to the test device, where the second test instruction includes the position information of the first chip.

Step 2043, if the first instruction format is different from the second instruction format, converting the first test instruction into a second test instruction in the second instruction format, and sending the second test instruction to the test equipment.

As another example, the transfer device may also extract the location information of the first chip from the first test instruction, where the instruction format of the location information of the first chip is the first instruction format, perform instruction format conversion on the instruction format of the location information of the first chip, convert the instruction format into the location information of the first chip in the second instruction format, use the location information of the first chip in the second instruction format as the second test instruction, and send the second test instruction to the test device, where the second test instruction includes the location information of the first chip in the second instruction format.

As an example, if the first test instruction further includes a first test state value, the transfer device may further detect the first test state value in the first test instruction before sending the second test instruction to the test device according to the first test instruction. If the first test state value is the first state value, it indicates that all the chips on the wafer have not been tested, and in this case, the transfer device generates a second test instruction according to the first test instruction to instruct the test device to test the first chip.

In addition, if the first test state value is the second state value, it indicates that all the chips on the wafer have been tested, and in this case, the transfer device generates the second test instruction according to the first test instruction to instruct the test device to stop testing or to turn off the device.

The transit device may extract the second state value of the first test state value from the first test instruction, and the method for generating the second test instruction according to the extracted second state value may refer to steps 2041-2043, which are not described herein again.

As an example, the relay device may directly generate the second test instruction in the second instruction format. For example, the second Test command includes a first signal for instructing the testing equipment to stop the Wafer Test, and the first signal may be denoted as EOWT (End of Wafer Test).

As an example, the second communication protocol adopted between the relay device and the testing device and the second instruction format supported by the testing device are set by the testing device by default.

Wherein, before the transfer equipment is not added, the wafer test can be carried out by utilizing the probe station and the test equipment. Since the communication protocols adopted by the different types of probe stations may be different, even if the different types of probe stations based on the same communication protocol are different, the supported instruction formats may be different, so that the test equipment sets the communication protocol and the instruction system corresponding to the probe stations before the wafer test is started. When wafer testing is performed with different types of probe stations, the testing equipment needs to frequently set a communication protocol and an instruction system, so that the wafer testing process is complicated.

In the embodiment of the application, the transfer equipment performs the instruction format conversion on the first instruction format and the second instruction format, so that when the probe stations of different types are used for wafer testing, the transfer equipment can realize the communication transfer function between the probe stations and the test equipment, and therefore the test equipment does not need to frequently set a communication protocol and an instruction system, and the wafer testing process is simpler.

In step 205, the test device receives a second test instruction sent by the transit device.

And step 206, the test equipment generates a first test response instruction according to the second test instruction, wherein the first test response instruction comprises a test result of the first chip.

As an example, the instruction format of the first test response instruction may be a second instruction format supported by the test device.

As one example, the test result may be a classification attribute value (BIN) that indicates whether the chip under test meets or fails a classification of the product specification.

The first test response command may be denoted as "TC 1" or "BIN 1, EOT", indicating that the classification attribute value of the test result of the first chip is a pass chip. Wherein "1" represents a qualified chip. Of course, the second instruction format of the first test response instruction may be other instruction formats, which is not limited in this embodiment of the application.

As one example, the first test response instruction further includes a second time, a transit device identification, and a second test status value.

And the second time is used for representing the test ending time of the probe platform to the first chip to be tested on the wafer. The transit device identifier is used for uniquely representing the transit device, and may include one or two of a transit device model and a transit device number. The second test state value is used for indicating whether the test equipment stops the wafer test. For example, the second test state value may be a third state value or a fourth state value, where the third state value is used to indicate that the test equipment has not stopped the wafer test, and the fourth wafer test state value is used to indicate that the test equipment has stopped the wafer test.

In addition, before the test equipment generates the first test response instruction, if the test equipment detects that the second test instruction further includes a second state value indicating that the second test instruction instructs the test equipment to stop testing or to close the test equipment, the test equipment performs the operation of stopping the wafer test or closing the test equipment, and generates the first test response instruction. The first test response instruction includes a second test state value in addition to the test result of the first chip. Wherein the test result of the first chip is an invalid test result, such as "TC! "or" BIN! EOT "indicates that the second test state value is the fourth state value.

Step 207, the test equipment sends a first test response instruction to the transfer equipment.

And step 208, the transfer device receives the first test response instruction sent by the test device.

As an example, after receiving the first test response instruction sent by the probe station, the relay device may further determine a test expiration time of the first chip according to the first test response instruction.

The cutoff test time is the receiving time of the first test response instruction or the second time in the first test response instruction. That is, the transfer device may determine the receiving time of the first test response instruction after receiving the first test response instruction sent by the test device, and take the receiving time of the first test response instruction as the expiration test time. Alternatively, the first test response instruction may include the second time, and the transfer device may use the second time in the first test response instruction as the expiration test time.

Step 209, the transfer device generates a wafer map file with a preset file rule according to the first test instruction and the first test response instruction, where the wafer map file includes the location information of the first chip and the test result.

The preset file rule comprises at least one of a file format, file content and a naming rule. The preset file rule is a file rule self-defined by the transfer device, and the transfer device can generate a wafer map file with a unified file rule according to the preset file rule, for example, a wafer map file with a unified file format, file content and naming rule can be generated.

As an example, when generating the wafer map file, the transit device may first detect whether the wafer map file with the preset file rule is created, and the operation of generating the wafer map file by the transit device is different for different situations. For example, the operation of generating the wafer map file with the preset file rule according to the first test instruction and the first test response instruction may include the following two implementation manners:

the first implementation mode comprises the following steps: if the wafer map file with the preset file rule is not created currently, the wafer map file with the preset file rule is created; extracting first information from the first test instruction and extracting second information from the first test response instruction, wherein the first information comprises position information of the first chip, and the second information comprises a test result of the first chip; and adding the first information and the second information into the wafer map file according to a preset file rule.

For example, when creating a wafer map file with a preset file rule, the transfer device may create the wafer map file according to a file format and a naming rule specified in the preset file rule. Then, first information is extracted from the first test instruction according to file contents specified in a preset file rule, and second information is extracted from the first test response instruction. And finally, generating the wafer map file according to the typesetting of the file contents of the preset file rule.

As one example, the first information may include one or more of a size of the first chip, a first time, a total number of chips tested, a first test status value, a wafer identification, a total number of tests, an operator identification, and a prober identification, in addition to the location information of the first chip. The second information may include one or more of a second time, a transfer apparatus identification, and a second test status value, in addition to the test result of the first chip.

The second implementation mode comprises the following steps: if the wafer map file with the preset file rule is created currently, first information is directly extracted from the first test instruction, and second information is extracted from the first test response instruction. And then, adding the first information and the second information into the wafer map file according to a preset file rule.

As an example, if the first test response command includes the second test state value, the transfer device may detect the second test state value in the first test response command after receiving the first test response command. If the second test state value is the fourth state value, it indicates that the wafer test is completed, and the test equipment has stopped the wafer test, in this case, the transfer equipment may further execute step 309 to store a wafer map file with a preset file rule, where the wafer map file includes location information and test results of all test chips on the wafer. Thereafter, the following steps 311 and 312 may be performed to complete the wafer test.

As an example, the transit device may further be connected to a server, and after saving the wafer map file, the transit device may further upload the wafer map file to the server, so as to further facilitate production control and data statistics, analysis, and processing.

And step 210, the transfer equipment generates a second test response instruction and sends the second test response instruction to the probe station.

And the second test response instruction is generated according to the first test response instruction, and the second test response instruction is used for indicating that the test of the first chip is completed. In addition, the second test response instruction further includes a test result of the first chip.

As an example, the relay device may send the second test instruction to the probe station via a wired network or a wireless network using the first communication protocol. In addition, the probe station supports a first instruction format, and correspondingly, the instruction format of the second test response instruction is a second instruction format.

As an example, the relay device may generate a second test response instruction according to the first test response instruction, and then send the second test response instruction to the probe station.

As an example, the first test response instruction is in a second instruction format supported by the test equipment, and in order to enable an instruction format of the second test response instruction generated according to the first test response instruction to be recognized by the probe station, the operation of the relay equipment sending the second test response instruction to the probe station according to the first test response instruction may include the following steps:

in step 2101, the first test response command is determined to be the second test response command if the first command format is the same as the second command format.

As another example, the transfer device may further extract the test result of the first chip from the first test response instruction, use the test result of the first chip as a second test response instruction, and send the second test response instruction to the test device, where the second test response instruction includes the test result of the first chip.

As another example, the relay device may also extract the third information from the first test response instruction, which is not limited in this embodiment of the application, as long as the third information may indicate that the test of the first chip is completed, the relay device may generate a second test response instruction according to the third information, where the second test response instruction is used to indicate that the test of the first chip is completed.

At step 2102, if the first instruction format is different from the second instruction format, the first test response instruction is converted into a second test response instruction in the first instruction format.

As an example, the transfer device may extract a test result of the first chip from the first test response instruction, where a format of the test result instruction of the first chip is a second instruction format, perform instruction format conversion on the instruction format of the test result of the first chip, convert the instruction format into the test result of the first chip in the first instruction format, use the test result of the first chip in the first instruction format as a second test response instruction, and send the second test response instruction to the test device, where the second test response instruction includes the test result of the first chip in the first instruction format.

As an example, if the first test response instruction further includes a second test state value, the relay device may further detect the second test state value in the first test response instruction before sending the second test response instruction to the probe station according to the first test response instruction. And if the second test state value is the third state value, the test equipment does not stop the wafer test, and under the condition, the transfer equipment generates a second test response instruction according to the first test instruction to indicate that the first chip test is finished. And then, the probe station receives a second test response instruction sent by the transfer equipment, detects a second chip to be tested on the wafer according to the second test response instruction, and generates a first test instruction of the second chip, wherein the first test instruction comprises position information of the second chip to be tested on the wafer. Then, the transfer device executes the process shown in fig. 2, and continuously generates the wafer map file until the probe station detects that all the chips on the wafer have been tested.

In addition, if the second test state value is the fourth state value, it indicates that the test equipment has stopped the wafer test, and in this case, the relay equipment generates a second test response instruction according to the first test instruction to instruct the prober to stop the test or to turn off the equipment. Thereafter, the following steps 311 and 312 may be performed to complete the wafer test.

The method for the transit device to extract the fourth state value of the second test state value from the first test response instruction and generate the second test response instruction according to the extracted fourth state value refers to step 2101 and 2102, which are not described herein again.

As one example, the relay device may generate the second test response instruction in the first instruction format. For example, the second test response command may be a second signal or a third signal, the second signal is used for instructing the probe station to detect a second chip to be tested on the wafer, and the third signal is used for instructing the probe station to stop the wafer test.

As an example, if the first test instruction further includes the total number of tests and the total number of tested chips, the transfer device may further detect the total number of tests and the total number of tested chips in the first test instruction. If the total number of the tests is inconsistent with the total number of the tested chips, the test of all the chips on the wafer is not completed, in this case, the transfer equipment generates a second test response instruction, and the second test response instruction is used for indicating the probe station to detect the second chip to be tested on the wafer.

In addition, if the total number of tests is consistent with the total number of tested chips, it indicates that all the chips on the wafer are tested, in this case, the relay device generates a second test response instruction, and the second test response instruction is used for instructing the probe station to stop testing or turn off the device.

It should be noted that step 210 is an optional step. In addition, step 210 may be executed after step 209, before step 209, or in synchronization with step 209, and the execution order of step 209 and step 210 is not limited in this embodiment of the application.

It should be noted that, after the probe station receives the second test response instruction sent by the relay device, and determines that the first chip test is completed according to the second test response instruction, if the probe station detects that all the chips on the wafer are tested, the probe station may further instruct the system to stop testing, and then a process of stopping the wafer test by the system is described in detail.

Please refer to fig. 3, which is a flowchart illustrating a wafer testing method according to an embodiment of the present application, the method being applied to the system shown in fig. 1, and the method including the following steps:

step 301, if the probe station detects that all the chips on the wafer have been tested, a first test instruction is generated, where the first test instruction includes position information of the first chip and a first test state value, the position information of the first chip is invalid position information, and the first test state value is a second state value.

Step 302, the probe station sends a first test instruction to the relay device.

Step 303, the relay device receives a first test instruction sent by the probe station.

Step 304, the transfer device sends a second test instruction to the test device according to the first test instruction, where the second test instruction includes the location information of the first chip and the second state value.

When the transfer equipment detects that the first test state value in the first test instruction is the second state value and indicates that all the chips on the wafer are tested, the transfer equipment generates a second test instruction according to the first test instruction, and the second test instruction is used for indicating the test equipment to stop testing or close the equipment.

In step 305, the test device receives a second test instruction sent by the relay device.

Step 306, the test equipment stops the wafer test or closes the equipment operation according to the second test instruction, and generates a first test response instruction, where the first test response instruction includes a test result of the first chip and a second test state value, the test result of the first chip is an invalid test result, and the second test state value is a fourth state value.

And when the test equipment detects that the second test instruction further comprises a second state value, which indicates that the second test instruction is used for indicating the test equipment to stop testing or close the equipment, the test equipment stops wafer testing or closes equipment operation, and generates a first test response instruction.

Step 307, the test device sends a first test response instruction to the transfer device.

Step 308, the transfer device receives the first test response instruction sent by the test device.

Step 309, the transfer device saves a wafer map file with preset file rules according to the first test response instruction, wherein the wafer map file includes position information and test results of all test chips on the wafer.

And step 310, the transit device generates a second test response instruction, and sends the second test response instruction to the probe station, where the second test response instruction includes a fourth state value for instructing the probe station to stop testing or to turn off the device.

When the transfer device detects that the second test state value in the first test response instruction is the fourth state value and indicates that the test device stops wafer testing, the transfer device is used for indicating the probe station to stop wafer testing or close the device according to the second test response instruction generated by the first test instruction.

And 311, the probe station receives a second test response instruction sent by the relay equipment.

In step 312, the prober stops the wafer testing or shuts down the device operation according to the second test response command.

And if the probe station detects that the second test response command also comprises a fourth state value which indicates that the test equipment stops the wafer test, the probe station stops the wafer test or closes the equipment operation, and indicates that the wafer test is finished.

As an example, after the probe station stops the wafer test or shuts down the equipment operation, a third test response command may also be generated and sent to the relay equipment. Wherein the third test response instruction is used for indicating that the probe station stops testing. And then, the transfer equipment receives the third test response instruction, and can stop the system test or close the equipment operation according to the third test response instruction.

It should be noted that step 310 and step 312 are optional steps. In addition, the steps 310 and 312 may be executed after the step 309, before the step 309, or synchronously with the step 309, and the execution sequence of the steps 309 and 310 and 312 is not limited in the embodiment of the present application.

In this embodiment of the application, after the probe station receives the second test response instruction sent by the relay device, and after the first chip test is determined to be completed according to the second test response instruction, if the probe station detects that all the chips on the wafer are tested, a first test instruction including position information of the first chip and a first test status value is generated, in this case, the position information of the first chip is invalid position information, and the first test status value is a second status value, which is used to instruct the relay device and the test device to stop or close the device, and also can instruct the probe station to stop or close the device, so as to complete the wafer test.

At least some of the steps in fig. 2 and 3 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the other steps or stages.

As shown in fig. 4, fig. 4 is a wafer map file generating apparatus provided in this embodiment of the present application, the apparatus includes a first receiving module 401, a first sending module 402, a second receiving module 403, and a first generating module 404, where:

the first receiving module 401 is configured to receive a first test instruction sent by a probe station, where the first test instruction includes location information of a first chip to be tested on a wafer;

the first sending module 402 is configured to send a second test instruction to the test equipment according to the first test instruction, where the second test instruction is used to instruct the test equipment to test the first chip;

a second receiving module 403, configured to receive a first test response instruction sent by the test device, where the first test response instruction includes a test result of the first chip;

the first generating module 404 is configured to generate a wafer map file with a preset file rule according to the first test instruction and the first test response instruction, where the wafer map file includes location information of the first chip and a test result.

In an embodiment, the instruction format of the first test instruction is a first instruction format supported by the probe station, and the first sending module 402 is configured to:

determining a second instruction format supported by the test equipment;

if the first instruction format is the same as the second instruction format, the first test instruction is used as a second test instruction to be sent to the test equipment;

and if the first instruction format is different from the second instruction format, converting the first test instruction into a second test instruction in the second instruction format, and sending the second test instruction serving as the second test instruction to the test equipment.

In one embodiment, the first generation module 504 is configured to:

if the wafer map file with the preset file rule is not created currently, the wafer map file with the preset file rule is created; extracting first information from the first test instruction and extracting second information from the first test response instruction, wherein the first information comprises position information of the first chip, and the second information comprises a test result of the first chip; adding the first information and the second information into the wafer map file according to a preset file rule;

if the wafer map file with the preset file rule is created currently, extracting first information from the first test instruction and extracting second information from the first test response instruction; and adding the first information and the second information into the wafer map file according to a preset file rule.

In one embodiment, the apparatus further comprises:

the second generating module is used for generating a second test response instruction, and the second test response instruction is used for indicating that the test of the first chip is finished;

and the second sending module is used for sending a second test response instruction to the probe station.

In one embodiment, the probe station supports a first instruction format, the instruction format of the first test response instruction is a second instruction format supported by the test equipment, and the second generating module is configured to:

if the first instruction format is the same as the second instruction format, determining the first test response instruction as a second test response instruction;

In one embodiment, the apparatus further comprises:

the first determining module is used for determining the initial test time of the first chip according to the first test instruction, wherein the initial test time is the receiving time of the first test instruction or the first time included by the first test instruction;

the second determining module is used for determining the ending test time of the first chip according to the first test response instruction, wherein the ending test time is the receiving time of the first test response instruction or the second time included by the first test response instruction;

the first generating module 404 is configured to generate a wafer map file with preset file rules according to the first test instruction, the first test response instruction, and the start test time and the end test time of the first chip.

For the specific limitations of the wafer map file generation apparatus, reference may be made to the above limitations of the wafer map file generation method, which are not described herein again. All or part of the modules in the wafer map file generation device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

Fig. 5 is a block diagram of a computer device 500 according to an embodiment of the present disclosure. The computer device may be the relay device in the embodiments of fig. 1, fig. 2 and fig. 3. The computer device 500 may be a tablet computer, a desktop computer, a server, or the like.

The computer device 500 includes: an interface 501, a processor 502, and a memory 503.

The interface 501 may be connected to peripheral devices by wire or wirelessly, wherein the peripheral devices may include a probe station and a test device, the interface 5011 is connected to the probe station 504, and the interface 5012 is connected to the test device 505. The interface 501, the processor 502 and the memory 503 may be connected by a bus or signal lines.

The processor 502 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so on. The processor 502 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 502 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 502 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that the display screen needs to display. In some embodiments, the processor 502 may further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

The memory 503 may include one or more computer-readable storage media, which may be non-transitory. The memory 503 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in the memory 503 is used to store at least one instruction for execution by the processor 502 to implement the wafer map file generation method and the wafer testing method described above. In some embodiments, the peripheral device may further comprise: a display 506 and a power supply 507. The interface 5013 is connected to the display 506, and the interface 5014 is connected to the power supply 507.

Those skilled in the art will appreciate that the configuration shown in FIG. 5 does not constitute a limitation of the computer device 500, and may include more or fewer components than those shown, or combine certain components, or employ a different arrangement of components.

In one embodiment, a computer-readable storage medium is further provided, which has instructions stored thereon, and when executed by a processor, implements the wafer map file generation method and the wafer test method described above.

In one embodiment, a computer program product is also provided for implementing the wafer map file generation method and the wafer test method described above when the computer program product is executed.

It should be understood that reference to "a plurality" herein means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A wafer map file generation method is applied to transfer equipment, wherein the transfer equipment is respectively connected with a probe station and test equipment, and the method comprises the following steps:

2. The method of claim 1, wherein the first test command has a first command format supported by the probe station;

determining a second instruction format supported by the test equipment;

3. The method of claim 1, wherein generating the wafer map file with preset file rules according to the first test command and the first test response command comprises:

4. The method of claim 1, wherein after receiving the first test response instruction sent by the test device, the method further comprises:

and sending the second test response instruction to the probe station.

5. The method of claim 4, wherein the probe station supports a first instruction format, and the instruction format of the first test response instruction is a second instruction format supported by the test equipment;

the generating of the second test response instruction includes:

6. The method according to any one of claims 1 to 5,

the transfer equipment and the probe station are communicated by adopting a first communication protocol;

the transfer equipment and the test equipment are communicated by adopting a second communication protocol;

wherein the first communication protocol is the same as or different from the second communication protocol.

7. The method according to any one of claims 1-5, wherein after receiving the first test instruction sent by the probe station, the method further comprises:

8. A wafer map file generating apparatus, characterized in that the apparatus comprises:

9. The apparatus of claim 8, wherein the first test command has a command format supported by the probe station, and wherein the first sending module is configured to:

determining a second instruction format supported by the test equipment;

10. The apparatus of claim 8, wherein the first generating module is configured to:

11. The apparatus of claim 8, further comprising:

12. The apparatus of claim 11, wherein the probe station supports a first instruction format, wherein the first test response instruction has a second instruction format supported by the test equipment, and wherein the second generation module is configured to:

13. The apparatus of any of claims 8-12, further comprising:

14. A computer device comprising an interface, a memory, a processor and a computer program stored in the memory and executable on the processor, the processor when executing the computer program performing the steps of the method of any of claims 1 to 7.

15. A computer-readable storage medium, having a program stored thereon, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.