CN113392552A - Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation - Google Patents

Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation Download PDF

Info

Publication number
CN113392552A
CN113392552A CN202110658355.XA CN202110658355A CN113392552A CN 113392552 A CN113392552 A CN 113392552A CN 202110658355 A CN202110658355 A CN 202110658355A CN 113392552 A CN113392552 A CN 113392552A
Authority
CN
China
Prior art keywords
switching device
parasitic inductance
width
switch device
finite element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110658355.XA
Other languages
Chinese (zh)
Other versions
CN113392552B (en
Inventor
宫金武
陈佳洛
林文强
陈思倩
潘尚智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan University WHU
Original Assignee
Wuhan University WHU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan University WHU filed Critical Wuhan University WHU
Priority to CN202110658355.XA priority Critical patent/CN113392552B/en
Publication of CN113392552A publication Critical patent/CN113392552A/en
Application granted granted Critical
Publication of CN113392552B publication Critical patent/CN113392552B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/06—Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及多器件大功率MOS管的并联均流问题，提出一种基于有限元仿真的多并联开关器件均流优化设计方法。所述多并联开关器件包括：驱动模块、第一个开关管器件、第二个开关管器件、...、第n个开关管器件。人工设定驱动模块与开关器件之间的走线的长度，根据第一个开关管器件、第二个开关管器件、...、第n个开关管器件之间结构对称原则，通过Altium Designer软件设计电路板；确定优化的目标寄生电感值；设定要求误差；结合目标寄生电感值计算初始化驱动模块与开关器件之间的走线的宽度，通过有限元仿真多次迭代优化驱动模块与开关器件之间的走线的宽度。本发明获取的仿真寄生参数准确性高，且有效减小了寄生参数；有效的减小并联不均流，提高系统稳定性。

Figure 202110658355

The invention relates to the problem of parallel current sharing of multi-device high-power MOS tubes, and proposes an optimal design method for current sharing of multi-parallel switching devices based on finite element simulation. The multi-parallel switch device includes: a driving module, a first switch device, a second switch device, . . . , and the nth switch device. Manually set the length of the traces between the drive module and the switch device, according to the principle of structural symmetry between the first switch device, the second switch device, ..., the nth switch device, through Altium Designer Software design circuit board; determine the optimized target parasitic inductance value; set the required error; combine the target parasitic inductance value to calculate the width of the trace between the initialization drive module and the switch device, and optimize the drive module and switch through multiple iterations of finite element simulation Width of traces between devices. The simulation parasitic parameters obtained by the invention have high accuracy, and effectively reduce the parasitic parameters; effectively reduce the uneven current in parallel connection, and improve the system stability.

Figure 202110658355

Description

Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation
Technical Field
The invention relates to the field of parallel current sharing design of multiple switch devices, in particular to a current sharing optimization design method of multiple parallel switch devices based on finite element simulation.
Background
In recent years, with the rapid development of power electronic technology, the requirement for power devices is higher and higher, and compared with the traditional Si MOSFET, the SiC MOSFET has many advantages of higher switching speed, lower on-state loss, higher blocking voltage and the like, and can improve the system efficiency, reduce the volume of equipment and further improve the power density of the equipment. However, due to the limitations of cost and the like under the current technological level and specific requirements, the current capacity of a single SiC MOSFET is limited, the requirements of high-power occasions cannot be met, a plurality of SiC MOSFETs often need to be used in parallel, and the scheme of parallel application is widely applied to the fields of motor control, inverters and the like. However, because parameters of the parallel devices in the loop are not consistent, currents of the branches are often unbalanced, the current imbalance causes non-negligible damage to the devices, mainly embodied in loss difference of the parallel devices, current and voltage stress difference of the devices and difference of switching speeds, and the difference causes a single device to be damaged when working under the working conditions of loss and excessive stress for a long time, so that damage is caused to other parallel devices and the whole system.
The current imbalance is mainly divided into static current imbalance and dynamic current imbalance, and main factors causing the dynamic current imbalance include device parameter imbalance, different parasitic inductance of a driving loop, influence of temperature characteristics and the like. The driving circuit plays a crucial role in dynamic current equalization of the parallel devices, and the grid driving resistance and the parasitic inductance in the driving circuit influence inconsistency of driving signals among the branches, so that the switching tube which is turned on first bears overcurrent, and the switching tube is possibly damaged. The conventional design scheme requires that the driving circuit and the main circuit of each switch tube are strictly symmetrically/equidistantly arranged, and in the layout of the multi-device parallel circuit board, firstly, the minimum impedance of the decoupling circuit of the main power circuit of the switch tube is ensured, and the parallel switch tubes are structurally symmetrical, so that the driving circuit of each parallel switch tube is difficult to structurally symmetrical on the basis of the symmetry of the main power circuit of the switch tube, and the design difficulty is brought to the parallel connection of multiple tubes. In order to solve the problem, the invention provides a current sharing optimization design method of a multi-parallel switch device based on finite element simulation.
Disclosure of Invention
In order to solve the problems of the background art, the invention provides a current sharing optimization design method of a multi-parallel switch device based on finite element simulation. Through finite element simulation analysis, parasitic inductance values of all driving loops are obtained, wiring layout is adjusted according to a parasitic inductance empirical expression, so that electrical characteristic symmetry (parasitic inductance equality) of all branches is realized under the condition of asymmetrical structure (unequal widths and lengths of driving wires), and dynamic current equalization of all parallel switching tubes is further realized.
The technical scheme of the invention is a current sharing optimization design method of a multi-parallel switch device based on finite element simulation.
The multiple parallel switching device includes: the driving module, a first switching device, a second switching device, an nth switching device;
the driving module is connected with the ith switching tube device through wiring, i belongs to [1, n ];
the plurality of switching device devices are connected in parallel;
the driving loop i is a loop formed by connecting a driving module and the ith switch tube through a lead;
parasitic inductance L of each driving loopiIs the value at the same frequency f;
the current sharing optimization design method of the multiple parallel switch devices based on finite element simulation comprises the following steps:
step 1: manually setting the length of a wiring between a driving module and a switch device, and designing a circuit board through Altium Designer software according to the principle of structural symmetry between a first switch tube device, a second switch tube device, a structure.
Step 2: determining an optimized target parasitic inductance value;
and step 3: setting a required error;
and 4, step 4: calculating the width of a wire between the initialization driving module and the switch device by combining a target parasitic inductance value, and iteratively optimizing the width of the wire between the driving module and the switch device for multiple times through finite element simulation by combining the width of the wire between the initialization driving module and the switch device;
preferably, in step 1, the length of the trace between the driving module and the switching device is:
the length of the wire between the driving module and the ith switch device is defined as:
li,i∈[1,n]and li∈[lmin,lmax]
Wherein lminFor the shortest distance of the driving loopmaxRouting a longest distance for a driving loop;
preferably, the step 2 specifically comprises:
the constraint conditions of the wiring width between the driving module and each switch device are as follows:
Wi∈[wmin,wmax]
wherein, wminIs the minimum value of the track width, wmaxIs the maximum trace width.
The length of the wire between the driving module and the nth switch device is lmaxSetting the width of the loop as wmaxThe designed circuit board is led into Ansys Q3D, excitation is added, and the line width of the longest driving loop is obtained by finite element simulation by taking parasitic inductance as a research objectmaxParasitic inductance value L of timeoIs prepared by mixing LoAs a target parasitic inductance value;
preferably, the required error in step 3 is defined as σL；
Preferably, in step 4, the calculating a width of a trace between the driving module and the switching device by combining the target parasitic inductance value and the length of the trace between the driving module and the switching device specifically includes:
Figure BDA0003114211460000031
i∈[1，n]
according to the implicit function expression, w can be obtained by means of Mathematica softwarei,0A numerical solution of (a), wherein liIs the length of the trace between the driving module and the ith switch device, LoIs a target parasitic inductance value, wi,0In order to initialize the width of a wire between the driving module and the ith switch device, n represents the number of the switch devices;
step 4.1, mixing wi,jAs the trace width between the driving module and the ith switch tube in the jth iteration, when j is 0, wi,j＝wi,0
Step 4.2, according to the width w of the wiringi,jAfter the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance L of the specific frequency f under the layout is obtained by utilizing finite element simulationi,j；
Step 4.3, if | Li,j-Lo|＜σlThen finishing the design of a driving loop i;
if Li,j-Lo|≥σlAnd L isi,j＜LOW is to bei,jAccording to a certain step length reduction, continuing to execute the step 4.2 until | Li,j-LO|＜σl；
If lLi,j-LO|≥σlAnd L isi,j≥LOW is to bei,jAccording to a certain step length increase, continuing to execute the step 4.2 until | Li,j-LO|＜σl。
Wherein L isi,jThe loop parasitic inductance value W of the driving module and the ith switching device obtained through simulation solution in the step 4.2 in the jth iterationi,jBetween the driving module and the ith switch tube for the jth iterationWidth of trace, LOIs a target parasitic inductance value, σlThe required error is obtained;
the simulation solution is as follows:
solving the numerical solution of the implicit function equation by using a dichotomy by using mathematical software mathematica;
the invention relates to a specific method for current sharing optimization design of a plurality of parallel switch devices based on finite element simulation, which comprises the following steps: under the condition of ensuring the symmetrical layout of the driving module and each switching tube device, the parasitic inductance can be reduced by reasonably adjusting the wiring length and the wiring width of the circuit board, so that the asymmetrical electrical characteristic symmetry of a plurality of driving loop structures can be realized, and the problem of parallel uneven current is reduced to a great extent.
Compared with the prior art, the invention has the following advantages:
the good current equalizing effect can be achieved without additional elements and control;
the simulation operation is simple and easy to realize, and is close to reality, and the accuracy is high;
finite element simulation can be carried out through mesh subdivision without establishing a complex model to obtain a parasitic inductance accurate solution;
drawings
FIG. 1: is a flow chart of the method of the present invention.
FIG. 2: is the most common half-bridge topology with three devices in parallel.
FIG. 3: the invention relates to a three-device parallel half-bridge circuit board layout.
Detailed Description
The invention is described in detail below with reference to the following drawings and specific embodiments:
FIG. 1 is a flow chart of the method of the present invention. The invention is explained by taking a half-bridge topology which is most commonly used by three-device parallel connection as an example, fig. 2 is the most commonly used half-bridge topology which is most commonly used by three-device parallel connection, wherein L is a parasitic inductance value and is a main factor causing parallel dynamic non-uniform current, fig. 3 is a circuit board layout diagram of the three-device parallel half-bridge, the upper and lower tubes are symmetrically driven, the three-tube driving is analyzed by taking the three-tube driving as an example, a lead T1 (upper-layer wire) and a lead B1 (lower-layer wire) are connected with a driving module and a switching tube Q1 to form a driving loop 1 which is a main optimized path, and the driving loop 2 and the. For the convenience of analysis, the voltage peak frequency of the half-bridge module is assumed to be 10MHz, and the parasitic inductance of each driving loop is measured by taking the value as a reference.
The specific implementation mode of the invention is a current sharing optimization design method of a multi-parallel switch device based on finite element simulation.
The multiple parallel switching device includes: the driving module, the first switching tube device, the second switching tube device and the third switching tube device;
the driving module is connected with the ith switching tube device through wiring, i belongs to [1,3 ];
the plurality of switching device devices are connected in parallel;
the driving loop i is a loop formed by connecting a driving module and the ith switch tube through a lead;
parasitic inductance L of each driving loopiIs the value at the same frequency of 10 MHz;
the model of the driving module is 1EDI20H12 AH;
the models of the first switching tube device, the second switching tube device and the third switching tube device are all IMZA65R027M 1H;
the current sharing optimization design method of the multiple parallel switch devices based on finite element simulation comprises the following steps
Step 1: according to the principle of structural symmetry among the first switch tube device, the second switch tube device and the third switch tube device, the wiring lengths among the driving module, the first switch device, the second switch device and the third switch device are set to be 30mm, 64mm and 106mm respectively, and the circuit board is designed through Altium Designer software;
step 2: determining an optimized target parasitic inductance value
The constraint conditions of the wiring width between the driving module and each switch device are as follows:
0.4mm≤Wi≤2mm
the longest length of the wire between the driving module and the third switch device is also lmax＝l3Setting the width of the circuit to be 2mm at 100mm, leading the designed circuit board into Ansys Q3D, adding excitation, and solving by taking parasitic inductance as a research object to obtain parasitic inductance Lo18.7nH, mixing Lo18.7nH as the target parasitic inductance value;
and step 3: set request error σL＝1nH；
And 4, step 4: calculating the width of a wire between the initialization driving module and the first switch device by combining a target parasitic inductance value, and iteratively optimizing the width of the wire between the driving module and the first switch device for multiple times through finite element simulation by combining the width of the wire between the initialization driving module and the first switch device;
and 4, calculating the width of the wiring between the driving module and the switch device by combining the target parasitic inductance value and the wiring length between the driving module and the switch device, specifically:
Figure BDA0003114211460000051
i∈[1，n]
the implicit function expression can be obtained by mathematical software Mathematica
Wi,0=0.46mm≈0.5mm
Wherein, W1,0Initializing the width of a wire between the driving module and the first switch device;
step 4.1, mixing W1，0As the width of the wire between the driving module and the 1 st switch tube at the 0 th iteration,
step 4.2, according to the width W of the wiring1，0After the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance value of the driving circuit 1 at 10MHz in the layout is obtained to be 17.57nH by utilizing finite element simulation;
step 4.3, judge | L1，0-LoI and sigmalThe magnitude relationship of (1) can be known
|L1.0-Lo|＝1.13nH＞1nH＝σlAnd L is1，0>Lo
Then W will be1，0The distance is reduced according to the step length of 0.1mm, namely the width of the drive circuit 1 during the second iteration is 0.4mm, namely W1，1＝0.4mm；
According to the width W of the wiring1，1After the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance value of the driving circuit 1 at 10MHz in the layout is obtained to be 18.30nH by utilizing finite element simulation;
determine | L1，1-LoI and sigmalThe magnitude relationship of (1) can be known
|L1，1-Lo|＝0.4nH＜1nH＝σl
Completing the design of the driving circuit 1;
and 5: only the driving loop 1 is optimized, the step 4 is continuously returned, and iterative optimization is carried out on the driving loop 2;
and 4, step 4: calculating the width of a wire between the initialization driving module and the second switch device by combining a target parasitic inductance value, and iteratively optimizing the width of the wire between the driving module and the second switch device for multiple times through finite element simulation by combining the width of the wire between the initialization driving module and the second switch device;
and 4, calculating the width of the wiring between the driving module and the switch device by combining the target parasitic inductance value and the wiring length between the driving module and the switch device, specifically:
Figure BDA0003114211460000061
i∈[1，n]
the implicit function expression can be obtained by mathematical software Mathematica
W2,0=0.95mm≈1mm
Wherein, W2,0Initializing the width of a wire between the driving module and the second switch device;
step 4.1, mixing W2,0As a firstThe wiring width between the driving module and the second switch tube is 0 time of iteration,
step 4.2, according to the width W of the wiring2,0After the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance value of the driving circuit 2 at 10MHz in the layout is obtained to be 19.67nH by utilizing finite element simulation;
step 4.3, judge | L2,0-LoI and sigmalThe magnitude relationship of (1) can be known
|L2,0-Lo|=0.97nH＜1nH=σl
The simulation solution is as follows:
solving the numerical solution of the implicit function equation by using a dichotomy by using mathematical software mathematica;
the design of the drive circuit 2 is completed.
By combining the analysis, the parasitic inductance values of the driving circuits 1, 2 and 3 designed and obtained by the method are respectively 18.30nH, 19.67nH and 18.7nH, the inductance value difference among the driving circuits is small, the design requirement is met, the electrical characteristic symmetry effect is good, the parallel non-uniform fluidity of the system can be reduced to a large extent, and the stability of the system is improved.
The above embodiments are only preferred embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields by using the contents of the present specification and the accompanying drawings are included in the scope of the present invention.

Claims (5)

1.一种基于有限元仿真的多并联开关器件均流优化设计方法，其特征在于，1. a multi-parallel switching device current sharing optimization design method based on finite element simulation, is characterized in that, 所述多并联开关器件包括：驱动模块、第一个开关管器件、第二个开关管器件、...、第n个开关管器件；The multi-parallel switch device includes: a drive module, a first switch device, a second switch device, ..., an nth switch device; 所述驱动模块与所述第i个开关管器件通过走线连接，i∈[1，n]；The drive module is connected to the i-th switch device through a wire, i∈[1,n]; 所述多个开关管器件并联连接；the plurality of switch devices are connected in parallel; 所述驱动回路i为驱动模块与第i个开关管通过导线连接形成的回路；The drive circuit i is a circuit formed by connecting the drive module and the i-th switch tube through a wire; 所述各个驱动回路寄生电感值Li为同一频率f下的值；The parasitic inductance value L i of each drive loop is the value under the same frequency f; 所述基于有限元仿真的多并联开关器件均流优化设计方法，包括以下步骤：The method for optimizing the current sharing of multiple parallel switching devices based on finite element simulation includes the following steps: 步骤1：人工设定驱动模块与开关器件之间的走线的长度，根据第一个开关管器件、第二个开关管器件、...、第n个开关管器件之间结构对称原则，通过Altium Designer软件设计电路板；Step 1: Manually set the length of the wiring between the driving module and the switching device, according to the principle of structural symmetry between the first switching device, the second switching device, ... and the nth switching device, Design circuit boards through Altium Designer software; 步骤2：确定优化的目标寄生电感值；Step 2: Determine the optimized target parasitic inductance value; 步骤3：设定要求误差；Step 3: Set the required error; 步骤4：结合目标寄生电感值计算初始化驱动模块与开关器件之间的走线的宽度，结合初始化驱动模块与开关器件之间的走线的宽度通过有限元仿真多次迭代优化驱动模块与开关器件之间的走线的宽度。Step 4: Calculate the width of the trace between the initialization drive module and the switching device in combination with the target parasitic inductance value, and optimize the drive module and the switching device through multiple iterations of finite element simulation in combination with the width of the trace between the initialization drive module and the switching device The width of the traces between. 2.根据权利要求1所述的基于有限元仿真的多并联开关器件均流优化设计方法，其特征在于，步骤1所述驱动模块与开关器件之间的走线的长度为：2. the multi-parallel switching device current sharing optimization design method based on finite element simulation according to claim 1, is characterized in that, the length of the wiring between the drive module and the switching device described in step 1 is: 驱动模块与第i开关器件之间的走线的长度，定义为：The length of the trace between the driver module and the i-th switching device is defined as: li，i∈∈[1，n]且li∈[lmin，lmax]l i , i∈∈[1,n] and l i ∈[l min , l max ] 其中，lmin为驱动回路走线最短距离，lmax为驱动回路走线最长距离。Among them, l min is the shortest distance of the driving circuit wiring, and l max is the longest distance of the driving circuit wiring. 3.根据权利要求1所述的基于有限元仿真的多并联开关器件均流优化设计方法，其特征在于，所述步骤2具体为：3. the multi-parallel switching device current sharing optimization design method based on finite element simulation according to claim 1, is characterized in that, described step 2 is specifically: 所述驱动模块与每个开关器件之间的走线宽度的约束条件为：The constraints on the width of the traces between the driving module and each switching device are: Wi∈[Wmin，Wmax]Wi ∈ [W min , W max ] 其中，Wmin为走线宽度最小值，Wmax为走线宽度最大值；Among them, W min is the minimum line width, and W max is the maximum line width; 驱动模块与第n个开关器件之间的走线长度为lmax，设置该回路的走线宽度为Wmax，将设计的电路板导入Ansys Q3D中，添加激励，以寄生电感为研究对象利用有限元仿真得出最长驱动回路线宽为Wmax时的寄生电感值Lo，将Lo作为目标寄生电感值。The length of the trace between the driver module and the nth switching device is l max , the trace width of the loop is set to W max , the designed circuit board is imported into Ansys Q3D, excitation is added, and the parasitic inductance is the research object with limited utilization The parasitic inductance value L o when the longest driving loop line width is W max is obtained by meta-simulation, and L o is taken as the target parasitic inductance value. 4.根据权利要求1所述的基于有限元仿真的多并联开关器件均流优化设计方法，其特征在于，步骤3所述要求误差定义为σL。4 . The method for optimizing the current sharing of multiple parallel switching devices based on finite element simulation according to claim 1 , wherein the required error in step 3 is defined as σ L . 5 . 5.根据权利要求1所述的基于有限元仿真的多并联开关器件均流优化设计方法，其特征在于，步骤4所述结合目标寄生电感值以及驱动模块与开关器件之间的走线长度，计算驱动模块与开关器件之间的走线宽度,具体为：5. The multi-parallel switching device current-sharing optimization design method based on finite element simulation according to claim 1, wherein the step 4 is combined with the target parasitic inductance value and the wiring length between the driving module and the switching device, Calculate the trace width between the driver module and the switching device, specifically:
Figure FDA0003114211450000021
Figure FDA0003114211450000021
 i∈[1，n]i∈[1,n] 根据该隐函数表达式可借助数学软件Mathematica求得Wi，0的数值解，其中，li为驱动模块与第i开关器件之间的走线的长度，Lo为目标寄生电感值,Wi，0为初始化驱动模块与第i开关器件之间的走线的宽度，n表示开关管器件的数量；According to the implicit function expression, the numerical solution of Wi , 0 can be obtained with the help of mathematical software Mathematica, where li is the length of the wiring between the drive module and the i -th switching device, L o is the target parasitic inductance value, W i, 0 is the width of the trace between the initialization drive module and the i-th switch device, and n represents the number of switch devices; 步骤4.1，将Wi，j作为第j次迭代时驱动模块与第i个开关管之间的走线宽度，当j＝0时，Wi，j＝Wi，0；Step 4.1, take Wi ,j as the line width between the drive module and the i-th switch tube during the j-th iteration, when j=0, Wi ,j =W i,0 ; 步骤4.2，按照走线宽度Wi，j调整步骤1设计的电路板后，导入Ansys Q3D中，添加激励，以寄生电感为研究对象，利用有限元仿真得出该布局下特定频率f的寄生电感值Li，j；Step 4.2, after adjusting the circuit board designed in step 1 according to the trace width Wi ,j , import it into Ansys Q3D, add excitation, take the parasitic inductance as the research object, and use the finite element simulation to obtain the parasitic inductance of the specific frequency f under the layout value L i,j ; 步骤4.3，若|Li，j-Lo|＜σl，则完成驱动回路i设计；Step 4.3, if |L i,j -L o |<σ l , complete the design of the drive circuit i; 若|Li，j-Lo|≥σl，且Li，j＜Lo，将Wi，j根据一定步长减小，继续执行步骤4.2，直至|Li，j-Lo|＜σl；If |L i,j -L o |≥σ l , and L i,j <L o , reduce Wi ,j according to a certain step size, and continue to perform step 4.2 until |L i,j -L o | <σ l ; 若|Li，j-Lo|≥σl，且Li，j≥Lo，将Wi，j根据一定步长增加，继续执行步骤4.2，直至|Li，j-Lo|＜σl；If |L i,j -L o |≥σ l , and Li, j ≥L o , increase Wi ,j according to a certain step size, and continue to perform step 4.2 until |L i,j -L o |< σ l ; 其中，Li，j为第j次迭代时通过步骤4.2仿真求解得到的驱动模块与第i个开关器件的回路寄生电感值，Wi，j为第j次迭代时驱动模块与第i个开关管之间的走线宽度，Lo为目标寄生电感值，σl为要求误差。Among them, Li,j is the loop parasitic inductance value of the driving module and the i-th switching device obtained by the simulation solution in step 4.2 at the j-th iteration, and Wi ,j is the driving module and the i-th switch at the j-th iteration. The trace width between the tubes, L o is the target parasitic inductance value, and σ l is the required error.
CN202110658355.XA 2021-06-15 2021-06-15 An optimal design method for current sharing of multi-parallel switching devices based on finite element simulation Active CN113392552B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110658355.XA CN113392552B (en) 2021-06-15 2021-06-15 An optimal design method for current sharing of multi-parallel switching devices based on finite element simulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110658355.XA CN113392552B (en) 2021-06-15 2021-06-15 An optimal design method for current sharing of multi-parallel switching devices based on finite element simulation

Publications (2)

Publication Number Publication Date
CN113392552A true CN113392552A (en) 2021-09-14
CN113392552B CN113392552B (en) 2022-04-15

Family

ID=77620895

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110658355.XA Active CN113392552B (en) 2021-06-15 2021-06-15 An optimal design method for current sharing of multi-parallel switching devices based on finite element simulation

Country Status (1)

Country Link
CN (1) CN113392552B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9881120B1 (en) * 2015-09-30 2018-01-30 Cadence Design Systems, Inc. Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness
CN112105138A (en) * 2020-08-25 2020-12-18 欣旺达电动汽车电池有限公司 Electronic component parallel current-sharing circuit, design method and PCB
CN112163355A (en) * 2020-09-24 2021-01-01 复旦大学 SiC MOSFET packaging structure optimization design method, medium and equipment
US20210133381A1 (en) * 2019-11-06 2021-05-06 Harbin Institute Of Technology Design method for paralleled sic power switching devices based on wiring optimization

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9881120B1 (en) * 2015-09-30 2018-01-30 Cadence Design Systems, Inc. Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness
US20210133381A1 (en) * 2019-11-06 2021-05-06 Harbin Institute Of Technology Design method for paralleled sic power switching devices based on wiring optimization
CN112105138A (en) * 2020-08-25 2020-12-18 欣旺达电动汽车电池有限公司 Electronic component parallel current-sharing circuit, design method and PCB
CN112163355A (en) * 2020-09-24 2021-01-01 复旦大学 SiC MOSFET packaging structure optimization design method, medium and equipment

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
孙康康等: "3300 V全SiC MOSFET功率器件开关特性研究", 《机车电传动》 *
柯俊吉等: "碳化硅MOSFET开关特性分析及杂散参数优化", 《华北电力大学学报(自然科学版)》 *
秦海鸿等: "寄生电感对SiC MOSFET开关特性的影响", 《南京航空航天大学学报》 *
邵伟华等: "基于优化对称布局的多芯片SiC模块动态均流", 《中国电机工程学报》 *

Also Published As

Publication number Publication date
CN113392552B (en) 2022-04-15

Similar Documents

Publication Publication Date Title
Pavlidis et al. 3-D topologies for networks-on-chip
CN105956289B (en) Power distribution network design method based on decoupling capacitor decoupling region
CN104732006A (en) IGBT module steady state temperature calculating method
CN113435090B (en) An electric-thermal-fluid multi-field coupling simulation method for IGBT modules based on working conditions
US20040196081A1 (en) Minimization of clock skew and clock phase delay in integrated circuits
CN115470747B (en) A clock tree synthesis method to achieve rapid timing convergence
CN113392552A (en) Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation
CN116306438A (en) CM-EMI modeling method based on silicon carbide power converter system, system and equipment thereof
CN110120746B (en) Multiphase parallel DCDC circuit and chip structure thereof
Lu et al. Steiner tree based rotary clock routing with bounded skew and capacitive load balancing
CN102411663A (en) Calculation multiplexing method, equipment and system for circuit fine tuning accelerating circuit simulation
US11062072B1 (en) Yield load pull system-based IC design method and system thereof
Gundu et al. Low leakage clock tree with dual-threshold-voltage split input–output repeaters
WO2024008186A1 (en) Method and system for calculating worst power supply noise of high-speed link, and storage medium
Gupta et al. Transmission line synthesis via constrained multivariable optimization
CN109446595B (en) Method for extracting parasitic parameters of silicon carbide inverter
Jun et al. Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Jun et al. Exploiting implementation diversity and partial connection of routers in application-specific network-on-chip topology synthesis
CN116760298A (en) Parallel MOS tube current sharing circuit and test circuit based on source pole differential mode inductance
CN113014215B (en) Design method and system of radio frequency stacked power amplifier
CN119397984A (en) Breaker power module layout optimization method and system based on multi-chip current sharing
CN112115661A (en) A high-efficiency silicon-based millimeter-wave chip and design method
Dong et al. Current Sharing Issues of Paralleled SiC MOSFET
Li et al. Two-port measurement of packaging parasitic inductance in SiC half-bridge power modules considering mutual inductance
Kuzmin Clock Network Design Challenges

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant