CN113392552A - Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation - Google Patents

Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation Download PDF

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CN113392552A
CN113392552A CN202110658355.XA CN202110658355A CN113392552A CN 113392552 A CN113392552 A CN 113392552A CN 202110658355 A CN202110658355 A CN 202110658355A CN 113392552 A CN113392552 A CN 113392552A
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driving module
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parasitic inductance
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宫金武
陈佳洛
林文强
陈思倩
潘尚智
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Wuhan University WHU
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Abstract

The invention relates to the parallel current sharing problem of multi-device high-power MOS (metal oxide semiconductor) tubes, and provides a current sharing optimization design method of a multi-parallel switch device based on finite element simulation. The multiple parallel switching device includes: the drive module, first switching device, second switching device. Manually setting the length of a wiring between a driving module and a switch device, and designing a circuit board through Altium Designer software according to the principle of structural symmetry between a first switch tube device, a second switch tube device, a structure. Determining an optimized target parasitic inductance value; setting a required error; and calculating the width of the wiring between the initialization driving module and the switch device by combining the target parasitic inductance value, and iteratively optimizing the width of the wiring between the driving module and the switch device for multiple times through finite element simulation. The simulation parasitic parameters obtained by the method are high in accuracy, and the parasitic parameters are effectively reduced; the parallel non-uniform current is effectively reduced, and the system stability is improved.

Description

Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation
Technical Field
The invention relates to the field of parallel current sharing design of multiple switch devices, in particular to a current sharing optimization design method of multiple parallel switch devices based on finite element simulation.
Background
In recent years, with the rapid development of power electronic technology, the requirement for power devices is higher and higher, and compared with the traditional Si MOSFET, the SiC MOSFET has many advantages of higher switching speed, lower on-state loss, higher blocking voltage and the like, and can improve the system efficiency, reduce the volume of equipment and further improve the power density of the equipment. However, due to the limitations of cost and the like under the current technological level and specific requirements, the current capacity of a single SiC MOSFET is limited, the requirements of high-power occasions cannot be met, a plurality of SiC MOSFETs often need to be used in parallel, and the scheme of parallel application is widely applied to the fields of motor control, inverters and the like. However, because parameters of the parallel devices in the loop are not consistent, currents of the branches are often unbalanced, the current imbalance causes non-negligible damage to the devices, mainly embodied in loss difference of the parallel devices, current and voltage stress difference of the devices and difference of switching speeds, and the difference causes a single device to be damaged when working under the working conditions of loss and excessive stress for a long time, so that damage is caused to other parallel devices and the whole system.
The current imbalance is mainly divided into static current imbalance and dynamic current imbalance, and main factors causing the dynamic current imbalance include device parameter imbalance, different parasitic inductance of a driving loop, influence of temperature characteristics and the like. The driving circuit plays a crucial role in dynamic current equalization of the parallel devices, and the grid driving resistance and the parasitic inductance in the driving circuit influence inconsistency of driving signals among the branches, so that the switching tube which is turned on first bears overcurrent, and the switching tube is possibly damaged. The conventional design scheme requires that the driving circuit and the main circuit of each switch tube are strictly symmetrically/equidistantly arranged, and in the layout of the multi-device parallel circuit board, firstly, the minimum impedance of the decoupling circuit of the main power circuit of the switch tube is ensured, and the parallel switch tubes are structurally symmetrical, so that the driving circuit of each parallel switch tube is difficult to structurally symmetrical on the basis of the symmetry of the main power circuit of the switch tube, and the design difficulty is brought to the parallel connection of multiple tubes. In order to solve the problem, the invention provides a current sharing optimization design method of a multi-parallel switch device based on finite element simulation.
Disclosure of Invention
In order to solve the problems of the background art, the invention provides a current sharing optimization design method of a multi-parallel switch device based on finite element simulation. Through finite element simulation analysis, parasitic inductance values of all driving loops are obtained, wiring layout is adjusted according to a parasitic inductance empirical expression, so that electrical characteristic symmetry (parasitic inductance equality) of all branches is realized under the condition of asymmetrical structure (unequal widths and lengths of driving wires), and dynamic current equalization of all parallel switching tubes is further realized.
The technical scheme of the invention is a current sharing optimization design method of a multi-parallel switch device based on finite element simulation.
The multiple parallel switching device includes: the driving module, a first switching device, a second switching device, an nth switching device;
the driving module is connected with the ith switching tube device through wiring, i belongs to [1, n ];
the plurality of switching device devices are connected in parallel;
the driving loop i is a loop formed by connecting a driving module and the ith switch tube through a lead;
parasitic inductance L of each driving loopiIs the value at the same frequency f;
the current sharing optimization design method of the multiple parallel switch devices based on finite element simulation comprises the following steps:
step 1: manually setting the length of a wiring between a driving module and a switch device, and designing a circuit board through Altium Designer software according to the principle of structural symmetry between a first switch tube device, a second switch tube device, a structure.
Step 2: determining an optimized target parasitic inductance value;
and step 3: setting a required error;
and 4, step 4: calculating the width of a wire between the initialization driving module and the switch device by combining a target parasitic inductance value, and iteratively optimizing the width of the wire between the driving module and the switch device for multiple times through finite element simulation by combining the width of the wire between the initialization driving module and the switch device;
preferably, in step 1, the length of the trace between the driving module and the switching device is:
the length of the wire between the driving module and the ith switch device is defined as:
li,i∈[1,n]and li∈[lmin,lmax]
Wherein lminFor the shortest distance of the driving loopmaxRouting a longest distance for a driving loop;
preferably, the step 2 specifically comprises:
the constraint conditions of the wiring width between the driving module and each switch device are as follows:
Wi∈[wmin,wmax]
wherein, wminIs the minimum value of the track width, wmaxIs the maximum trace width.
The length of the wire between the driving module and the nth switch device is lmaxSetting the width of the loop as wmaxThe designed circuit board is led into Ansys Q3D, excitation is added, and the line width of the longest driving loop is obtained by finite element simulation by taking parasitic inductance as a research objectmaxParasitic inductance value L of timeoIs prepared by mixing LoAs a target parasitic inductance value;
preferably, the required error in step 3 is defined as σL；
Preferably, in step 4, the calculating a width of a trace between the driving module and the switching device by combining the target parasitic inductance value and the length of the trace between the driving module and the switching device specifically includes:
Figure BDA0003114211460000031
i∈[1，n]
according to the implicit function expression, w can be obtained by means of Mathematica softwarei,0A numerical solution of (a), wherein liIs the length of the trace between the driving module and the ith switch device, LoIs a target parasitic inductance value, wi,0In order to initialize the width of a wire between the driving module and the ith switch device, n represents the number of the switch devices;
step 4.1, mixing wi,jAs the trace width between the driving module and the ith switch tube in the jth iteration, when j is 0, wi,j＝wi,0
Step 4.2, according to the width w of the wiringi,jAfter the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance L of the specific frequency f under the layout is obtained by utilizing finite element simulationi,j；
Step 4.3, if | Li,j-Lo|＜σlThen finishing the design of a driving loop i;
if Li,j-Lo|≥σlAnd L isi,j＜LOW is to bei,jAccording to a certain step length reduction, continuing to execute the step 4.2 until | Li,j-LO|＜σl；
If lLi,j-LO|≥σlAnd L isi,j≥LOW is to bei,jAccording to a certain step length increase, continuing to execute the step 4.2 until | Li,j-LO|＜σl。
Wherein L isi,jThe loop parasitic inductance value W of the driving module and the ith switching device obtained through simulation solution in the step 4.2 in the jth iterationi,jBetween the driving module and the ith switch tube for the jth iterationWidth of trace, LOIs a target parasitic inductance value, σlThe required error is obtained;
the simulation solution is as follows:
solving the numerical solution of the implicit function equation by using a dichotomy by using mathematical software mathematica;
the invention relates to a specific method for current sharing optimization design of a plurality of parallel switch devices based on finite element simulation, which comprises the following steps: under the condition of ensuring the symmetrical layout of the driving module and each switching tube device, the parasitic inductance can be reduced by reasonably adjusting the wiring length and the wiring width of the circuit board, so that the asymmetrical electrical characteristic symmetry of a plurality of driving loop structures can be realized, and the problem of parallel uneven current is reduced to a great extent.
Compared with the prior art, the invention has the following advantages:
the good current equalizing effect can be achieved without additional elements and control;
the simulation operation is simple and easy to realize, and is close to reality, and the accuracy is high;
finite element simulation can be carried out through mesh subdivision without establishing a complex model to obtain a parasitic inductance accurate solution;
drawings
FIG. 1: is a flow chart of the method of the present invention.
FIG. 2: is the most common half-bridge topology with three devices in parallel.
FIG. 3: the invention relates to a three-device parallel half-bridge circuit board layout.
Detailed Description
The invention is described in detail below with reference to the following drawings and specific embodiments:
FIG. 1 is a flow chart of the method of the present invention. The invention is explained by taking a half-bridge topology which is most commonly used by three-device parallel connection as an example, fig. 2 is the most commonly used half-bridge topology which is most commonly used by three-device parallel connection, wherein L is a parasitic inductance value and is a main factor causing parallel dynamic non-uniform current, fig. 3 is a circuit board layout diagram of the three-device parallel half-bridge, the upper and lower tubes are symmetrically driven, the three-tube driving is analyzed by taking the three-tube driving as an example, a lead T1 (upper-layer wire) and a lead B1 (lower-layer wire) are connected with a driving module and a switching tube Q1 to form a driving loop 1 which is a main optimized path, and the driving loop 2 and the. For the convenience of analysis, the voltage peak frequency of the half-bridge module is assumed to be 10MHz, and the parasitic inductance of each driving loop is measured by taking the value as a reference.
The specific implementation mode of the invention is a current sharing optimization design method of a multi-parallel switch device based on finite element simulation.
The multiple parallel switching device includes: the driving module, the first switching tube device, the second switching tube device and the third switching tube device;
the driving module is connected with the ith switching tube device through wiring, i belongs to [1,3 ];
the plurality of switching device devices are connected in parallel;
the driving loop i is a loop formed by connecting a driving module and the ith switch tube through a lead;
parasitic inductance L of each driving loopiIs the value at the same frequency of 10 MHz;
the model of the driving module is 1EDI20H12 AH;
the models of the first switching tube device, the second switching tube device and the third switching tube device are all IMZA65R027M 1H;
the current sharing optimization design method of the multiple parallel switch devices based on finite element simulation comprises the following steps
Step 1: according to the principle of structural symmetry among the first switch tube device, the second switch tube device and the third switch tube device, the wiring lengths among the driving module, the first switch device, the second switch device and the third switch device are set to be 30mm, 64mm and 106mm respectively, and the circuit board is designed through Altium Designer software;
step 2: determining an optimized target parasitic inductance value
The constraint conditions of the wiring width between the driving module and each switch device are as follows:
0.4mm≤Wi≤2mm
the longest length of the wire between the driving module and the third switch device is also lmax＝l3Setting the width of the circuit to be 2mm at 100mm, leading the designed circuit board into Ansys Q3D, adding excitation, and solving by taking parasitic inductance as a research object to obtain parasitic inductance Lo18.7nH, mixing Lo18.7nH as the target parasitic inductance value;
and step 3: set request error σL＝1nH；
And 4, step 4: calculating the width of a wire between the initialization driving module and the first switch device by combining a target parasitic inductance value, and iteratively optimizing the width of the wire between the driving module and the first switch device for multiple times through finite element simulation by combining the width of the wire between the initialization driving module and the first switch device;
and 4, calculating the width of the wiring between the driving module and the switch device by combining the target parasitic inductance value and the wiring length between the driving module and the switch device, specifically:
Figure BDA0003114211460000051
i∈[1，n]
the implicit function expression can be obtained by mathematical software Mathematica
Wi,0=0.46mm≈0.5mm
Wherein, W1,0Initializing the width of a wire between the driving module and the first switch device;
step 4.1, mixing W1，0As the width of the wire between the driving module and the 1 st switch tube at the 0 th iteration,
step 4.2, according to the width W of the wiring1，0After the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance value of the driving circuit 1 at 10MHz in the layout is obtained to be 17.57nH by utilizing finite element simulation;
step 4.3, judge | L1，0-LoI and sigmalThe magnitude relationship of (1) can be known
|L1.0-Lo|＝1.13nH＞1nH＝σlAnd L is1，0>Lo
Then W will be1，0The distance is reduced according to the step length of 0.1mm, namely the width of the drive circuit 1 during the second iteration is 0.4mm, namely W1，1＝0.4mm；
According to the width W of the wiring1，1After the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance value of the driving circuit 1 at 10MHz in the layout is obtained to be 18.30nH by utilizing finite element simulation;
determine | L1，1-LoI and sigmalThe magnitude relationship of (1) can be known
|L1，1-Lo|＝0.4nH＜1nH＝σl
Completing the design of the driving circuit 1;
and 5: only the driving loop 1 is optimized, the step 4 is continuously returned, and iterative optimization is carried out on the driving loop 2;
and 4, step 4: calculating the width of a wire between the initialization driving module and the second switch device by combining a target parasitic inductance value, and iteratively optimizing the width of the wire between the driving module and the second switch device for multiple times through finite element simulation by combining the width of the wire between the initialization driving module and the second switch device;
and 4, calculating the width of the wiring between the driving module and the switch device by combining the target parasitic inductance value and the wiring length between the driving module and the switch device, specifically:
Figure BDA0003114211460000061
i∈[1，n]
the implicit function expression can be obtained by mathematical software Mathematica
W2,0=0.95mm≈1mm
Wherein, W2,0Initializing the width of a wire between the driving module and the second switch device;
step 4.1, mixing W2,0As a firstThe wiring width between the driving module and the second switch tube is 0 time of iteration,
step 4.2, according to the width W of the wiring2,0After the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance value of the driving circuit 2 at 10MHz in the layout is obtained to be 19.67nH by utilizing finite element simulation;
step 4.3, judge | L2,0-LoI and sigmalThe magnitude relationship of (1) can be known
|L2,0-Lo|=0.97nH＜1nH=σl
The simulation solution is as follows:
solving the numerical solution of the implicit function equation by using a dichotomy by using mathematical software mathematica;
the design of the drive circuit 2 is completed.
By combining the analysis, the parasitic inductance values of the driving circuits 1, 2 and 3 designed and obtained by the method are respectively 18.30nH, 19.67nH and 18.7nH, the inductance value difference among the driving circuits is small, the design requirement is met, the electrical characteristic symmetry effect is good, the parallel non-uniform fluidity of the system can be reduced to a large extent, and the stability of the system is improved.
The above embodiments are only preferred embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields by using the contents of the present specification and the accompanying drawings are included in the scope of the present invention.

Claims (5)

1. A current sharing optimization design method of a plurality of parallel switch devices based on finite element simulation is characterized in that,
the multiple parallel switching device includes: the driving module, a first switching device, a second switching device, an nth switching device;
the driving module is connected with the ith switching tube device through wiring, i belongs to [1, n ];
the plurality of switching device devices are connected in parallel;
the driving loop i is a loop formed by connecting a driving module and the ith switch tube through a lead;
parasitic inductance L of each driving loopiIs the value at the same frequency f;
the current sharing optimization design method of the multiple parallel switch devices based on finite element simulation comprises the following steps:
step 1: manually setting the length of a wiring between a driving module and a switch device, and designing a circuit board through Altium Designer software according to the principle of structural symmetry between a first switch tube device, a second switch tube device, a structure.
Step 2: determining an optimized target parasitic inductance value;
and step 3: setting a required error;
and 4, step 4: and calculating the width of the wiring between the initialization driving module and the switch device by combining the target parasitic inductance value, and iteratively optimizing the width of the wiring between the driving module and the switch device for multiple times by combining the width of the wiring between the initialization driving module and the switch device through finite element simulation.
2. The finite element simulation-based current sharing optimization design method for multiple parallel switching devices according to claim 1, wherein the lengths of the routing lines between the driving module and the switching devices in step 1 are as follows:
the length of the wire between the driving module and the ith switch device is defined as:
li，i∈∈[1，n]and li∈[lmin，lmax]
Wherein lminFor the shortest distance of the driving loopmaxThe longest distance is routed for the drive loop.
3. The finite element simulation-based current sharing optimization design method for multiple parallel switches according to claim 1, wherein the step 2 specifically comprises:
the constraint conditions of the wiring width between the driving module and each switch device are as follows:
Wi∈[Wmin，Wmax]
wherein, WminIs the minimum value of the trace width, WmaxThe maximum value of the wiring width is obtained;
the length of the wire between the driving module and the nth switch device is lmaxSetting the width of the loop as WmaxThe designed circuit board is led into Ansys Q3D, excitation is added, and the line width of the longest driving loop is obtained by finite element simulation by taking parasitic inductance as a research objectmaxParasitic inductance value L of timeoIs prepared by mixing LoAs a target parasitic inductance value.
4. The finite element simulation-based current sharing optimization design method for multiple parallel switching devices according to claim 1, wherein the required error in step 3 is defined as σL。
5. The finite element simulation-based current sharing optimization design method for multiple parallel switches according to claim 1, wherein in step 4, in combination with the target parasitic inductance value and the length of the trace between the driving module and the switch device, the width of the trace between the driving module and the switch device is calculated, specifically:
Figure FDA0003114211450000021
i∈[1，n]
according to the implicit function expression, W can be obtained by means of Mathematica softwarei，0A numerical solution of (a), wherein liIs the length of the trace between the driving module and the ith switch device, LoIs a target parasitic inductance value, Wi，0In order to initialize the width of a wire between the driving module and the ith switch device, n represents the number of the switch devices;
step 4.1, mixing Wi，jWhen j is equal to 0, W is taken as the trace width between the driving module and the ith switch tube in the jth iterationi，j＝Wi，0；
Step 4.2, according to the width W of the wiringi，jAfter the circuit board designed in the step 1 is adjusted, the circuit board is led into Ansys Q3D, excitation is added, parasitic inductance is taken as a research object, and the parasitic inductance L of the specific frequency f under the layout is obtained by utilizing finite element simulationi，j；
Step 4.3, if | Li，j-Lo|＜σlThen finishing the design of a driving loop i;
if Li，j-Lo|≥σlAnd L isi，j＜LoW is to bei，jAccording to a certain step length reduction, continuing to execute the step 4.2 until | Li，j-Lo|＜σl；
If Li，j-Lo|≥σlAnd L isi，j≥LoW is to bei，jAccording to a certain step length increase, continuing to execute the step 4.2 until | Li，j-Lo|＜σl；
Wherein L isi，jThe loop parasitic inductance value W of the driving module and the ith switching device obtained through simulation solution in the step 4.2 in the jth iterationi，jThe width of the wire between the driving module and the ith switch tube during the jth iteration, LoIs a target parasitic inductance value, σlTo require an error.
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