CN117709272A

CN117709272A - Dynamic characteristic prediction method and system for castode type power module

Info

Publication number: CN117709272A
Application number: CN202311827683.3A
Authority: CN
Inventors: 卓放; 宋瑞杰; 王丰; 夏镔冰; 田嘉琛; 高鹏宇; 程思悦
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-03-15

Abstract

The invention discloses a dynamic characteristic prediction method and a dynamic characteristic prediction system for a cam type power module, which are used for analyzing the working state of devices in the power module, acquiring the current direction of each branch of the power module and dividing the working state of the devices in the power module; acquiring the nonlinear characteristic of the junction capacitance of a device in the power module; acquiring the transconductance nonlinear characteristic of a device in the power module; according to the current direction of each branch and combining a finite element analysis method, parasitic parameters in the power module and the PCB are obtained; combining the nonlinear characteristics of junction capacitance, the nonlinear characteristics of transconductance and parasitic parameters in the power module and the PCB, determining the switching conditions among the stages according to the working state dividing result of the devices in the power module, constructing a voltage-current equation of each stage of the power module, and solving to obtain the dynamic characteristic prediction result of each stage of the power module.

Description

Dynamic characteristic prediction method and system for castode type power module

Technical Field

The invention relates to the field of wide bandgap semiconductor devices, in particular to a dynamic characteristic prediction method and a dynamic characteristic prediction system for a cascode power module.

Background

Modeling of power electronics has been one of the focus of power electronics research, where modeling of silicon MOSFETs has been mature. With the maturation and application of gallium nitride device technology, modeling for GaN devices has attracted extensive attention from expert students. GaN devices include enhanced (e-mode) gallium nitride and depletion (p-mode) gallium nitride, which, when used, tend to be built in the form of a capode. Regarding modeling of an enhancement mode GaN device, wang Kangping et al of the western traffic university propose a segment model of an enhancement mode GaN device, which considers the influence of parasitic inductance, nonlinearity of parasitic capacitance, and nonlinearity of device transconductance, and writes the voltage-current relation of the on and off processes, and thus calculates the switching loss, but the topology is simple and cannot be simply used for a cascode type power module.

Xie Ruiliang and the like are equivalent to building a continuous analytical model based on a hyperbolic tangent function for an enhanced GaN device, and the model can accurately reflect nonlinearities of current-voltage characteristics and capacitance-voltage characteristics of the enhanced GaN transistor, but the nonlinearity is not suitable for strong nonlinearity occasions, and is difficult to accurately describe the nonlinearity of a casode type power module.

The junction capacitance of the GaN transistor of the field plate structure in the off state is modeled based on physical characteristics, the relation between the physical parameters and the electrical parameters of the device is established, and meanwhile, the nonlinear physical root of the junction capacitance is revealed, but the consistency of the result characterization model constructed by the method and the actual situation is not high. For modeling of the co-source co-gate GaN device, a series of intensive studies have been made by the us CPES center. In order to calculate the power loss of the co-source co-gate type GaN device, factors such as parasitic inductance introduced by packaging and a PCB, nonlinearity of junction capacitance, transconductance of a transistor and the like are comprehensively considered, an accurate analysis model of the co-source co-gate type GaN device is provided, a coupling phenomenon between parasitic inductances in the packaging of the device is pointed out, a method for accurately extracting the parasitic inductance of the packaging of the device is provided, a simulation model of the co-source co-gate type GaN device is built, influence of the packaging and the parasitic inductance on the device characteristics is researched based on the simulation model, and parasitic parameter optimization caused by improving the packaging of the co-source co-gate type GaN device is researched, but the model does not consider that a low-voltage silicon MOSFET is in different states in each stage due to parameter change, so that model consistency is poor and is not accurate enough.

The current state of research shows that the existing research on GaN device modeling mainly focuses on modeling of a single tube and a simple application circuit thereof, and each model only focuses on the accuracy of the modeled model in certain aspects, and there is no literature for comprehensively and accurately modeling the coupling of parasitic parameters among devices and comprehensively analyzing the working modes of a cam type GaN device under the influence of multiple parameters.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a method and a system for predicting the dynamic characteristics of a cathode type power module, which are used for predicting the dynamic characteristics of an overall power module.

The invention is realized by the following technical scheme:

a dynamic characteristic prediction method of a cam type power module comprises the following steps:

s1, analyzing the working state of a device in a power module, obtaining the current direction of each branch of the power module, and dividing the working state of the device in the power module;

s2, acquiring the nonlinear characteristic of the junction capacitance of a device in the power module;

s3, acquiring the transconductance nonlinear characteristic of a device in the power module;

s4, obtaining parasitic parameters in the power module and the PCB according to the current direction of each branch and by combining a finite element analysis method;

s5, combining the junction capacitance nonlinear characteristic, the transconductance nonlinear characteristic and the parasitic parameters in the power module and the PCB of the device in the power module, confirming the switching conditions among the stages according to the working state division result of the device in the power module, constructing a voltage-current equation of each stage of the power module, and solving to obtain the dynamic characteristic prediction result of each stage of the power module.

Preferably, the working state dividing method of the devices in the power module in step 1 is as follows:

cut-off region, silicon MOSFET and gallium nitride HEMT are equivalent to output capacitance C _oss0 And C _oss1 ；

In the saturation region, the silicon MOSFET and gallium nitride HEMT are equivalent to controlled current sources, driven by a drive voltage v _GS0 And v _GS1 Controlling;

in the varistor region, the silicon MOSFET and gallium nitride HEMT are equivalent to the on-resistance R _DS(ON)0 And R is _DS(ON)1 。

Preferably, the step 2 junction capacitance nonlinear characteristic obtaining method is as follows:

and obtaining and fitting the junction capacitance of the device in the power module to obtain the nonlinear characteristic of the junction capacitance of the device in the power module.

Preferably, the junction capacitance is fitted by adopting an interpolation fitting or linear regression fitting method.

Preferably, the method for acquiring the transconductance nonlinear characteristic in the step S3 is as follows:

and acquiring current and voltage curves of devices in the power module, and extracting transconductance nonlinear characteristics according to the current and voltage curves.

Preferably, the method for obtaining the parasitic parameter in step S4 is as follows:

based on the current direction of each branch, respectively constructing three-dimensional physical models of the PCB and the power module, constructing a bonding wire model with the same parameters as the actual bonding wire, defining a current inflow source point and a current outflow sink point, and obtaining parasitic parameters of the power module and the PCB through finite element simulation.

Preferably, in step 5, the voltage and current equation of each stage is transformed to obtain a corresponding space state equation, and MATLAB is adopted to solve the space state equation to obtain the dynamic characteristic prediction result of each stage of the power module.

A system for predicting dynamic characteristics of a code type power module comprises,

the current direction analysis module is used for analyzing the working state of the devices in the power module, obtaining the current direction of each branch of the power module and dividing the working state of the devices in the power module;

the junction capacitance characteristic module is used for acquiring the nonlinear characteristic of the junction capacitance of the device in the power module;

the transconductance characteristic module is used for acquiring transconductance nonlinear characteristics of devices in the power module;

the parasitic parameter module is used for acquiring parasitic parameters in the power module and the PCB according to the current direction of each branch and by combining a finite element analysis method;

the dynamic characteristic prediction module is used for combining the junction capacitance nonlinear characteristic, the transconductance nonlinear characteristic and the parasitic parameters in the power module and the PCB of the device in the power module, confirming the switching conditions among the stages according to the working state division result of the device in the power module, constructing a voltage-current equation of each stage of the power module and solving the voltage-current equation to obtain the dynamic characteristic prediction result of each stage of the power module.

Compared with the prior art, the invention has the following beneficial technical effects:

according to the dynamic characteristic prediction method of the cascode power module, parasitic inductance distribution of the high-voltage gallium nitride HEMT and low-voltage silicon MOSFET structure power module in an on process and an off process respectively is analyzed, nonlinearity of the low-voltage silicon MOSFET and high voltage is considered, switching conditions of adjacent switching modes are analyzed, different switching sequences of the switching modes under different conditions are analyzed, circuits of all the switching modes are analyzed, corresponding space state equations are obtained, numerical solutions under certain conditions are obtained through the space state equations, and each current value of the whole switching process is obtained.

Drawings

FIG. 1 is a circuit diagram of a cascode GaN power module of the invention;

FIG. 2 is a state analysis diagram of a cathode-type GaN power module according to the present invention;

FIG. 3 is a graph showing a junction capacitance nonlinear characteristic of a cascode GaN power module according to the present invention;

FIG. 4 is a graph of a nonlinear transconductance characteristic of a cascode GaN power module according to the present invention;

FIG. 5 is an internal parasitic parameter extraction diagram of a cascode GaN power module according to the present invention;

FIG. 6 is an extraction diagram of parasitic parameters of an external PCB circuit of a cascode GaN power module according to the invention;

FIG. 7 is a flow chart of a turn-on process of a cascode GaN power module according to the present invention;

FIG. 8 is a circuit diagram of stages in a turn-on process of a cam type GaN power module according to the present invention;

FIG. 9 is a circuit diagram of various stages in a turn-off process of a cam type GaN power module according to the present invention;

FIG. 10 is a graph of the results of an analysis model of the turn-on process of a cascode GaN power module according to the present invention;

FIG. 11 is a graph showing the result of a model for turning off a gallium nitride power module according to the invention.

Detailed Description

The invention will now be described in further detail with reference to the accompanying drawings, which illustrate but do not limit the invention.

s1, analyzing the working state of a device in the power module, obtaining the current direction of each branch of the power module, and dividing the working state of the device in the power module.

Fig. 1 is a block diagram of a gallium nitride power module of a cathode type, which is an application example of the mathematical model proposed by the present invention. In the figure, the DSP representsGeneral controller V _G Represents the driving voltage, R _G Represents the driving resistance, L _g0 Represents the parasitic inductance of the drive wiring, L _k Represents Kelvin trace parasitic inductance, L _s1 Represents parasitic inductance of silicon MOSFET drain and gallium nitride HEMT source connection wiring, L _g1 Represents parasitic inductance of silicon MOSFET source and gallium nitride HEMT gate connection wiring, L _d1 Representing the parasitic inductance of the wiring from the drain electrode of the gallium nitride HEMT to the positive electrode of an external direct current source, L _s Representing the parasitic inductance of the wiring from the source of the silicon MOSFET to the cathode of the external DC source, C _GD0 、C _GS0 And C _DS0 Respectively representing the capacitance of the gate drain, the gate source and the drain source of the silicon MOFSET, C _GD1 、C _GS1 And C _DS1 Respectively representing the capacitance of the grid drain electrode, the grid source electrode and the drain source electrode of the gallium nitride HEMT, V _in Representing equivalent quantity of direct-current voltage input equipment and direct-current bus supporting capacitor in actual circuit, I _L Representing the equivalent value of the inductor current in the extremely short time of the switching process, and the diode represents the equivalent diode which is arranged on the other side of the bridge arm or works as a passive tube when the diode is controlled.

Because the mathematical analysis model provided by the invention needs to accurately extract and model various elements in the structure, the current in the structure needs to be analyzed so as to avoid the inaccuracy of parasitic inductance extraction to influence the final mathematical model result. In fig. 1, the current direction on different branches in the on or off state can be obtained by analysis, and the current direction directly affects the value of mutual inductance between different inductors, so that it is necessary to perform loop current direction analysis before parasitic parameter extraction is performed, it can be seen that the current direction of the main loop is always unchanged in the on-off state, the loop currents of the silicon mosfet and the gallium nitride HEMT respectively change, and the common part current of the driving loop and the main loop is determined by the main loop current. In the parasitic inductance extraction stage of step 4, the current flow direction needs to be set accurately to ensure that parameters are accurate.

To accurately build a mathematical analysis model, nonlinear devices in a circuit need to be modeled in different stages. The circuit comprises a low-voltage silicon MOSFET,Three nonlinear devices, namely a high-voltage gallium nitride HEMT and a diode. Fig. 2 shows the voltage v of the gate source electrode of two voltage-controlled devices of silicon MOSFET and gallium nitride HEMT in the structure _GS And v _DS And the determined device states are switched among a cut-off region, a saturation region and a variable resistance region in the switching process under the normal working condition, and each switching corresponds to one conversion of the working state of the whole power module. In the cut-off region, the two devices are equivalent to the output capacitance C _oss0 And C _oss1 The method comprises the steps of carrying out a first treatment on the surface of the In the saturation region, the two devices are equivalent to controlled current sources, driven by a voltage v _GS0 And v _GS1 Controlling; in the varistor region, the two devices are equivalent to on-resistance R _DS(ON)0 And R is _DS(ON)1 . The operating state of the circuit diode is simply divided into an on state and an off state.

According to the analysis, the parasitic inductance can be accurately extracted, the working state of the device can be accurately divided, and the method is respectively used for extracting the parasitic inductance in the step 4 and constructing the mathematical analysis model in the step 5.

S2, obtaining and fitting the junction capacitance of the device in the power module to obtain the nonlinear characteristic of the junction capacitance of the device in the power module.

In the invention, the nonlinear characteristic of the device junction capacitance needs to be accurately modeled. The silicon MOSFET and the gallium nitride HEMT are both voltage driven devices, corresponding junction capacitances exist among three electrodes of a drain electrode, a source electrode and a grid electrode, and in an actual circuit, the input capacitance C is influenced as a whole _iss Output capacitance C _oss And feedback capacitance C _rss Wherein the capacitance C is input _iss ＝C _GS +C _GD Output capacitance C _oss ＝C _DS +C _GD Feedback capacitor C _rss ＝C _GD 。

In operation, the change of the depletion layer inside the device dominates the change of the capacitance, at the drain-source voltage v _DS The junction capacitance exhibits strong nonlinearity at full voltage, especially within 100V of low voltage, and there is a capacitance change of 1 to 3 orders of magnitude within the full voltage, which results in a difference in switching speed between the low and high voltage states during switching. If junction capacitance nonlinearities are not considered in the model, the effect will beAnd the judgment of the actual switching speed further influences the estimation of the actual switching loss, which is not beneficial to the construction of an accurate construction analysis model.

If the datasheet provided by the device comprises a junction capacitance-drain-source voltage curve, the datasheet data points can be directly extracted and fitted by MATLAB curve fitting; if the datasheet curve is not available or more accurate curve results are needed for the device, the static characteristics of the device need to be measured by adopting a curve tracking device such as B1506A and the like, and the data can be directly used for data fitting in the next step.

The data with weaker nonlinearity can be fitted by using exponential fitting and the like, and the fitting mode has a better prediction effect on the data outside the rated voltage, but the data with stronger nonlinearity is difficult to fit by using a conventional fitting formula. And the fitting result of MATLAB can be directly used for constructing a mathematical model.

Fig. 3 shows curve fitting data of three junction capacitances, and it can be seen that excellent fitting performance is difficult to obtain by using a conventional formula fitting under the condition of good curve fitting effect, especially under the strong nonlinear condition within 100V. The method for extracting and fitting the nonlinear capacitance can obtain extremely high fitting degree and can be directly used for junction capacitance characteristics of a mathematical analysis model.

S3, acquiring current and voltage curves of devices in the power module, and extracting transconductance nonlinear characteristics of the devices in the power module according to the current and voltage curves.

In the invention, the transconductance nonlinear accurate modeling is needed. Transconductance g _m Gate-source voltage v when the device is in a controlled current source state _GS For channel current i _ch Has a control coefficient of i _ch ＝g _m (v _GS -V _TH ) Transconductance g is generally considered _m Also v _GS And typically linearizes it, but the actual device transconductance and gate-source voltage are not linear and their non-linear characteristics need to be taken into account.

Fig. 4 shows the fitting result of the current, and the fitting result of the current can be used for obtaining the corresponding transconductance fitting result, so that the fitting quality of the method is high.

the invention requires accurate modeling of parasitic inductance and high frequency resistance in the circuit board. Based on the current direction analysis result in the step 1, three-dimensional physical models of the PCB and the power module can be respectively constructed through finite element software such as ANSYS Q3D, selection of specified materials in the models, construction of a bonding line model with the same parameters as actual bonding lines, and definition of a current inflow source point and a current outflow sink point. It should be noted that if a certain metal network is one-end current inflow and multi-end current outflow, a source is set at a current outflow point, a sink is set at a current inflow point, and in the final data processing, the related mutual inductance values are inverted to obtain the correct parasitic parameters.

Fig. 5 and fig. 6 are a physical model of a power module and a physical model of a PCB board in an embodiment, and a required high-frequency parasitic parameter matrix can be obtained through finite element simulation, which is used for mathematical analysis model construction and dynamic characteristic prediction in step 5.

S5, combining the junction capacitance nonlinear characteristic, the transconductance nonlinear characteristic and the module interconnection parasitic parameter of the devices in the power module, confirming the switching conditions among the stages according to the working state division result of the devices in the power module, constructing a voltage-current equation of each stage of the power module, further obtaining a corresponding space state equation of each stage, and solving the space state equation to obtain a dynamic characteristic prediction result of each stage of the power module.

Based on the obtained junction capacitance and transconductance nonlinear characteristics, and parasitic parameters and high-frequency resistance obtained through finite element analysis software, the circuit states of each switching stage can be analyzed, corresponding space state equations can be obtained, and MATLAB is utilized to solve the space state equations so as to obtain the switching characteristics. It should be noted that under the influence of the circuit parameters, there are different turn-on processes, as shown in fig. 7, which are mainly dependent on the mode switching speed of the low-voltage silicon MOSFET.

S501: at time t0, V _G Generating a step voltage of 12V through R _G ，L _g For C _iss0 Since CGS0 is much larger than the other junction capacitances, the process can be considered to charge CGS0 primarily. The silicon and GaN channels remain closed during this process, so the equivalent circuit is shown. This phase ends at time t1, vGS0 reaches VTH0.

At time t1, v _GS0 Reach V _TH0 The silicon transistor enters a saturated state, and the channel current is used as a controlled current source to absorb the silicon MOS junction capacitor C _GD0 ，C _DS0 ，C _GS1 An electric charge. Not neglecting L _s1 And L _g1 The delay effect is brought about when id0=is1=ig1, based on v _DS0 The speed of change is different. This phase ends at time t2, v _GS1 Rising to V _TH1 。

If v _DS0 When the voltage drops to 0 in this stage, the low-voltage silicon MOSFET enters the varistor region first, corresponding to the case 2 of entering the on stage 3, and the charging speed of the high-voltage gallium nitride HEMT is faster.

At time t2, if v _GS1 Reach V _TH1 Gallium nitride HEMT enters a saturated state, and gallium nitride HEMT junction capacitor C _DS1 And C _GD1 By discharging through the channel, resulting in a voltage v _DS1 Drop down at v _DS0 +v _DS1 <V _in A corresponding voltage difference is applied to the parasitic inductance L _d1 +L _s1 +L _s On, cause the main loop current i _d1 Rapidly increases and the current slew rate is v _DS1 Decreasing and increasing. Due to inductor current I _L ＝i _d1 +i _db The inductor current is thus gradually diverted from the diode to the main loop. This phase ends at time t3, i _d1 Increased to I _L 。

If v _DS0 At this stage down to 0, the low voltage silicon MOSFET first enters the varistor region.

time t3, i _d1 Increased to I _L And i _d1 The rate of rise has reached a maximum. Since the gallium nitride HEMT has no reverse recovery, due toThis is considered to be directly equivalent to the opposite side transistor from time t3 as the capacitor C _db ，v _DS1 From the previous slow drop (providing a voltage difference i for parasitic inductance) _d Increasing) becomes a rapid decrease during which the current rise rate changes less, resulting in a more constant voltage across the parasitic inductance. This phase ends at drain-source voltage v _DS1 Decreasing to 0.

If v _DS0 At this stage down to 0, the low voltage silicon MOSFET first enters the varistor region quickly.

At time t4, when v _DS1 Reducing to 0, the gallium nitride HEMT enters the variable resistance region from the saturation region, the gallium nitride HEMT is equivalent to on-resistance, and the channel current is not influenced by V any more _GS1 Control, corresponding v _GS1 And v _DS0 Is no longer clamped by the current of the main loop, L _g1 ，L _s1 ，C _GS1 The LC tank whose initial value is the end value of the previous stage is constituted, and the damping effect of the parasitic resistance on the current needs to be considered at this stage. It should be noted that at this stage v _GS1 At risk of exceeding v _GS1max It is necessary in the design to measure whether its magnitude exceeds the maximum gate-source voltage (known as 10V from datasheet).

In addition, the silicon MOSFET drain-source voltage v is not clamped at this stage _DS0 Rapidly decline, C _DS0 And C _GD0 Through rapid discharge of the channel, correspondingly, the silicon MOSFET drives current to C rapidly _GS0 Charging to increase the capacity for discharge current up to v _DS0 Decreasing to 0, the silicon MOSFET now enters the variable resistance region from the saturation region.

At time t5, both transistors enter the on-resistance phase, and the drive loop of the silicon MOSFET is completely decoupled from the main loop due to the Kelvin connection, at which stage V _G Pair C through RLC loop _GS0 Charging up to v _GS0 ＝V _G In this process, R _ds(on)0 Subject to gate-source voltage v _GS0 With v _GS0 Increasing and gradually decreasing, and is in a variable resistance state.

On the other hand, the driving circuit of gallium nitride HEMT cannot realize Kelvin connection, so that the circuit thereofResonance pass L _s1 And R is _ds(on)1 Still coupled to the main loop and affects the oscillation of the main loop current through Ls 1. In the whole, C can be _GS1 ，L _s1 ，R _ds(on)0 ，L _g1 The formed network is regarded as an impedance, and is connected with a current source and R _ds(on)1 、L _d1 、L _s1 Together forming an RLC charging loop, drain current i _d1 At on-resistance R _ds(on)0 And R is _ds(on)1 Is damped by (a) the oscillation gradually decays until it stabilizes at I _L This phase ends.

Through the above analysis on different opening processes, the circuit equivalent circuits at different stages are obtained as shown in fig. 8, the equations are written in columns, and the corresponding space state equations are obtained, so that the voltage and current waveforms in the opening processes can be obtained as shown in fig. 9.

S502: at time t0, V _G Jump from 12V to 0V, C _GS0 And C _GD0 By R _G ，L _g Discharge due to C _GS0 Far greater than C _GD0 C is often ignored in this process _GD0 . In this process, the silicon and gallium nitride channel currents are not affected, and the equivalent circuit is shown in the following figure, and this phase ends at time t1, satisfying the silicon MOSFET going from the variable resistance region into the saturation region.

time v at t1 _GS0 Reach I _L /g _m0 +V _TH0 And continue to decrease, the low voltage silicon MOSFET enters the saturation region from the variable resistance region, v _GS0 Controlling the channel current to make the channel current i _ch0 With v _GS0 And decreases. The node current law is satisfied at the drain node of the silicon MOSFET, and the current I is input to the node _L Remain unchanged, i _ch0 In the case of reduction, the redundant current pair C _GD0 And C _DS0 Charging, C in special cascode configuration _DS0 And C _GS1 In parallel, thus passing through the inductance L at the same time _s1 And L _g1 For C _GS1 Charging, v _DS0 Rapidly rise from 0, V _GS1 And rapidly decreases from 0. This phase ends when the HEMT goes from the variable resistance region into the saturation region

At time t2, if silicon MOSFETThe driving loop has very small resistance and its input capacitance C _iss0 The discharge is fast, the silicon MOSFET has entered the cut-off region from the saturation region before the gallium nitride HEMT enters the saturation region from the resistance region, at which time the silicon MOSFET is equivalent to the output capacitance C _oss0 At this time, the main loop current charges the output capacitor of the silicon MOSFET after passing through the gallium nitride channel, v _DS1 Rapidly increasing, it should be noted that gallium nitride HEMT input capacitance C _iss1 And C _oss0 Anti-parallel, thus being discharged simultaneously, v _GS1 And rapidly decreases. When the silicon MOSFET enters the cut-off region, the external driving loop and the power loop are decoupled, C in the external driving loop _GS0 Continuously discharging until v _GS0 Equal to 0. End mark is gallium nitride HEMT gate-source voltage v at time t3 _GS1 Reduce to I _L /g _m1 +V _TH1 The gallium nitride HEMT enters the saturation region from the resistance region.

At time t3, v _GS1 Reach I _L /g _m1 +V _TH1 And continue to decrease, the high voltage gallium nitride HEMT goes from the variable resistance region into the saturation region, v _GS1 For channel current i _ch1 Acting to control, when v _GS1 Further reduction, forcing the channel current to decrease and be less than the power loop current I _L The excessive current starts to flow to C _GD1 And C _DS1 Charging, v _DS1 Rapidly increase, while the diode voltage v _db Rapidly decreasing, and the current caused by the voltage change across the diode shares a part of I _L Thus i _d1 And consequently decreases. This phase ends at the gallium nitride HEMT gate-source voltage v _GS1 Down to V _TH1 The gallium nitride HEMT enters the cut-off region from the saturation region.

At time t4, the gallium nitride HEMT enters a cut-off region from a saturation region, and is equivalent to an output capacitor C in a main loop _oss1 Gallium nitride HEMT channel is completely closed, and power loop current is opposite to output capacitor C _oss1 And (5) charging. At a higher v _DS1 Lower C _oss1 The nonlinearity is not obvious, and the capacitance is not changed at this stage.

It should be noted that the voltage-current variation at this stage involves the dc bus voltage V _in At this time, divided by diode, power device and powerLoop parasitic inductance. When the whole power device enters the cut-off region, more current is shunted by the power device and enters the diode to accelerate the voltage drop of the two ends of the power device, and the voltage v of the drain and the source of the gallium nitride HEMT is correspondingly increased _DS1 And rapidly rises. Ignoring the forward recovery and forward conduction voltage drop of the diode, the voltage drop across the diode at the moment t5 ends in this stage to zero, meaning that the freewheeling diode is forward biased and enters the forward conduction state from the reverse off state.

At time t5, diode voltage v _db Minimizing as diode to assume constant current source I _L The remaining part of the current in the main loop oscillates via the main loop inductance, the output capacitance of the two devices and other parasitic parameters of the two drive loops.

Through the above analysis on different turn-off processes, the circuit equivalent circuits of different stages are obtained as shown in fig. 10, the equations are written in columns, and the corresponding space state equations are obtained, so that the voltage and current waveforms of the turn-off processes can be obtained as shown in fig. 11.

The invention also provides a system for predicting the dynamic characteristics of the SCODE type power module, which comprises,

The invention provides a dynamic characteristic prediction method of a cam type power module, which is used for solving the problems that the existing model is not accurate enough, the dynamic characteristic prediction is not accurate enough, the switching mode analysis is not strict enough, and the switching process judgment is not comprehensive enough. According to the invention, parasitic parameters of the silicon MOSFET, the depletion gallium nitride HEMT, the bonding wire between the internal transistors and the copper wiring in the module are synthesized, nonlinear changes of junction capacitance and device transconductance and mutual inductance between parasitic inductances in the module are considered, and a high-frequency parasitic parameter model of the cam type power module is obtained, and can be popularized to high-frequency parasitic parameter matrixes with different parallel numbers, so that accurate modeling of the whole power module is realized.

The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims

1. The method for predicting the dynamic characteristics of the castcode type power module is characterized by comprising the following steps of:

2. The method for predicting dynamic characteristics of a cam type power module according to claim 1, wherein the method for dividing the working states of devices in the power module in step 1 is as follows:

3. The method for predicting dynamic characteristics of a cam type power module according to claim 1, wherein the step 2 of obtaining the nonlinear characteristics of the junction capacitance is as follows:

4. A method for predicting dynamic characteristics of a cam type power module according to claim 3, wherein the junction capacitance is fitted by adopting an interpolation fitting or linear regression fitting method.

5. The method for predicting dynamic characteristics of a cam type power module according to claim 1, wherein the method for acquiring the transconductance nonlinear characteristic in step S3 is as follows:

6. The method for predicting dynamic characteristics of a cam type power module according to claim 1, wherein the method for obtaining the parasitic parameter in step S4 is as follows:

7. The method for predicting the dynamic characteristics of a cam type power module according to claim 1, wherein in the step 5, the voltage and current equation of each stage is transformed to obtain a corresponding space state equation, and the space state equation is solved by MATLAB to obtain the dynamic characteristic prediction result of each stage of the power module.

8. A system for performing a method for predicting dynamic characteristics of a power module of the capode type as claimed in any one of claims 1-7, comprising,