CN113392025B - Method for monitoring process of reconfigurable FPGA software - Google Patents
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Abstract
The invention discloses a method for monitoring a process of reconfigurable FPGA software, which comprises the following steps: the special verification test system utilizing the reconfigurable FPGA software is used for leading out important internal signals through FPGA pins while carrying out copying monitoring on the important internal signals, and transmitting the important internal signals from a test board to a main control FPGA board through the FPGA pins for collection. The special verification test system of the reconfigurable FPGA software comprises: a signal transfer layer module; a verification instruction layer module; verifying a functional layer module; verifying an environment layer module; and verifying the top layer module.
Description
Technical Field
The invention relates to the field of computer software verification and test, in particular to a method for monitoring a process of reconfigurable FPGA software.
Background
The field programmable logic device (FPGA) technology has evolved tremendously over the last decades, essentially: the FPGA can solve the problems of miniaturization, low power consumption, high reliability and the like of an electronic system, has short development period, little development software investment and continuously reduced chip price, promotes the FPGA to replace the market of the ASIC more and more, and particularly, the FPGA is the first choice for small-batch and multi-variety product requirements.
At present, aiming at the requirements of more and more on-satellite FPGA software reconstruction realization, the traditional FPGA verification test means cannot meet the verification requirements of reconfigurable FPGA software in terms of verification function test point coverage and verification accuracy. The conventional verification test system architecture takes the design requirement specification of the on-board FPGA reconfigurable code as a guide to formulate a verifiable test scheme, writes a directional test case for a part of codes to be tested by adopting a hardware description language after defining a test point to be verified, judges whether the designed function is correct or not by observing an output waveform in the verification process, is usually implemented on an EDA verification test software tool, and is generally shown in figure 1 for the erection of the conventional FPGA verification test system. Fig. 1 shows a conventional FPGA verification test architecture setup.
In addition, lv Xinxin et al put forward a relatively advanced FPGA general verification platform in FPGA general verification platform establishment method research in microelectronics and computer 2010.5, the platform architecture is established from three aspects of adopting a hierarchical structure, unifying test case formats and extracting general base classes, the platform architecture is mainly changed easily through modularized operation, and meanwhile, clearer layering division of the platform is utilized, so that certain independence among layers is ensured.
Disclosure of Invention
Traditional FPGA verification test system erection is guided by task demands only, and cannot be well adapted to a plurality of special verification points of reconfigurable FPGA software, such as: the reconstruction process monitoring, the reconstruction realization function verification, the active inspection of the integrity of the reconstruction code and the like become verification test dead zones of the FPGA reconfigurable software. Meanwhile, the complicated and diversified reconstruction function requirements are required to drive the continuous change of the excitation section. Frequent updating, compiling, and then implementation of test stimulus code all take a lot of manpower and time.
The later proposed FPGA general verification test system is erected by utilizing a hierarchical structure, a unified test case format and extracting general base classes, but because the main point is to establish a general verification platform, the FPGA software is not considered to be closely related to an interface protocol, and the general verification environment of the FPGA can not be realized for all kinds or functions; meanwhile, the drive classes in the system architecture are all from an upper drive layer, and the drive is transmitted by calling pre-existing drive data, so that the method has a plurality of defects: 1. the precompiled driving code library needs to have a large sample test library, the library is to be realized in advance for all chip types and different functions, the background workload is conceivable, and once verification requirements with special test points such as reconfigurable FPGA software appear, the top layer can only be erected from a verification test system to be added, and then the steps are complicated. 2. It is also not possible to verify the desired verification point of interest to the reconfigurable FPGA software, such as the reconfiguration process monitoring, whether the implementation of the reconfiguration function is correct, etc. 3. The architecture is too tightly hierarchical to allow autonomous tuning pruning based on reconfigurable needs.
In view of the problems in the prior art, according to one aspect of the present invention, there is provided a method for process monitoring of reconfigurable FPGA software, comprising: the special verification test system utilizing the reconfigurable FPGA software is used for leading out important internal signals through FPGA pins while carrying out copying monitoring on the important internal signals, and transmitting the important internal signals from a test board to a main control FPGA board through the FPGA pins for collection. The special verification test system of the reconfigurable FPGA software comprises: the signal transmission layer module provides direct signal interconnection with the reconfigurable FPGA software to be tested and is accessed by other modules of the special verification test system; the verification instruction layer module is used for monitoring the foremost input and the foremost output of the target reconstruction code to be detected of the reconfigurable FPGA software and also monitoring the running process of the target reconstruction code to be detected; the verification function layer module compares the output result of the target reconstruction code to be tested with the processing result of the verification platform; the verification environment layer module registers the scene use in the environment layer; and the verification top layer module defines a global top layer file and constrains the working modes of the global variable and the target reconstruction code to be tested.
In one embodiment of the present invention, the authentication instruction layer module includes:
the one or more detection monitoring modules monitor the foremost input and the endmost output of the target reconstruction code to be detected of the reconfigurable FPGA software;
the driving generation module is used for driving and generating the most direct excitation input serving as the target reconstruction code to be tested, so that the driving excitation is ensured to be correctly and completely applied to the target reconstruction code to be tested;
the driving scheduling module is an upper layer cooperation module of the driving generation module and is used for dynamically adjusting and changing the driving scheduling module;
the process monitoring module is used for monitoring the operation process of the target reconstruction code to be detected;
and the time recording module is used for carrying out real-time monitoring on the target reconstruction code to be detected along with the process monitoring module, and acquiring complete reconstruction time and reconstruction interval by setting a start and end register signal.
In one embodiment of the present invention, the authentication function layer module includes an input agent module and an output agent module.
In one embodiment of the invention, the input agent module controls when the detection monitoring module begins monitoring inputs and when the co-drive generation module and the drive scheduling module work together.
In one embodiment of the invention, the output proxy module sorts and integrates the data acquired by the detection monitoring module of the output end, and controls the detection monitoring module of the output end.
In one embodiment of the present invention, the authentication function layer module includes: and the comparison module and the model reference library are used for carrying out secondary confirmation verification test on the copy target code by using input signal excitation through the model reference library, and comparing the result with the result of the actual target test code through the output monitor through the comparison module.
In one embodiment of the invention, the verification environment layer module comprises a conventional reconstruction function verification environment library, a reconstruction test code environment library and a reconstruction tracking code environment library.
In one embodiment of the present invention, the reconfigurable test code environment library performs the following verification on reconfigurable FPGA software: and (5) relevant fault injection verification, reconstruction program correctness verification, reconstruction program integrity verification and reconstruction data verification correctness verification.
In one embodiment of the present invention, the reconfigurable trace code environment library performs the following tests on reconfigurable FPGA software: a reconfiguration failure recovery test, a system reconfiguration time test and a reconfiguration failure recovery test.
In one embodiment of the invention, the verification top layer module generates different scenes through different constraints, realizes the test of the directional function test point of the target reconstruction code to be tested, or realizes the randomized verification of the target reconstruction code to be tested through random scene change.
The invention provides a verification test system erection aiming at on-board on-orbit reconfigurable FPGA software. The system erection can solve the following problems:
1) Establishing a flexible and variable verification test system erection, and verifying the on-board reconfigurable FPGA software by using the system erection;
2) A process monitoring module is added into the system erection model to solve the problem of reconfigurable process monitoring of on-board reconfigurable FPGA software;
3) Adding a time recording module into the system erection model to solve the problems of actual reconfigurable time, record of the time of completion of the reconfiguration, the time interval of the reconfiguration and the like of the on-board reconfigurable FPGA software;
4) Adding a DUT module copying and recording comparison module into the system erection model to solve the problem that the current partial verification only verifies whether the test function point is correct or not and cannot prove whether the test function point is not wrong or not;
5) The drive dispatch control module is added in the system erection model, so that the problems that the drive transmission logic cannot be flexibly changed after one-time excitation are solved.
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To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
Fig. 1 shows a conventional FPGA verification test architecture setup.
FIG. 2 shows a schematic block diagram of a dedicated verification test system 200 for reconfigurable FPGA software, according to one embodiment of the invention.
FIG. 3 illustrates a schematic block diagram of a full flow verification monitoring implementation in a verification instruction layer module in accordance with one embodiment of the invention.
FIG. 4 shows a schematic block diagram of an implementation of a model reference and result comparison module in a verification function layer module in accordance with one embodiment of the invention.
FIG. 5 illustrates a verification test point profile for a reconfigurable code implementation in a verification environment in accordance with one embodiment of the invention.
FIG. 6 shows a flow chart of a verification process for reconfigurable FPGA software according to one embodiment of the invention.
Detailed Description
In the following description, the present invention is described with reference to the embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without the specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
In order to improve the pertinence of the reconstruction test verification of the FPGA software, the applicability of the FPGA software to various reconstruction realization forms and the requirements of verification authenticity and efficiency. Aiming at the reconfigurable verification test direction of the FPGA, a test verification scheme combining verification methodology is provided: top-down hierarchical verification test scheme based on FPGA software reconfiguration. The overall architecture of the top-down hierarchical verification test scheme is as follows: the verification top layer, the verification environment layer, the verification function layer, the verification instruction layer and the signal transmission layer are five layers. The five layers are closely connected, and each layer maintains certain independence through modularized division.
FIG. 2 shows a schematic block diagram of a dedicated verification test system 200 for reconfigurable FPGA software, according to one embodiment of the invention.
As shown in fig. 2, the dedicated verification test system 200 includes a signaling layer module 210, a verification instruction layer module 220, a verification function layer module 230, a verification environment layer module 240, and a verification top layer module 250.
The signal transmission layer module 210 can provide direct signal interconnection with the reconfigurable FPGA software to be tested, and can be freely accessed by any layer module above the signal transmission layer module, so that the flexibility of the platform is greatly ensured on the premise of ensuring that the bottom layer signal transmission is accurate, and the signal transmission layer module is mainly connected with interfaces, clock domains and the like. The signal transfer layer module 210 also acts as the most direct driving layer for the target reconstruction code to be tested.
The verification instruction layer module 220 may include one or more detection monitoring modules 221, a drive scheduling module 222, a process monitoring module 223, a time recording module 224, and a drive generation module 225, among others.
Conventional verification tests typically only concern consistency between the output results and the expected expectations, while what is of interest for practical use such as reconfigurable FPGA software is simply a relatively simple synergy of the output results and the expected expectations. Therefore, one or more detection and monitoring modules 221 need to add detection and monitoring modules to input and output, so as to perform real-time detection and monitoring on the input and output signal data.
The driver generation module 225 is used to generate the most direct stimulus input to the device under test or the object code (DUT), and needs to ensure that its driving stimulus can be properly and completely applied to the DUT, and its value is the most direct stimulus input verification to the DUT.
The driving dispatching module 222 can be used as an upper layer of the driving generating module and a cooperation module, because of the special implementation and complexity of the reconfigurable software, the directional test of the reconfigurable software can not be realized by single driving generation or unordered driving excitation, and the test accuracy and directivity are insufficient, so that the driving dispatching module is required to flexibly generate driving excitation, dispatch and control various driving, and the driving dispatching module can dynamically adjust and change the realization excitation generation and the function requirement of the strong fitting degree according to the actual function and the required verification test point of the reconfigurable FPGA software.
For simple FPGA realization, whether DUT test is accurate or not can be verified to a certain extent by paying attention to input and output, but for complex software such as an on-board reconfigurable FPGA, the function of the FPGA cannot be illustrated only by monitoring input and output, but the design of the FPGA cannot be illustrated, and a plurality of internal problems cannot be exposed in time.
The time recording module 224, in combination with the process monitoring module, may acquire the complete reconstruction time, the reconstruction interval, etc. for calculation by setting the start-end register signal while the process monitoring is performed in real time on the object to be measured. The problem of complete simulation reconstruction time detection is accurately solved.
The conventional simulation verification means can only carry out simulation verification on internal signals through simulation software, but because of the specificity of the reconfigurable FPGA software, when verification tests are carried out only on the reconfigurable FPGA software, the verification means for carrying out simulation observation on the internal signals by means of the simulation verification means often have the defects, and the actual reconstruction process cannot be truly restored due to the fact that the simulation of the whole reconstruction process cannot be completely executed due to the current simulation speed limitation, and meanwhile, the method also comprises the following steps: the true reconstruction program receives the problems of the integrity and the correctness judgment, the reconstruction failure probability, the reconstruction failure recovery and the like which accord with the non-measurable problem of the important verification test points of the reconstruction FPGA software.
In order to solve the problems, the invention provides a verification means which is different from the traditional verification test and only observes the result, and the invention creatively adds a process monitoring implementation by monitoring the forefront input and the final output of the reconstruction code of the target to be detected. FIG. 3 illustrates a schematic block diagram of a full flow verification monitoring implementation in a verification instruction layer module in accordance with one embodiment of the invention. As shown in fig. 3, the target reconstruction code 310 to be tested is subjected to full-flow verification monitoring. The forefront of the target reconstruction code 310 to be measured is monitored by the monitor 320, the running process of the target reconstruction code 310 to be measured is monitored by the monitor 330, and the output of the target reconstruction code 310 to be measured is monitored by the monitor 340.
The realization of the process monitoring technology is that the accompanying monitoring function is added in the verification test code, important internal signals are copied and monitored, meanwhile, the signals are led out through pins of the FPGA, and the signals are transmitted from the test board to the main control FPGA board through the pins for collection.
The time recording module 224 is introduced to acquire the complete reconstruction time, the reconstruction interval and the like for calculation by setting the start-end register signal while monitoring the target to be measured in real time along with process monitoring. The problem of complete simulation reconstruction time detection is accurately solved.
The application of the drive scheduling module 222 greatly solves the flexible control of verification test drive excitation, and dynamically adjusts and changes the drive scheduling module to realize excitation generation and function requirements of strong fitting degree according to the actual functions of the reconfigurable FPGA software and the required verification test points.
The verification function layer module 230 may include an input agent module 231, a model replication module 232, a result record comparison module 233, an output agent module 234, etc., which can process things such as comparing the output result of the object code under test DUT with the processing result of the verification platform using the necessary abstract layer things. The verification function layer module 230 integrates a driving module, a monitoring module, a sequence scheduling module and the like in the verification instruction layer module 220, and simultaneously introduces a comparison module and a model reference library concept.
In the dedicated verification test system 200 of reconfigurable FPGA software of the present invention, the input agent module 231 and the output agent module 234 may be regarded as one factory. Wherein the input agent module 231 is used as an integration of the driving module, the monitoring module and the driving scheduling module in the verification instruction layer. The input agent module 231 can generate and distribute reasonable tasks, and the directional control monitoring module starts to monitor the input and works together with the driving and dispatching module; meanwhile, the agent module 231 is used for integration, and needs to control whether to generate the driving schedule, how to generate the driving schedule and what driving is generated for overall control. The output agent module 234 can sort and integrate the data acquired by the output detection monitoring module, and control the output detection monitoring module.
FIG. 4 shows a schematic block diagram of an implementation of a model reference and result comparison module in a verification function layer module in accordance with one embodiment of the invention. As shown in fig. 4, the model reference library 410 is used to perform a secondary validation verification test on the copied target reconstruction code 430 to be tested by using input signal excitation, and the result is compared with the result of the actual target test code through the output monitor by the result comparison module 420, so as to ensure that no sporadic test result error is introduced in the verification process, and meanwhile, the situation that the verification error is considered to be correct or reached for a certain action or function is avoided, but the situation that no problem exists is not proved. In particular, the implementation form of the reconfigurable FPGA software needs to carry out multiple verification on the reconfiguration data, the reconfiguration process data, the continuity verification, the integrity of the reconfiguration program and the correctness of the reconfiguration program, and plays a role in guaranteeing the correctness of the reconfiguration program read-in verification function layer with large data volume.
Meanwhile, the model copying module and the result recording and comparing module can be used for automatically verifying the testing process, actively and automatically comparing the result, recording and comparing results for automatic testing, and greatly reducing manual repeated labor and realizing high-accuracy comparison.
The verification environment layer module 240 requires that all derived categories need to be from its own scenes, and all scene uses need only be registered in the environment layer for use, and need not be redefined and then used. The method has the advantages that the method is convenient to call, plays a good management role, and can quickly set up added scenes.
FIG. 5 illustrates a verification test point profile for a reconfigurable code implementation in a verification environment in accordance with one embodiment of the invention. As shown in fig. 5, the application scenario added in the environment layer module 240 includes a conventional reconfiguration function verification environment library 510, a reconfiguration test code environment library 520, and a reconfiguration trace code environment library 530. The conventional reconfiguration function verification environment library 510 contains conventional verification means, and can be developed for reconfigurable FPGA software according to sequential logic, including: normal input/output frame detection, abnormal or erroneous input frame detection, frame interval, and other conventional reconfigurable functions.
The reconfiguration test code environment library 520 and the reconfiguration tracking code environment library 530 contain corresponding function test programs for a plurality of currently mainly used implementation modes of FPGA reconfiguration software, and can also realize judgment of the integrity of the actual FPGA reconfiguration code by presetting a start register and an end register, detect the reconfiguration rate of the actual FPGA, and realize test compared with invisible information verified by common simulation. Thanks to the burning of the reconstruction tracking code, the fault occurrence point and the fault generation reason analysis can be rapidly positioned, and the FPGA reconstruction process can be tracked in a whole flow. Specifically, the reconfigurable test code environment library 520 performs the following verification on the reconfigurable FPGA software: correlation fault injection verification, reconstruction program correctness verification, reconstruction program integrity verification, reconstruction data verification correctness verification, and the like. The reconfigurable tracking code environment library 530 performs the following tests on the reconfigurable FPGA software: a reconfiguration failure recovery test, a system reconfiguration time test, a reconfiguration failure recovery test, and the like.
Of course, only adding the reconstructed test code environment library 520 and the reconstructed trace code environment library 530 does not allow the tester to intuitively and quickly find and locate the problem and solve the problem again. The implementation of a reconfigurable generic verification platform based largely on FPGA also requires the monitoring of the output results by means of a monitoring system we introduce, compared to the monitoring in conventional verification tests. The invention keeps the output result monitoring, adds the monitoring and tracking to the input result and the reconstruction process, and uses the monitor information to continuously pass the hardware test verification platform and return to the upper computer: inputting and outputting all-stage flow information in the process, and facilitating the manual quick and visual finding of the problem.
The verification top layer module 250 may define global top layer files, and restrict some global variables and configurations such as working modes of the target code DUT to be tested, so that different scenarios can be generated through different constraints, and also the test of the directional function test point of the target code DUT to be tested can be realized, and also the randomized verification of the target code DUT to be tested can be realized through random scenario change.
The special verification test system based on the on-board on-orbit reconfigurable FPGA software is provided above by combining with fig. 2 to 5, and comprises 5 layers, wherein the layers are set up in a modularized mode while the self-functional attribute is maintained, so that the system is flexibly coordinated without losing uniformity.
FIG. 6 shows a flow chart of a verification process for reconfigurable FPGA software according to one embodiment of the invention.
In the verification process of on-board on-orbit reconfigurable FPGA software by using the system disclosed by the invention, firstly, in step 610, targeted reconstruction verification test excitation is required to be called from a reconstruction verification test environment library according to task requirements and target codes, and is used for selecting excitation driving sending sequences in an excitation driving dispatching model, and meanwhile, conventional detection of input excitation and output excitation is erected. In step 620, when the verification test starts, the preset verification process monitoring and time recording model starts to work, and the two models work cooperatively to monitor the reconstruction target code in real time and extract time information, so as to monitor the time axis of each reconstruction process and process conveniently, and calculate the actual reconstruction time and the reconstruction interval. In step 630, the target code is repeatedly verified for the second time by the model replication function module, when the target reconstruction code acts, the model replication function module acts simultaneously, and the generated result is automatically compared with the result generated by the actual DUT module by the record comparison module, so that the blind spot of the accidental verification problem is avoided efficiently.
The reconfigurable function is realized by mainly using virtexII and IV of Xilinx on the current satellite, but in consideration of the future selection of other chips and the generation of new verification requirements generated according to new reconstruction realization forms, the verification environment layer erected by the system is relatively open, and other environment libraries such as a reconstruction verification test environment library, a reconstruction tracking environment library and the like can be added at any time for expansion. The extended content can conveniently act on other layers below.
The verification top layer is relatively fixed and is used for defining global top layer files, and meanwhile, some global variables, the working modes of the DUT and other configurations are restrained, so that different scenes can be generated through different constraints, the test of the directional function test point of the DUT can be realized, and the randomized verification of the DUT can be realized through random scene change.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (9)
1. A method for process monitoring of reconfigurable FPGA software, characterized by:
the special verification test system utilizing the reconfigurable FPGA software is used for leading out important internal signals through FPGA pins while carrying out copying monitoring on the important internal signals, and transmitting the important internal signals from a test board to a main control FPGA board through the FPGA pins for collection;
the special verification test system of the reconfigurable FPGA software comprises:
the signal transmission layer module provides direct signal interconnection with the reconfigurable FPGA software to be tested and is accessed by other modules of the special verification test system;
the verification instruction layer module is used for monitoring the foremost input and the foremost output of the target reconstruction code to be detected of the reconfigurable FPGA software and also monitoring the running process of the target reconstruction code to be detected;
the verification function layer module compares the output result of the target reconstruction code to be tested with the processing result of the verification platform;
the verification environment layer module registers the scene use in the environment layer; and
A verification top layer module, which defines a global top layer file and constrains the working modes of global variables and target reconstruction codes to be tested,
wherein the verification instruction layer module comprises:
the one or more detection monitoring modules monitor the foremost input and the endmost output of the target reconstruction code to be detected of the reconfigurable FPGA software;
the driving generation module is used for driving and generating the most direct excitation input serving as the target reconstruction code to be tested, so that the driving excitation is ensured to be correctly and completely applied to the target reconstruction code to be tested;
the driving scheduling module is an upper layer cooperation module of the driving generation module and is used for dynamically adjusting and changing the driving scheduling module;
the process monitoring module is used for monitoring the operation process of the target reconstruction code to be detected;
and the time recording module is used for carrying out real-time monitoring on the target reconstruction code to be detected along with the process monitoring module, and acquiring complete reconstruction time and reconstruction interval by setting a start register signal and an end register signal.
2. The method of process monitoring of reconfigurable FPGA software of claim 1, wherein the verification function layer module comprises an input agent module and an output agent module.
3. The method of process monitoring of reconfigurable FPGA software of claim 2, wherein the input agent module controls when the detection monitoring module begins monitoring inputs and when the co-drive generation module and the drive scheduling module work together.
4. A method of process monitoring reconfigurable FPGA software as in claim 3 wherein the output proxy module collates and integrates data acquired by the output test monitor module and controls the output test monitor module.
5. The method of process monitoring of reconfigurable FPGA software of claim 2, wherein the verification function layer module comprises: and the comparison module and the model reference library are used for carrying out secondary confirmation verification test on the copy target code by using input signal excitation through the model reference library, and comparing the result with the result of the actual target test code through the output monitor through the comparison module.
6. The method of process monitoring of reconfigurable FPGA software of claim 1, wherein the verification environment layer module comprises a conventional reconfiguration function verification environment library, a reconfiguration test code environment library, and a reconfiguration trace code environment library.
7. The method of process monitoring of reconfigurable FPGA software of claim 6, wherein the reconfigurable test code environment library validates the reconfigurable FPGA software by: and (5) relevant fault injection verification, reconstruction program correctness verification, reconstruction program integrity verification and reconstruction data verification correctness verification.
8. The method of process monitoring of reconfigurable FPGA software of claim 6, wherein the reconfigurable trace code environment library performs the following tests on the reconfigurable FPGA software: and (5) testing the reconstruction failure recovery and the system reconstruction time.
9. The method for process monitoring of reconfigurable FPGA software of claim 1, wherein the verification top layer module generates different scenes by different constraints, and realizes the test of the directional function test point of the object to be tested reconfiguration code or realizes the randomized verification of the object to be tested reconfiguration code by random scene change.
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| CN202110759404.9A CN113392025B (en) | 2018-03-14 | 2018-03-14 | Method for monitoring process of reconfigurable FPGA software |
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| CN201810208126.6A CN108388516B (en) | 2018-03-14 | 2018-03-14 | Special verification test system capable of reconstructing FPGA software |
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| CN109508288B (en) * | 2018-10-22 | 2022-04-01 | 暨南大学 | Model detection method, device and storage medium |
| CN109492272A (en) * | 2018-10-22 | 2019-03-19 | 暨南大学 | A kind of modeling of restructural timing network conditionevent system and verification method and system |
| CN109344086B (en) * | 2018-11-15 | 2021-09-17 | 天津津航计算技术研究所 | Software testing platform based on SIP chip |
| CN109884517B (en) * | 2019-03-21 | 2021-04-30 | 浪潮商用机器有限公司 | Chip to be tested and test system |
| CN110321280B (en) * | 2019-05-22 | 2022-03-22 | 梁俊杰 | Data processing method and related equipment |
| CN111965447B (en) * | 2020-07-22 | 2022-10-18 | 电子科技大学 | Hardware configurable analog signal comprehensive test system |
| CN111880983B (en) * | 2020-08-04 | 2021-12-14 | 北京天融信网络安全技术有限公司 | CAN bus abnormality detection method and device |
| CN112596966B (en) * | 2020-12-17 | 2022-11-01 | 海光信息技术股份有限公司 | Chip verification method, device, equipment and storage medium |
| CN114003495A (en) * | 2021-10-29 | 2022-02-01 | 四川虹美智能科技有限公司 | Android application reconstruction method and device of unmanned vending cabinet and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104077204A (en) * | 2014-07-22 | 2014-10-01 | 无锡中微爱芯电子有限公司 | Reconfigurable 8-bit RSIC (reduced instruction set computer) SCM (Single Chip Microcomputer) simulator |
| CN106407516A (en) * | 2016-08-31 | 2017-02-15 | 北京中电华大电子设计有限责任公司 | Verification method for parallel verification |
| CN107423505A (en) * | 2017-07-21 | 2017-12-01 | 山东华芯半导体有限公司 | A kind of reusable checking system of module level and SoC level and verification method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6542844B1 (en) * | 2000-08-02 | 2003-04-01 | International Business Machines Corporation | Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits |
| KR100921314B1 (en) * | 2004-07-12 | 2009-10-13 | 양세양 | High Performance Design Verification Apparatus Using Verification Results Re-use Technique and Its Rapid Verification Method Using the Same |
| US7302625B1 (en) * | 2005-11-21 | 2007-11-27 | Xilinx, Inc. | Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration |
| CN104142876A (en) * | 2013-05-06 | 2014-11-12 | 上海华虹集成电路有限责任公司 | Function verification method and verification environmental platform for USB (universal serial bus) equipment controller modules |
| JP2018530040A (en) * | 2015-07-31 | 2018-10-11 | 呉 国盛ＷＵ， Ｇｕｏｓｈｅｎｇ | Self-adaptive chip and placement method |
-
2018
- 2018-03-14 CN CN201810208126.6A patent/CN108388516B/en active Active
- 2018-03-14 CN CN202110759404.9A patent/CN113392025B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104077204A (en) * | 2014-07-22 | 2014-10-01 | 无锡中微爱芯电子有限公司 | Reconfigurable 8-bit RSIC (reduced instruction set computer) SCM (Single Chip Microcomputer) simulator |
| CN106407516A (en) * | 2016-08-31 | 2017-02-15 | 北京中电华大电子设计有限责任公司 | Verification method for parallel verification |
| CN107423505A (en) * | 2017-07-21 | 2017-12-01 | 山东华芯半导体有限公司 | A kind of reusable checking system of module level and SoC level and verification method |
Non-Patent Citations (1)
| Title |
|---|
| 基于VMM的FPGA软件可重用验证平台;刘宪忠;于天民;黄志国;;自动化技术与应用(第12期);全文 * |
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| CN108388516A (en) | 2018-08-10 |
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