CN113381396A - Circuit and power chip for input voltage abrupt change turn-off output - Google Patents

Circuit and power chip for input voltage abrupt change turn-off output Download PDF

Info

Publication number
CN113381396A
CN113381396A CN202110786929.1A CN202110786929A CN113381396A CN 113381396 A CN113381396 A CN 113381396A CN 202110786929 A CN202110786929 A CN 202110786929A CN 113381396 A CN113381396 A CN 113381396A
Authority
CN
China
Prior art keywords
voltage
outputs
output
input
input voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110786929.1A
Other languages
Chinese (zh)
Other versions
CN113381396B (en
Inventor
许锦龙
李瑞平
池伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Original Assignee
Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch filed Critical Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Priority to CN202110786929.1A priority Critical patent/CN113381396B/en
Publication of CN113381396A publication Critical patent/CN113381396A/en
Application granted granted Critical
Publication of CN113381396B publication Critical patent/CN113381396B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/006—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of too high or too low voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a circuit and a power chip for switching off output when input voltage suddenly changes, which comprises: the system comprises an input voltage slope detection module, a shutdown signal generation module, a shutdown signal holding module and a system shutdown module, wherein the input voltage slope detection module outputs a first voltage after receiving an input voltage, the shutdown signal generation module receives the first voltage and outputs a fourth voltage, the shutdown signal holding module outputs a seventh voltage after receiving the fourth voltage, and the system shutdown module receives the seventh voltage and outputs an eighth voltage; and when the fourth voltage is at a high level, the seventh voltage is also at a high level, and the seventh voltage controls the field effect transistor in the system shutdown module to be switched on so as to enable the eighth voltage to be reduced to zero volts, thereby controlling the power tube in the power supply chip to be switched off. The invention judges whether to close the power chip or not by detecting the fluctuation condition of the voltage at the input end of the power chip, thereby preventing the output voltage of the system from being unstable and causing the damage of the rear-stage load.

Description

Circuit and power chip for input voltage abrupt change turn-off output
Technical Field
The invention relates to the technical field of switching power supplies, in particular to a circuit and a power supply chip for switching off output when input voltage suddenly changes.
Background
In the application process of the DC-DC power supply, the power is often powered up by using a mechanical switch, hot plugging and the like, and in the process: on one hand, the voltage of the input end of the DC-DC power supply chip can be raised in a step mode, and if the DC-DC power supply chip is not well processed, output overshoot is easy to generate; on the other hand, if the switch or the like is in poor contact, the voltage at the input end can rapidly rise and then rapidly fall for a plurality of times, so that the normal operation of the chip is seriously disturbed, and the DC-DC power supply chip can generate very serious overshoot even a rear-stage circuit is damaged if the DC-DC power supply chip is improperly processed.
The existing power supply system usually avoids output overshoot by a soft start mode, that is, the output voltage and current are slowly established, but this method only aims at the condition that the input voltage normally rises, such as the voltage slowly rises or the voltage steps rises, but has no particularly good effect on the problem of poor contact.
Disclosure of Invention
The invention aims to solve the problems of unstable work and overshoot of output of a DC-DC power supply chip when the input end is in poor contact or is electrified in a step mode.
In order to solve the technical problems, the invention provides a circuit for switching off output by sudden change of input voltage and a power chip, wherein the circuit is characterized in that the power tube in the power chip is controlled to stop working when the input voltage has severe fluctuation by detecting the fluctuation of the input voltage of the power chip, and the power tube is delayed for a certain time to restart after the fluctuation stops, so that the power tube does not work when the input voltage of the power chip is unstable, and the power tube restarts working after the input voltage is stable, thereby avoiding the problems of output overshoot and the like generated under the condition and ensuring the stable working of a system.
The invention provides a circuit for switching off output of input voltage abrupt change, which comprises:
the input voltage slope detection module comprises an operational amplifier, wherein the non-inverting end of the operational amplifier is connected with a first reference voltage, the inverting end of the operational amplifier is connected with the input voltage of the power supply chip through a second capacitor and then outputs a first voltage, and the inverting end and the output end are connected and connected in series with a first resistor;
the shutdown signal generation module comprises a first comparator and a second comparator, wherein the first comparator outputs a second voltage after receiving a second reference voltage and a first voltage, the second comparator outputs a third voltage after receiving a third reference voltage and the first voltage, and the second voltage and the third voltage output a fourth voltage through an OR gate;
the system shutdown module comprises a transconductance amplifier and a third field effect transistor, wherein the output end of the transconductance amplifier is connected with the drain electrode of the third field effect transistor, the source electrode of the third field effect transistor is grounded, the transconductance amplifier receives a reference voltage and a feedback voltage of a voltage feedback pin of a power chip and generates an eighth voltage for controlling the on-off of a power tube in the power chip through a frequency compensation circuit, and when a fourth voltage is at a high level, the third field effect transistor is switched on, and the eighth voltage is zero volt;
the higher the eighth voltage is, the larger the conduction duty cycle of the power tube is, the higher the output energy is, and when the eighth voltage is zero volt, the power tube is turned off.
As a further improvement, the circuit further includes a shutdown signal holding module, where the shutdown signal holding module includes a flip-flop and a phase inverter, the fourth voltage is connected to the set end of the flip-flop and the input end of the phase inverter, the phase inverter receives the fourth voltage and outputs an opposite voltage signal to the reset end of the flip-flop, the output end of the flip-flop outputs a seventh voltage, and the output end of the flip-flop is connected to the gate of the third fet.
As a further improvement, the voltage at the input end of the power supply chip is connected with a first capacitor after being stabilized, and the first capacitor is used for ensuring that an internal circuit of the power supply chip can still normally work when the input voltage is severely changed, so that the voltage stabilization effect is achieved.
As a further improvement, when the input voltage rises and the first voltage is smaller than the first reference voltage, the faster the input voltage rises, the lower the first voltage; when the input voltage drops and the first voltage is greater than the first reference voltage, the faster the input voltage drops, the higher the first voltage.
As a further improvement, the degree of deviation of the first voltage from the first reference voltage reflects the slope of the rise or fall of the input voltage, and a fourth voltage signal that can reflect the slope of the input voltage is output by comparing the first voltage with the second reference voltage and the third reference voltage.
As a further improvement, the third reference voltage is higher than the first reference voltage, and the first reference voltage is higher than the second reference voltage, preferably, the third reference voltage is slightly higher than the first reference voltage, and the first reference voltage is slightly higher than the second reference voltage.
As a further improvement, when the input voltage rises, and the slope of the input voltage is: dVIN/dt > (VREF1-VREF2)/(R1 × C2), wherein: VREF1 and VREF2 are respectively the voltage value of the first reference voltage and the voltage value of the second reference voltage, R1 is the first resistance value, and C2 is the second capacitance, then the power chip is turned off.
When the input voltage is reduced, if the first voltage is greater than the third reference voltage, the third voltage outputs a high level, the slope of the reduction of the input voltage is overlarge, and if the first voltage is less than the third reference voltage, the third voltage outputs a low level.
When the input voltage drops, and the slope of the input voltage is:
and dVIN/dt < (VREF1-VREF 3)/(R1. C2), wherein VREF1 and VREF3 are respectively the voltage value of the first reference voltage and the voltage value of the third reference voltage, R1 is a first resistance value, and C2 is the capacity of the second capacitor, so that the power chip is shut down.
When at least one of the second voltage and the third voltage is at a high level, the fourth voltage outputs a high level, otherwise, the fourth voltage outputs a low level; when the fourth voltage is at a high level, the slope of the rise or fall of the input voltage is too large.
When the fourth voltage outputs a high level, the sixth voltage outputs a low level, the seventh voltage outputs a high level, and at the moment, the power tube in the power supply chip is turned off, otherwise, the power tube is turned on.
As a further improvement, the shutdown signal holding module includes a delay unit, a third comparator and a trigger, the fourth voltage is converted by the delay unit in a delay manner and then outputs a fifth voltage, the third comparator receives the fifth voltage and a reference voltage and then outputs a sixth voltage, a set end and a reset end of the trigger respectively receive the fourth voltage and the sixth voltage and then output a seventh voltage through an output end, and the seventh voltage is connected to a gate of the third field effect transistor;
when the fourth voltage is changed from a high level to a low level, the constant current source charges the third capacitor through the first field effect transistor, the delay unit outputs the high level to the sixth voltage after a delay time, and the shutdown signal is removed; wherein the delay time is a time when the fifth voltage rises from zero volts to the reference voltage.
As a further improvement, the delay unit includes a phase inverter composed of a first field effect transistor and a second field effect transistor, a third capacitor, and a constant current source, wherein a source electrode of the first field effect transistor is connected to the constant current source, gate electrodes of the first field effect transistor and the second field effect transistor are connected to each other and receive a fourth voltage, the second field effect transistor is connected to a drain electrode of the first field effect transistor and connected to one electrode of the third capacitor, and a source electrode of the second field effect transistor and the other electrode of the third capacitor are grounded.
A second aspect of the present invention provides a power supply chip having the circuit for abruptly switching off an output of an input voltage provided by the first aspect of the present invention.
As a further improvement, the power supply chip further comprises a voltage stabilizing source, a reference voltage source, a sawtooth skin generating module, a PWM generating module, a power tube driving module and a power tube.
When the seventh voltage is high level, the third field effect transistor is switched on, the eighth voltage is short-circuited, and the power tube is switched off to play a role in shutdown.
The invention judges whether to close the power chip or not by detecting the fluctuation condition of the voltage at the input end of the power chip, thereby preventing the output voltage of the system from being unstable and causing the damage of the rear-stage load.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
Fig. 1 is a schematic circuit diagram of an embodiment of the circuit of the present invention.
Fig. 2 is a schematic circuit diagram of another embodiment of the circuit of the present invention.
Fig. 3 is a schematic diagram of an embodiment of a power chip according to the invention.
Fig. 4 is a schematic connection diagram of the power supply chip of the present invention applied to a power supply system.
Fig. 5 is a voltage waveform diagram of the input voltage, the first voltage, the fourth voltage, and the seventh voltage according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that VIN is the input voltage, VDD is the internal power supply voltage, and the voltage is the voltage of VIN regulated by the voltage regulation module in the following embodimentsAnd obtaining VREF, wherein VREF is the internal reference voltage of the power chip, VREF1, VREF2 and VREF3 are obtained by resistance voltage division of VREF voltage and are used for providing a reference voltage source for a circuit, the VREF voltage is greater than VREF1, VREF2 and VREF3, VFB voltage is the feedback voltage of the FB pin of the power chip, generally, the output voltage of the power system is obtained by methods of resistance voltage division and the like, and I is the internal reference voltage of the power chipC2Is the current through the second capacitor C2.
As shown in fig. 1, a circuit for abruptly switching off an output of an input voltage includes:
the input voltage slope detection module 100 comprises an operational amplifier OP1, wherein the non-inverting input end of the operational amplifier OP1 is connected with a first reference voltage VREF1, the inverting input end of the operational amplifier is connected with the input voltage VIN of a power chip through a second capacitor C2 and then outputs a first voltage V1, and a first resistor R1 is connected between the inverting input end and the output end in series;
the shutdown signal generating module 200 comprises a first comparator COMP1 and a second comparator COMP2, wherein the first comparator COMP1 outputs a second voltage V2 after receiving a second reference voltage VREF2 and a first voltage V1, the second comparator COMP2 outputs a third voltage V3 after receiving a third reference voltage VREF3 and the first voltage V1, and the second voltage V2 and the third voltage V3 output a fourth voltage V4 through an OR gate OR 1;
the system shutdown module 400 comprises a transconductance amplifier OTA1 and a third field effect transistor M3, wherein the output end of the transconductance amplifier OTA1 is connected with the drain electrode of the third field effect transistor M2, the gate electrode of the third field effect transistor M3 receives a fourth voltage V4, the source electrode of the third field effect transistor M3 is grounded, the transconductance amplifier OTA1 receives a reference voltage VREF and a feedback voltage (namely, a VFB voltage) of a FB pin of a power chip and then generates an eighth voltage V8 for controlling the power tube in the power chip to be switched on and off through a frequency compensation circuit, when the fourth voltage is at a high level, the third field effect transistor M3 is switched on, and at this time, the eighth voltage is zero volt;
the higher the eighth voltage V8 is, the larger the on duty ratio of the power tube is, the higher the output energy is, and when the eighth voltage V8 is zero volts, the power tube is turned off.
The input voltage VIN is stabilized by the voltage stabilizing module to obtain an internal power supply voltage VDD, a first capacitor C1 is connected in series between the input voltage VIN and the internal power supply voltage VDD, as shown in fig. 4, the first capacitor C1 is connected in parallel between a VDD pin and a GND pin of the power chip.
The second capacitor C2, the first resistor R1 and the operational amplifier OP1 form a simple differential circuit, the differential circuit can detect the change slope of the input voltage VIN in real time, when the slope of the VIN voltage rising or falling changes, the output voltage of the operational amplifier OP1 changes, and the current I of the second capacitor C2 changesC2The flow direction is shown in FIG. 1, current IC2= C2 × dVIN/dt, the first voltage V1 is calculated as formula (1): v1= VREF 1-R1C 2 dVIN/dt.
In the above formula (1), VREF1 is the voltage value of the first reference voltage VREF1, R1 is the resistance of the first resistor, C2 is the capacitance of the second capacitor C2, and dVIN/dt is the rate of increase or decrease of the VIN voltage as a function of the change of the VIN voltage with time t.
As can be seen from the formula (1), when VIN rises, the first voltage V1 is smaller than the first reference voltage VREF1, and the faster VIN rises, the lower the value of the first voltage V1; when VIN decreases, the first voltage V1 is greater than the first reference voltage VREF1, and the faster VIN decreases, the higher the value of the first voltage V1 is; the degree to which the first voltage V1 deviates from the first reference voltage VREF1 may reflect the slope of the increase or decrease in the VIN voltage.
A non-inverting input terminal of the first comparator COMP1 receives a second reference voltage VREF2, and an inverting input terminal of the first comparator COMP1 receives a first voltage V1 and outputs a second voltage V2; the non-inverting input terminal of the second comparator COMP2 receives the first voltage V1, the inverting input terminal receives the third reference voltage VREF3 and outputs a third voltage V3, and the second voltage V2 and the third voltage V3 output a fourth voltage V4 through an OR gate OR 1.
The second reference voltage VREF2 is slightly lower than the first reference voltage VREF1, for example, the second reference voltage VREF2 is 0.2V lower than the first reference voltage VREF1, and in some embodiments, the second reference voltage VREF2 is 0.1V-0.2V lower than the first reference voltage VREF 1.
The third reference voltage VREF3 is slightly higher than the first reference voltage VREF1, for example, the third reference voltage VREF3 is 0.2V higher than the first reference voltage VREF1, and in some embodiments, the third reference voltage VREF3 is 0.1-0.2V higher than the first reference voltage VREF 1.
It can be seen that the third reference voltage VREF3 is greater than the first reference voltage VREF1, the first reference voltage VREF1 is greater than the second reference voltage VREF2, and the voltage values of the first reference voltage VREF1, the second reference voltage VREF2 and the third reference voltage VREF3 can be set according to actual requirements.
When the input voltage VIN rises, the first voltage V1 is smaller than the second reference voltage VREF2, and the second voltage V2 outputs a high level, at this time, it can be considered that the slope of the rise of the input voltage VIN is too large, and the first voltage V1 is smaller than the second reference voltage VREF2, and the second voltage V2 outputs a low level.
The conditions for the second voltage V2 to output a high level are: VREF2> V1= VREF1-R1 × C2 × dVIN/dt.
Therefore, when the input voltage VIN rises, the slope of the input voltage is: dVIN/dt > (VREF1-VREF2)/(R1 × C2), the power chip is turned off, wherein: VREF1 and VREF2 are respectively a voltage value of the first reference voltage and a voltage value of the second reference voltage, R1 is a first resistance value, and C2 is a second capacitance; when the input voltage VIN drops and the first voltage V1 is greater than the first reference voltage VREF1, if the first voltage V1 is greater than the third reference voltage VREF3 at the same time, the third voltage V3 outputs a high level, at which it can be considered that the slope of the drop of the input voltage VIN is too large, and when the first voltage V1 is less than the third reference voltage VREF3, the third voltage V3 outputs a low level.
The condition that the third voltage V3 outputs a high level is: VREF3< V1= VREF1-R1 × C2 × dVIN/dt, and it is thus found that, when the input voltage VIN decreases, the slope of the input voltage is: dVIN/dt < (VREF1-VREF3)/(R1 × C2), the power chip is turned off, wherein: VREF1, VREF2, VREF3 are the voltage value of the first reference voltage, the voltage value of the second reference voltage, and the voltage value of the third reference voltage, respectively, R1 is the first resistance value, C2 is the second capacitance, and dVIN/dt is a negative value when the input voltage decreases.
When at least one of the second voltage V2 and the third voltage V3 is at a high level, the fourth voltage V4 outputs a high level, otherwise, outputs a low level, and when the fourth voltage V4 output by the shutdown signal generation module 200 is at a high level, it indicates that the slope of the rise or fall of the input voltage VIN is too large.
As shown in fig. 2, the circuit for abruptly turning off the output of the input voltage further includes a shutdown signal holding module 300, which includes a flip-flop SREF1, a delay unit, and a third comparator COMP3, where the fourth voltage V4 is converted by the delay unit in a delay manner to output a fifth voltage V5, the third comparator COMP3 receives the fifth voltage V5 and the reference voltage VREF and outputs a sixth voltage V6, and a set end, i.e., an S end and a reset end, i.e., an R end, of the flip-flop respectively receive the fourth voltage V4 and the sixth voltage V6 and output a seventh voltage V7.
When the shutdown signal holding module 300 is provided, the seventh voltage output by the flip-flop is connected to the gate of the third fet M3, and when the fourth voltage V4 is at a high level, the seventh voltage V7 is also at a high level, and the third fet M3 is turned on.
The delay unit comprises a first field effect transistor M1, a second field effect transistor M2, a third capacitor C3 and a constant current source IS1, wherein the source electrode of the first field effect transistor M1 IS connected with the constant current source IS1, the grid electrodes of the first field effect transistor M1 and the second field effect transistor M2 are connected with each other and receive a fourth voltage V4, a second field effect transistor M2 IS connected with the drain electrode of the first field effect transistor M1 and connected with one electrode of the third capacitor C3, the source electrode of the second field effect transistor M2 and the other electrode of the third capacitor C3 are grounded, and the first field effect transistor M1 and the second field effect transistor M2 form an inverter.
In some embodiments, the first fet M1 is a pmos transistor and the second fet M2 is an nmos transistor.
When the fourth voltage V4 is at a high level, the first fet M1 is turned off, the second fet M2 is turned on, and the third capacitor C3 discharges through the second fet M2, so that the voltage of the third capacitor C3 can be instantaneously discharged to zero volts because the capacitance of the third capacitor C3 is small.
When the fourth voltage V4 goes low, the first fet M1 IS turned on, the second fet M2 IS turned off, and the constant current source IS1 charges the third capacitor C3 through the first fet M1, and the fifth voltage V5 across the third capacitor C3 IS calculated by equation (2): v5= IS1 × t/C3, where IS1 IS the current value provided by the constant current source, C3 IS the capacity of the third capacitor C3, and t IS the charging time.
As can be seen from the above equation (2), the fifth voltage V5 rises with time, and when the fifth voltage V5 rises to be greater than the reference voltage VREF, the sixth voltage V6 outputs a high level, and since the fourth voltage V4 has changed from the high level to the low level, the time T equation (3) when the fifth voltage V5 changes from the low level to the high level is: t = C3 × VREF/IS1, where C3 IS the capacity of the third capacitance, VREF IS the voltage value of the reference voltage, IS1 IS the current value provided by the constant current source, which IS typically 1 uA.
By charging the third capacitor C3, the trigger performs different operations after the delay time T, so as to achieve the effect of time delay, and the input voltage VIN of the power supply chip is more stable and then works, thereby further improving the stability.
As an embodiment, the shutdown signal holding module 300 may not have a delay function, so that the fourth voltage V4 is still connected to the S terminal of the flip-flop, and when the fourth voltage V4 is at a high level, the output seventh voltage V7 is at a high level, and the shutdown of the power chip is correspondingly controlled. At this time, the non-inverting input terminal of the third comparator COMP3 may not be connected to the third capacitor C3, but directly connected to the drain of the nmos tube, and at this time, the drain of the first field effect transistor M1 is connected to the constant current source or the connection resistor, so that when the fourth voltage V4 is at a high level, the nmos tube is turned off, the output level of the third comparator COMP3 is still at a low level, and the seventh voltage V7 correspondingly outputs a high level, which correspondingly controls the power chip to turn off.
In other embodiments, the fourth voltage V4 may be directly connected to an inverter, an output terminal of the inverter is connected to an R terminal of the flip-flop, an inverted signal of the fourth voltage V4 is transmitted to the R terminal of the flip-flop through the inverter, when the fourth voltage V4 is high, the voltage at the R terminal is zero volts, and the seventh voltage V7 outputs high.
The specific implementation form of the inverter may be various, as long as the implementation is to output a voltage signal opposite to the fourth voltage so as to reset the flip-flop, for example, one path of the fourth voltage V4 may be connected to the S-terminal of the flip-flop, the other path may be connected to the R-terminal of the flip-flop through the not gate, and similarly, when the fourth voltage V4 is at a high level, the flip-flop outputs a shutdown signal; therefore, the power-off signal of the power supply chip can be output when the slope of the input voltage is larger without setting the delay unit.
Therefore, the shutdown signal holding module 300 may include only a flip-flop and an inverter, the fourth voltage is connected to the set end of the flip-flop and the input end of the inverter, the inverter receives the fourth voltage and outputs an opposite voltage signal to the reset end of the flip-flop, the output end of the flip-flop outputs a seventh voltage and is connected to the gate of the third fet, the seventh voltage controls the on/off of the third fet M3, and the eighth voltage V8 controls the on/off of the power transistor in the power chip.
In specific implementation, the inverter determines whether to perform a pull-up design according to requirements, and a description thereof is omitted.
The non-inverting input terminal of the third comparator COMP3 receives the fifth voltage V5 across the third voltage C3, the inverting input terminal receives the reference voltage VREF inside the chip, and the output terminal is connected to the R terminal of the flip-flop SRFF1, which is an RS flip-flop in some embodiments.
The truth table of the RS flip-flop is shown in table 1 below:
S R Q
1 0 1
0 1 0
0 0 holding the previous state
1 1 Illegal input
TABLE 1
In table 1 above: "1" represents high level, "0" represents low level, S, R, Q is the corresponding link of flip-flop, and S end, R end are the input, and Q is the output.
The seventh voltage V7 is a shutdown signal, and initially, the voltage at two ends of the third capacitor C3, that is, the fifth voltage V5, is zero volt, so the sixth voltage V6 is zero volt, and the seventh voltage V7 output by the Q end of the flip-flop SRFF1 is at a high level, that is, it indicates that the voltage fluctuation at the input end is large, and the power transistor needs to be shut down.
The transconductance amplifier OTA1 receives the VFB voltage and the reference voltage VREF of the power chip, amplifies the difference between the reference voltage VREF and the VFB voltage, and generates an eighth voltage V8 through the frequency compensation circuit, and the eighth voltage V8 generates a control signal of a power tube built in the power chip through other circuits to control the on/off of the power tube, so as to change the output voltage, so that the VFB voltage is close to the VREF voltage, thereby realizing the effect of stable output.
The higher the voltage of the eighth voltage V8, the larger the on duty ratio of the power tube, and the higher the output energy. When the eighth voltage V8 is zero volts, the power tube is not conducting.
When the seventh voltage V7 is at a high level, the slope of the input voltage is too high, and the seventh voltage V7 controls the third fet M3 to be turned on, so that the eighth voltage V8 is shorted to the ground, and the power tube in the power chip is not turned on, thereby performing the shutdown function. In addition, the eighth voltage V8 is shorted to ground, which corresponds to the power tube driving circuit restarting.
A power chip is provided with the circuit for switching off the output by sudden change of input voltage in the embodiment, and the power chip can be a boosting power chip or a step-down power chip.
As shown in fig. 3, when the circuit for switching off the output of the input voltage abrupt change is applied to a buck power supply chip, the output end of the transconductance amplifier OTA1 is connected to a PWM generating module, the PWM generating module receives an eighth voltage V8 and a sawtooth wave signal generated by the sawtooth wave generating module and then outputs the PWM signal to a power tube driving module, and the power tube driving module controls the power tube to be switched on and off.
As an embodiment, the voltage regulator and the reference voltage source in the power supply chip take power from the input voltage VIN to generate the voltage regulator VDD and the reference voltage VREF.
The FB pin of the power chip is a feedback pin, the VFB voltage in fig. 1 and 2 is a feedback voltage from the FB pin of the power chip, and the VIN pin is an input voltage pin for connecting to an input of the system.
The DV SET pin of the power chip is a setting pin for the maximum slope of the input voltage VIN, and a second capacitor C2 is connected between the DV SET pin and the VIN pin in parallel and used for detecting the rising or falling slope of the input voltage VIN.
As shown in fig. 4, a power supply system has the power supply chip described in the above embodiment, the VDD pin of the power supply chip is connected to the first capacitor C1, the DV SET pin is connected to the second capacitor C2, the SW pin is the output terminal pin of the power tube and is connected to the first inductor L1 and one end of the first diode D1, other connection portions in fig. 4 are the conventional connections of the conventional buck chip circuit, such as the voltage dividing resistors RB and RT and the capacitor CFF on the FB pin, the capacitor C0 and the capacitor C5 connected to one end of the first inductor L1, and the capacitors CIN and C4 connected in parallel between the VIN pin and the GND pin, and so on, and the invention will not be further described.
As shown in fig. 5, fig. 5 shares four portions, i.e., the first portion, the second portion, the third portion, and the fourth portion from top to bottom, and the first reference voltage VREF1 is set to 0.4V, and the changes of the first voltage V1, the fourth voltage V4, and the seventh voltage V7 with the input voltage VIN will be described below.
The first part shows the fluctuation of the input voltage VIN, and when the input terminal has poor contact, the input voltage VIN will generate similar fluctuation, and fig. 5 is only a diagram, only for better explaining the present invention, and the actual power-on situation will be more complicated and varied.
The second part is the variation of the first voltage V1, when the input voltage VIN is stable, the first voltage V1 is equal to the first reference voltage VREF1, when the input voltage VIN rises, the first voltage V1 falls to be lower than 0.4V, when the input voltage VIN falls, the first voltage V1 rises to be higher than 0.4V; the faster the input voltage VIN rises or falls, the more the first voltage V1 deviates from 0.4V.
The third part is the variation of the fourth voltage V4, and when the first voltage V1 deviates from 0.4V to some extent, for example, the first voltage V1 is higher than 0.6V or the V1 is lower than 0.2V, the fourth voltage V4 outputs a high level. When the input voltage VIN decreases slowly or rises slowly, the fourth voltage V4 does not become high, and the fourth voltage V4 does not become high because the first decrease of the input voltage VIN in fig. 5 is relatively gentle.
The fourth part is the variation of the seventh voltage V7, the seventh voltage V7 is delayed from the fourth voltage V4, it can be seen from the figure that the pulse width of the seventh voltage V7 is greater than that of the fourth voltage V4, the delay time in fig. 5 is about 35us, i.e. the pulse width of the seventh voltage V7 is greater than that of the fourth voltage V4 by 35us, and this delay time is the time from charging the third capacitor C3 to the fifth voltage V5 reaching the reference voltage VREF from zero volts, and the implementation can be different according to the variation of the requirement, and generally speaking, the delay time is about 7 switching cycles for a switching frequency of 200 KHZ.
The invention judges whether to close the power chip or not by detecting the fluctuation condition of the voltage of the input end, thereby preventing the output of the power system from being unstable and causing the damage of the rear-stage load.
In the above embodiment, the reference voltage signals received at the input terminals of the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3 may be connected to the non-inverting input terminal or the inverting input terminal, and for those skilled in the art, modifications may be made on the basis of the present invention to obtain a shutdown signal generating module with the same function, so as to implement that when the input voltage rises or falls too fast, the fourth voltage V4 outputs a high-level signal.
It should be noted that, the first capacitor C1 has a larger capacity and is generally connected externally, and when the first capacitor C1 is externally connected, it may be regarded as a part of the input voltage slope detection module 100, and may also be regarded as being connected to the input voltage slope detection module 100; the second capacitor C2 can be integrated in the power chip or externally arranged, and when the second capacitor C2 is externally arranged, a user can conveniently set the capacity of the capacitor by himself, so that shutdown under the condition of different input voltage slopes can be realized.
For those skilled in the art, the above embodiments are not described in detail, and can be understood from the accompanying drawings, which do not affect the implementation of the present invention.
In the above embodiments, the components of each circuit or module may be replaced by circuits or modules with the same function, and the circuit structure that realizes the same function may also be replaced by other known circuit structures, and the present invention is not described in detail.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A circuit for abruptly switching off an output from an input voltage, comprising:
the input voltage slope detection module comprises an operational amplifier, wherein the in-phase end of the operational amplifier receives a first reference voltage, the inverting end of the operational amplifier outputs the first voltage after being connected with the input voltage of the power supply chip through a second capacitor, and the inverting end and the output end are connected and connected in series with a first resistor;
the shutdown signal generation module comprises a first comparator and a second comparator, wherein the first comparator outputs a second voltage after receiving a second reference voltage and a first voltage, the second comparator outputs a third voltage after receiving a third reference voltage and the first voltage, and the second voltage and the third voltage output a fourth voltage through an OR gate;
the system shutdown module comprises a transconductance amplifier and a third field effect transistor, wherein the output end of the transconductance amplifier is connected with the drain electrode of the third field effect transistor, the source electrode of the third field effect transistor is grounded, the transconductance amplifier receives a reference voltage and a feedback voltage of a voltage feedback pin of a power chip and generates an eighth voltage for controlling the on-off of a power tube in the power chip through a frequency compensation circuit, and when a fourth voltage is at a high level, the third field effect transistor is switched on, and the eighth voltage is zero volt;
the higher the eighth voltage is, the larger the conduction duty cycle of the power tube is, the higher the output energy is, and when the eighth voltage is zero volt, the power tube is turned off.
2. The circuit for input voltage abrupt turn-off output according to claim 1, further comprising a shutdown signal holding module, wherein the shutdown signal holding module comprises a flip-flop and an inverter, the fourth voltage is connected to the set terminal of the flip-flop and the input terminal of the inverter, the inverter receives the fourth voltage and outputs an opposite voltage signal to the reset terminal of the flip-flop, and the output terminal of the flip-flop outputs a seventh voltage and is connected to the gate of the third fet.
3. The input voltage abrupt turn-off output circuit according to claim 1 or 2, wherein the faster the input voltage rises and the first voltage is less than the first reference voltage, the lower the first voltage; when the input voltage drops and the first voltage is greater than the first reference voltage, the faster the input voltage drops, the higher the first voltage.
4. The circuit for turning off the output of the input voltage abruptly as claimed in claim 3, wherein when the input voltage rises and the first voltage is less than the second reference voltage, the second voltage outputs a high level, and the slope of the rise of the input voltage is too large;
when the input voltage rises, and the slope of the input voltage is: dVIN/dt > (VREF1-VREF2)/(R1 × C2), wherein: VREF1 and VREF2 are respectively a first reference voltage value and a second reference voltage value, R1 is a first resistance value, and C2 is a second capacitance capacity, then the power chip is turned off;
when the input voltage is reduced and the first voltage is greater than the third reference voltage, the third voltage outputs a high level, and the slope of the reduction of the input voltage is overlarge;
when the input voltage drops, and the slope of the input voltage is: and dVIN/dt < (VREF1-VREF 3)/(R1. C2), wherein VREF1 and VREF3 are respectively a first reference voltage value and a third reference voltage value, R1 is a first resistance value, and C2 is the capacity of a second capacitor, so that the power chip is shut down.
5. The input voltage abrupt change turn-off output circuit of claim 1, further comprising a shutdown signal holding module, wherein the shutdown signal holding module comprises a delay unit, a third comparator and a trigger, the fourth voltage is converted by the delay unit in a delayed manner and outputs a fifth voltage, the third comparator receives the fifth voltage and a reference voltage and outputs a sixth voltage, a set end and a reset end of the trigger respectively receive the fourth voltage and the sixth voltage and output a seventh voltage through an output end, and the seventh voltage is connected to a gate of the third field effect transistor.
6. The circuit of claim 5, wherein the delay unit comprises an inverter formed by a first field effect transistor and a second field effect transistor, a third capacitor, and a constant current source, wherein a source of the first field effect transistor is connected to the constant current source, gates of the first field effect transistor and the second field effect transistor are connected to receive a fourth voltage, the second field effect transistor is connected to a drain of the first field effect transistor and to one pole of the third capacitor, and a source of the second field effect transistor and the other pole of the third capacitor are grounded.
7. The circuit for turning off the output by sudden change of the input voltage according to claim 6, wherein when the fourth voltage changes from high level to low level, the constant current source charges the third capacitor through the first field effect transistor, the delay unit outputs the sixth voltage at high level after a delay time, and the shutdown signal is released;
the delay time is the time for the fifth voltage to rise from zero volts to the reference voltage.
8. The circuit of claim 5, wherein when the fourth voltage outputs a high level, the sixth voltage outputs a low level, the seventh voltage outputs a high level, the third FET is turned on, the eighth voltage is shorted to ground, and the power transistor in the power chip is turned off.
9. The circuit for switching off the output of an input voltage abruptly according to any one of claims 1, 2 and 4 to 8, wherein when at least one of the second voltage and the third voltage is at a high level, the fourth voltage outputs a high level, and otherwise the fourth voltage outputs a low level; when the fourth voltage is at a high level, the slope of the rise or fall of the input voltage is too large.
10. A power supply chip having the circuit for turning off an output by abrupt input voltage change of any one of claims 1 to 9.
CN202110786929.1A 2021-07-13 2021-07-13 Circuit and power chip for input voltage abrupt change turn-off output Active CN113381396B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110786929.1A CN113381396B (en) 2021-07-13 2021-07-13 Circuit and power chip for input voltage abrupt change turn-off output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110786929.1A CN113381396B (en) 2021-07-13 2021-07-13 Circuit and power chip for input voltage abrupt change turn-off output

Publications (2)

Publication Number Publication Date
CN113381396A true CN113381396A (en) 2021-09-10
CN113381396B CN113381396B (en) 2022-06-10

Family

ID=77581845

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110786929.1A Active CN113381396B (en) 2021-07-13 2021-07-13 Circuit and power chip for input voltage abrupt change turn-off output

Country Status (1)

Country Link
CN (1) CN113381396B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159416A (en) * 2007-01-12 2008-04-09 崇贸科技股份有限公司 Control circuit of power supply converter and method thereof
CN105244848A (en) * 2015-10-30 2016-01-13 杰华特微电子（杭州）有限公司 Overvoltage protection method and circuit
CN112510983A (en) * 2021-02-05 2021-03-16 上海芯龙半导体技术股份有限公司 Short-circuit protection circuit, chip and system for switching power supply

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159416A (en) * 2007-01-12 2008-04-09 崇贸科技股份有限公司 Control circuit of power supply converter and method thereof
CN105244848A (en) * 2015-10-30 2016-01-13 杰华特微电子（杭州）有限公司 Overvoltage protection method and circuit
CN112510983A (en) * 2021-02-05 2021-03-16 上海芯龙半导体技术股份有限公司 Short-circuit protection circuit, chip and system for switching power supply

Also Published As

Publication number Publication date
CN113381396B (en) 2022-06-10

Similar Documents

Publication Publication Date Title
US7298124B2 (en) PWM regulator with discontinuous mode and method therefor
US8319487B2 (en) Non-isolated current-mode-controlled switching voltage regulator
US9030177B2 (en) Switched-mode power supply having an adaptive on-time function and controlling output with a ripple control method
US9054596B2 (en) Device for synchronous DC-DC conversion and synchronous DC-DC converter
US8773102B2 (en) Hysteretic CL power converter
US8040121B2 (en) Switching regulator
TWI384742B (en) Voltage regulator automatically adjusting an output voltage according to a load current and method thereof
US8018214B2 (en) Regulator with soft-start using current source
US20110134665A1 (en) Low-voltage start up circuit and method for DC-DC boost converter
TW201703411A (en) Buck-boost power converter and associated control circuit
JP2010045947A (en) Abnormal-current preventive circuit for dc-dc converter
CN100479310C (en) Switching power supply apparatus
US20120043951A1 (en) Switching Regulator and Constant On-time Module
CN113238604B (en) Constant voltage control circuit, chip and system
CN104617771A (en) Switching power converter system and control method thereof
US8547078B2 (en) Methods for light load efficiency improvement of a buck boost voltage regulator
JP2020065402A (en) Switching regulator
CN112953194A (en) Low-voltage starting circuit
CN109617413B (en) Boost chip and mode switching circuit thereof
JP2013094060A (en) Abnormal current prevention circuit for dc-dc converter
CN114744869A (en) Three-level step-down DC converter
US10985650B2 (en) Open-loop charge pump for increasing ripple frequency of output voltage
US20110057636A1 (en) Method for Reducing Energy Loss in DC-DC Converter and Related Control Device and DC-DC Converter
CN113381396B (en) Circuit and power chip for input voltage abrupt change turn-off output
JP2007151322A (en) Power circuit and dc-dc converter

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant