CN113380704A - Method of forming semiconductor device - Google Patents

Method of forming semiconductor device Download PDF

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Publication number
CN113380704A
CN113380704A CN202011372171.9A CN202011372171A CN113380704A CN 113380704 A CN113380704 A CN 113380704A CN 202011372171 A CN202011372171 A CN 202011372171A CN 113380704 A CN113380704 A CN 113380704A
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China
Prior art keywords
hard mask
etch
layer
pitch
patterned hard
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CN202011372171.9A
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Chinese (zh)
Inventor
赖启胜
孙维中
陈立庭
高魁佑
林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113380704A publication Critical patent/CN113380704A/en
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    • H—ELECTRICITY
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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Abstract

Processes are provided for forming gate structures of different pitches. An example method includes: providing a workpiece having a substrate and semiconductor fins spaced apart from each other by isolation features; depositing a layer of gate material over the workpiece; forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising elongated features of different pitches; performing a first etching process to form a trench through the gate material layer using the patterned hard mask as an etching mask; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etching process includes using carbon tetrafluoride and does not use oxygen. Embodiments of the present application also relate to methods of forming semiconductor devices.

Description

Method of forming semiconductor device
Technical Field
Embodiments of the present application relate to methods of forming semiconductor devices.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each of which has smaller, more complex circuits than the previous generation. In the course of IC development, it is common for the functional density (i.e., the number of interconnected devices per chip area) to increase, while the geometry (i.e., the smallest component (or line) that can be produced using the fabrication process) decreases. Such a scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs.
This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. For example, double patterning or multiple patterning has been used to form patterned features of uniform size. First a mandrel is formed over the hard mask layer. A spacer layer is then deposited over the mandrel, including over the sidewalls of the mandrel. After removing the spacer layer deposited over the mandrel to expose the mandrel, the mandrel is selectively removed, leaving behind a patterned spacer layer lining the sidewalls of the mandrel. The patterned spacer layer is used as an etch mask to pattern the underlying hard mask layer. However, when different pitch gate structures are desired in a semiconductor device, the etch loading effect may prevent uniform etching throughout the depth of the gate material used for the gate structures. Several conventional approaches have been proposed to address this challenge, but they are not satisfactory in all respects. Accordingly, there is a need for an improved method.
Disclosure of Invention
Some embodiments of the present application provide a method of forming a semiconductor device, comprising: providing a workpiece comprising a substrate and a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature;
depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etch process through the layer of gate material using the patterned hard mask as an etch mask to form trenches extending through about 90% and about 95% of the first thickness towards the top surfaces of the plurality of semiconductor fins; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature; wherein the first plurality of elongated members comprises a first pitch and the second plurality of elongated members comprises a second pitch that is greater than the first pitch; wherein the first etch process comprises using carbon tetrafluoride and a pressure between 40mTorr and 100 mTorr; wherein the first etching process does not use oxygen.
Other implementations of the present application provide a method of forming a semiconductor device, comprising: providing a workpiece, the workpiece comprising: a substrate; a plurality of semiconductor fins located over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and a dielectric layer conformally disposed over the plurality of semiconductor fins; depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etch process using the patterned hard mask as an etch mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature; wherein the first plurality of elongated members comprises a first pitch and the second plurality of elongated members comprises a second pitch that is greater than the first pitch; wherein the first and third etching processes do not use oxygen, and the second etching process includes using oxygen.
Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: providing a workpiece, the workpiece comprising: a substrate; a plurality of semiconductor fins located over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and a silicon oxide layer conformally disposed over the plurality of semiconductor fins; depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etch process using the patterned hard mask as an etch mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature; wherein the first plurality of elongated members comprises a first pitch and the second plurality of elongated members comprises a second pitch that is 1.1 to 2 times the first pitch; wherein the first etching process comprises carbon tetrafluoride and does not use oxygen; wherein the third etching process does not use oxygen and hydrogen bromide and includes chlorine.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
FIG. 1 is a flow diagram of a method for fabricating a semiconductor device in accordance with aspects of the present invention;
FIG. 2 is a schematic perspective view of a workpiece for a semiconductor device according to aspects of the present invention;
FIG. 3A is a partial schematic top view of a workpiece at one of the stages of manufacture, such as those associated with the method of FIG. 1, in accordance with aspects of the present invention;
fig. 3B and 4-11 are partial schematic cross-sectional views of a workpiece at various stages of manufacture, such as those associated with the method of fig. 1, in accordance with aspects of the present invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Additionally, various components may be arbitrarily drawn in different scales for simplicity and clarity.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) elements or components as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Still further, when a number or range of numbers is described by "about", "approximately", etc., the term is intended to encompass numbers included within a reasonable range of the number described, such as within +/-10% of the number described or other value as understood by one of ordinary skill in the art. For example, the term "about 5 nm" encompasses a size range from 4.5nm to 5.5 nm.
Semiconductor conductor manufacturing advances to accommodate the shrinking dimensions of semiconductor device features. When the reduction in size exceeds the resolution of photolithography, multiple patterning techniques have been used. For example, a Double Patterning Lithography (DPL) process (e.g., a photo-etch-photo-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-dielectric patterning (SIDP) process, other double patterning processes, or a combination thereof) may be used to form the patterned etch mask. Further iterations of the process steps may be performed to form even smaller sized features. For example, a triple patterning process (e.g., a photo-etch-photo-etch (lelelete) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof may be performed. Typically, multiple patterning processes combine lithographic processes and self-aligned processes, allowing the created pattern to be, for example, a pitch that is smaller than that obtainable using a single direct lithographic process. For example, in some embodiments, a patterned sacrificial layer is formed over a substrate using a photolithographic process, and spacers are formed alongside the patterned sacrificial layer using, for example, a self-aligned process. The patterned sacrificial layer is then removed and the spacers can be used as an etch mask to pattern underlying layers, such as a hard mask layer.
A limitation of the aforementioned multiple patterning techniques is that the resulting etch mask includes features of substantially uniform width. This is so because these features are the result of a self-aligned process that occurs on a scale that exceeds the resolution of the lithographic process. Although the lithographic process (es) in multiple patterning techniques may dictate the spacing and spacing between features, it is imperative to vary the dimensions of the self-aligned features. In the above example, as the sacrificial layer is patterned by the photolithography process, the dimensions of the sacrificial layer components in the patterned sacrificial layer may be controlled by the photolithography process. However, the photolithography process does not affect the manner in which the spacers are deposited over the sacrificial layer. Instead, the thickness and uniformity of the spacer layer is largely controlled by the material properties of the spacer layer and the process parameters that are uniformly distributed throughout the spacer layer. As a result, the component dimensions in the spacer layer are largely uniform.
This limitation presents challenges when gate structures with varying pitches are required in semiconductor devices. It has been observed that densely packed features and loosely packed features experience different etch rates due to different etch loading. In one mode of non-uniform etch loading, the byproducts of the etch process may redeposit at different rates on the lateral faces of isolated regions (i.e., loosely packed regions) and dense regions (i.e., densely packed regions), resulting in non-uniform lateral etching in different regions. In some cases, the byproduct redeposition rate in the isolation regions is greater than the byproduct redeposition rate in the dense regions, and the etch rate of the isolation regions is slower than the etch rate of the dense regions. To compensate for the non-uniform lateral etch, the patterned hard mask may be trimmed using additional photolithography and etching processes. In examples where the isolation regions are etched at a lower rate, the patterned hard mask features in the isolation regions are trimmed to have smaller dimensions. However, such additional photolithography and trim processes may involve increased costs and may reduce manufacturing yield. High resolution lithography with smaller wavelengths may also be used to precisely form etch mask features with varying dimensions to compensate for non-uniform lateral etching. However, the use of such high resolution lithographic techniques also involves increased costs.
The present invention provides a process for uniformly etching through a layer of gate material using etch mask features of different pitch but similar size to form a gate structure having substantially straight sidewalls. An example process includes: a first etch process for etching through the layer of gate material over the top surface of the active region (e.g., fin or semiconductor fin); a second etching process for etching the gate material layer to the top surface of the isolation feature; and a third etching process for etching into the isolation feature. The first etching process includes using carbon tetrafluoride and no oxygen (O)2). In addition, the first etching process is performed under increased pressure to reduce lateral etching. The second etching process includes a nitridation process to nitride the dummy gate dielectric layer to protect the active region. The third etching process does not contain oxygen (O)2) And hydrogen bromide (HBr). Instead, the third etching process involves the use of chlorine gas and is short in duration. By avoiding the use of costly alternative processes, the process according to the present invention provides an economical option for forming gate structures of different pitch with substantially vertical sidewalls. In other words, the process of the present invention provides a greater degree of design freedom for circuit designers, regardless of significant increases in manufacturing costs.
Various aspects of the invention will now be described in more detail with reference to the appended drawings. Fig. 1 is a flow diagram of a method 100 for fabricating a semiconductor device in accordance with various aspects of the present invention. In some embodiments, the semiconductor device includes a multi-gate transistor, wherein the gate structure surrounds multiple sides of the active region in its channel region. Examples of multi-gate transistors include fin field effect transistors (finfets) or Gate All Around (GAA) transistors. The method 100 is merely an example and is not intended to limit the present invention to that explicitly illustrated in the method 100. Other steps may be provided before, during, and after the method 100, and some of the steps described may be removed, replaced, or deleted with respect to further embodiments of the method 100. For simplicity, not all steps are described in detail herein. The method 100 will be described below in conjunction with the perspective, top, and partial cross-sectional views of the workpiece 200 shown in fig. 2, 3A, 3B, and 4-11. Since the semiconductor device will be formed from the workpiece 200, the workpiece 200 may be referred to as the semiconductor device 200, depending on the context in which it is desired.
Semiconductor device 200 may be included in a microprocessor, memory, and/or other Integrated Circuit (IC) device. In some embodiments, the semiconductor device 200 may be part of an IC chip, a system on a chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), laterally diffused mos (ldmos) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The illustrations of the semiconductor device 200 in fig. 2, 3A, 3B, and 4-11 have been simplified for the sake of clarity in order to better understand the inventive concepts of the present invention. Other components may be added to the semiconductor device 200, and some of the components described below may be replaced, modified, or deleted in other embodiments of the semiconductor device 200.
Referring to fig. 1, 2, 3A, and 3B, the method 100 includes a block 102 in which a workpiece 200 including a plurality of fins 204 is received at block 102. As shown in fig. 2, 3A, and 3B, the workpiece 200 includes a substrate 202. In the depicted embodiment, the substrate 202 is a bulk substrate comprising silicon. Alternatively, in some implementations, the substrate 202 includes a bulk substrate (including, for example, silicon) and one or more layers of material disposed over the bulk substrate. For example, the one or more material layers may include a semiconductor layer stack having various semiconductor layers (such as heterostructures) disposed over a bulk substrate, wherein the semiconductor layer stack is subsequently patterned to form the fin. The semiconductor layer may comprise any suitable semiconductor material, such as silicon, germanium, silicon germanium, other suitable semiconductor materialsA semiconductor material, or a combination thereof. The semiconductor layers may comprise the same or different materials, etch rates, atomic percent compositions, weight percent compositions, thicknesses, and/or configurations depending on the design requirements of the semiconductor device 200. In some embodiments, the semiconductor layer stack comprises alternating semiconductor layers, for example, a semiconductor layer composed of a first material and a semiconductor layer composed of a second material. For example, the semiconductor layer stack alternates between a silicon layer and a silicon germanium layer (e.g., Si/SiGe/Si from bottom to top). In some embodiments, the semiconductor layer stack includes semiconductor layers of the same material but having alternating atomic percent compositions, such as a semiconductor layer having a first atomic percent composition and a semiconductor layer having a second atomic percent composition. For example, the semiconductor layer stack includes silicon germanium layers (e.g., Si from bottom to top) with alternating atomic percentages of silicon and/or germaniumaGeb/SicGed/SiaGebWhere a, c are different atomic percentages of silicon and b, d are different atomic percentages of germanium). Alternatively or additionally, the bulk substrate 202 and/or one or more material layers comprise another elemental semiconductor, such as germanium; a compound semiconductor such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and/or cadmium telluride; alloy semiconductors such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; other group III-V materials; other group II-V materials; or a combination thereof. Alternatively, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and/or other suitable methods.
In some embodiments, the plurality of fins 204 may be formed from the substrate 202 or deposited a semiconductor layer over the substrate 202 using a multiple patterning process, such as a Double Patterning Lithography (DPL) process (e.g., a photo-etch-photo-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-dielectric patterning (SIDP) process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a photo-etch-photo-etch (lelel) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. Typically, multiple patterning processes combine lithographic processes and self-aligned processes, allowing the created pattern to be, for example, a pitch that is smaller than that obtainable using a single direct lithographic process. For example, in some embodiments, a patterned sacrificial layer is formed over a substrate using a photolithographic process, and spacers are formed alongside the patterned sacrificial layer using, for example, a self-aligned process. The patterned sacrificial layer is then removed and the spacers can be used to pattern the underlying layers. In some implementations, a directed self-assembly (DSA) technique is implemented during multiple patterning processes. Since each of the plurality of fins 204 is formed from a semiconductor material that forms the substrate 202 or a semiconductor layer deposited over the substrate 202, it may also be referred to as a semiconductor fin or a semiconductor fin structure. A detailed description of the process of forming the plurality of fins 204 is omitted for the sake of brevity.
Referring to fig. 2, fig. 2 is a perspective view of a workpiece 200 including a plurality of fins 204. The fins 204 extend upward from the substrate 202 along the Z-direction and extend parallel to each other along the X-direction. By way of example, five fins are shown in fig. 2 of the present invention. The invention is not so limited and workpieces comprising more or less fins 204 are fully contemplated. Isolation features 206 (i.e., Shallow Trench Isolation (STI) features) are formed between adjacent fins 204 to provide electrical isolation and mechanical support. Accordingly, the isolation feature 206 comprises an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, and/or other suitable isolation compositions), or combinations thereof. As shown in fig. 2, the isolation feature 206 is pulled back to form the inter-fin recess 205 such that a portion of each of the plurality of fins rises above the top surface of the isolation feature 206. The top view shown in fig. 3A also shows that the plurality of fins 204 extend along the X-direction, and each fin is spaced apart from adjacent fins by an isolation feature 206. A Y-direction view along section I-I' along one of the plurality of fins 204 is provided in fig. 3B. The isolation feature 206 is not visible in fig. 3B because the cross-section passes through one of the plurality of fins 204. To illustrate various components of the present invention, subsequent figures, including fig. 4-11, are partial sectional views of a cross-section I-I' through a fin 204 of a workpiece 200, as shown in fig. 3B.
Referring to fig. 1 and 4, the method 100 includes block 104, wherein a layer of gate material 208 is deposited over the plurality of fins 204. As shown in fig. 4, a layer of gate material 208 is deposited over the workpiece 200, including over the top surface of the isolation feature 206, over the top surface of each of the plurality of fins 204, and into the inter-fin recess 205 (as shown in fig. 2, but not shown in fig. 4). In some embodiments employing a gate-last process or a gate replacement process, gate material layer 208 is intended for forming a dummy gate stack and may comprise polysilicon. The dummy gate structure serves as a placeholder for the functional gate structure, throughout a portion of the fabrication process, and is replaced by the functional gate stack at a later point. A dummy gate dielectric layer 207 may be blanket deposited over the workpiece 200 prior to depositing the gate material layer 208. As shown in fig. 4, along section I-I', a dummy gate dielectric layer 207 is disposed between the top surface of fin 204 and gate material layer 208. A dummy gate dielectric layer 207 is also disposed over sidewalls of the plurality of fins 204. In some embodiments, the dummy gate dielectric layer 207 may include silicon oxide deposited using thermal oxidation or a suitable process.
Still referring to fig. 1 and 4, the method 100 includes block 106, wherein a hard mask layer 210 is deposited over the gate material layer 208. In some embodiments, the hard mask layer 210 is patterned to form a patterned hard mask layer 210 to be used as an etch mask for patterning the gate material layer 208. In some embodiments not shown, the hard mask layer 210 may be a single layer formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, or a suitable dielectric material. In some alternative embodiments, illustrated in fig. 4, the hard mask layer 210 may be a multilayer. As shown in fig. 4, the hard mask layer 210 includes a first hard mask layer 212 and a second hard mask layer 214. In some embodiments, the first hard mask layer 212 is formed of silicon oxide and the second hard mask layer is formed of a nitrogen-containing dielectric material such as silicon nitride or silicon oxynitride. Each of the first and second hard mask layers 212, 214 may be deposited using Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), other suitable processes, or a combination thereof.
Referring to fig. 1 and 4, method 100 includes block 108 in which mandrel features 216 (including first plurality of mandrel features 2161, second plurality of mandrel features 2162, and third plurality of mandrel features 2163) are formed over hardmask layer 210. Each of the first plurality of spindle parts 2161 has a first width W1 along the X-direction. Each of the second plurality of spindle parts 2162 has a second width W2 along the X-direction. Each of the third plurality of spindle parts 2163 has a third width W3 along the X-direction. The third width W3 is greater than the second width W2, and the second width W2 is greater than the first width W1. In some cases, the ratio of the second width W2 to the first width W1 is between about 1.1 and about 2.0, and the ratio of the third width W3 to the first width W1 is between about 1.1 and about 2.0. Note that although the first, second, and third pluralities of mandrel components 2161, 2162, 2163 are shown adjacent to one another on the workpiece 200 in fig. 4, the present invention is not so limited, and fig. 4 is merely intended to representatively illustrate mandrel components that may be formed with varying widths in different areas of the same workpiece 200.
The mandrel members 216 may be formed in the following example process. A sacrificial layer is deposited over the hard mask layer 210 by spin coating, Chemical Vapor Deposition (CVD), or a suitable deposition process. The sacrificial layer may be formed of a material having an etch selectivity different from that of the hard mask layer 210 or the spacer layer (218 shown in fig. 5), so that the sacrificial layer may be patterned or removed without damaging the hard mask layer 210 and the spacer layer. In some embodiments, the sacrificial layer may be a suitable semiconductor material (e.g., silicon, germanium, or amorphous silicon), a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide), other suitable material, or a combination thereof. The sacrificial layer is then patterned to form mandrel features 216. The sacrificial layer is patterned using a photolithography process. A photoresist layer is deposited over the sacrificial layer using spin coating and then baked in a pre-exposure bake process. The photoresist layer may be a single layer or multiple layers, such as three layers. The pre-baked photoresist layer is then exposed to radiation that is reflected off of or transmitted through the patterned photomask. Then, the exposed photoresist layer is baked in a post-exposure bake process, and developed in a developing process. The radiation source may be an excimer laser source, an Ultraviolet (UV) source, a Deep Ultraviolet (DUV) source, or an Extreme Ultraviolet (EUV) source. Because the photoresist layer is selected to be radiation sensitive, the exposed (or unexposed) portions of the photoresist layer chemically change during the development process and become dissolved in the developer solution. The resulting patterned photoresist layer bears a pattern corresponding to the pattern of the mask. The patterned photoresist layer may then be used as an etch mask during an etching process to remove portions of the underlying sacrificial layer. The etching process may include a dry etching process (e.g., a Reactive Ion Etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. After the etching process, the patterned photoresist layer may be removed by ashing or a suitable method. Alternatively, the exposure process may implement maskless lithography, electron beam writing, ion beam writing, and/or nano-printing techniques. As shown in fig. 4, since the mandrel part 216 is formed by the photolithography process, the mandrel part may be allowed to have different widths in the X direction.
Referring to fig. 1, 5, and 6, the method 100 includes a block 110 in which a first plurality of spacer features 2181, a second plurality of spacer features 2182, and a third plurality of spacer features 2183 are formed over the hard mask layer 210. In some embodiments represented by fig. 5, the spacer layer 218 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the mandrel members 216, using spin coating, Chemical Vapor Deposition (CVD), or a suitable deposition process. The spacer layer 218 may be formed of a material having an etch selectivity different from that of the mandrel members 216, so that the mandrel members 216 may be selectively removed without damaging the spacer layer 218. Meanwhile, the material of the spacer layer 218 may be selected to have an etch selectivity different from that of the hard mask layer 210, so that the spacer features formed by the spacer layer 218 may be used as an etch mask for the hard mask layer 210. In some embodiments, spacer layer 218 may be a suitable semiconductor material (e.g., silicon, germanium, or amorphous silicon), a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide), other suitable material, or a combination thereof.
Referring now to fig. 6, after depositing the spacer layer 218, an anisotropic etch back process may be performed to remove the excess spacer layer 218 on the hard mask layer 210 and on the top surface of the mandrel features 216. An etch-back process is performed such that the mandrel members 216 are exposed from portions of the spacer layers extending along the sidewalls of the mandrel members 216. The mandrel components 216 are then selectively removed, leaving behind a patterned spacer layer 218 comprising a first plurality of spacer components 2181, a second plurality of spacer components 2182, and a third plurality of spacer components 2183. In some embodiments represented by fig. 6, the first plurality of spacer elements 2181 may be characterized by a first pitch P1, the second plurality of spacer elements 2182 may be characterized by a second pitch P2, and the third plurality of spacer elements 2183 may be characterized by a third pitch P3. As can be seen from fig. 4-6, the first pitch P1 substantially corresponds to the first width W1, the second pitch P2 substantially corresponds to the second width W2, and the third pitch P3 substantially corresponds to the third width W3. In some cases, the first pitch P1 is substantially equal to the first width W1 and the thickness of the spacer layer 218; the second pitch P2 is substantially equal to the second width W2 and the thickness of the spacer layer 218; the third pitch P3 is substantially equal to the thickness of the third width W3 spacer layer 218. In some embodiments, the ratio of the second pitch P2 to the first pitch P1 is between about 1.1 and about 2.0, and the ratio of the third pitch P3 to the first pitch P1 is between about 1.1 and about 2.0. Although the second pitch P2 and the third pitch P3 share the same range, in the illustrated embodiment, the third pitch P3 is greater than the second pitch P2. The difference between the first pitch P1 and the second pitch P2 or the third pitch P3 is at least about 10% to be sufficiently significant that the resulting device may exhibit different characteristics or functions. Meanwhile, the second pitch P2 or the third pitch P3 is less than about twice the first pitch P1, so that the device density is not affected by the increased pitch.
Referring to fig. 1 and 7, the method 100 includes a block 112 in which the hard mask layer 210 is patterned using the first, second, and third pluralities of spacer features 2181, 2182, 2183 as an etch mask. In some embodiments, the hard mask layer 210 including the first and second hard mask layers 212 and 214 may be etched through the first, second, and third pluralities of spacer features 2181, 2182, 2183 using a dry etch process, a wet etch process, or a suitable process. An exemplary dry etch may use a fluorine-containing precursor (e.g., CF)4、SF6、NF3、CH2F2、CHF3And/or C2F6) Oxygen-containing precursor, chlorine-containing precursor (e.g. Cl)2、CHCl3、CCl4And/or BCl3) Bromine-containing precursors (e.g., HBr, and/or CHBR)3) An iodine-containing precursor, other suitable precursors (which may be used to generate the etchant gas and/or the etching plasma), or combinations thereof. An exemplary wet etch process implements an etch solution comprising TMAH, NH4OH、H2O2、H2SO4HF, HCl, other suitable wet etching composition, or combinations thereof. As shown in fig. 7, an operation at block 112 transfers a pattern of the first plurality of spacer features 2181, the second plurality of spacer features 2182, and the third plurality of spacer features 2183 onto the hard mask layer 210 resulting in a patterned hard mask 220 comprising a first plurality of hard mask features 2201, a second plurality of hard mask features 2202, and a third plurality of hard mask features 2203. Similar to the first, second, and third pluralities of spacer components 2181, 2182, 2183, the first plurality of hardmask componentsMold components 2201 include a first pitch P1, second plurality of hard mask components 2202 include a second pitch P2, and third plurality of hard mask components 2203 include a third pitch P3. As shown in fig. 7, gate material layer 208 located beneath first plurality of hard mask components 2201, second plurality of hard mask components 2202, and third plurality of hard mask components 2203 includes a first thickness (T1) measured from the top surface of fin 204.
Referring to fig. 1 and 8, the method 100 includes a block 114 in which a first etch process 300 is performed using the patterned hard mask 220 as an etch mask. In some embodiments, the first etch process 300 is a main etch process that etches the second thickness T2 to a height Z2 in a top-down manner from the top surface height Z1 of the gate material layer 208. In some cases, the second thickness T2 is about 90% and about 95% of the first thickness T1. That is, at the end of the first etch process 300, a limited or measurable amount of the gate material layer remains over the top surfaces of the plurality of fins 204. To easily remove the byproducts of the first etch process 300 of the gate material layer 208, the first etch process includes using carbon tetrafluoride (CF)4) A dry etching process as an etchant. Among conventional processes, carbon tetrafluoride (CF) is not preferably used in the main etching process4) Since this would result in a strong lateral etch that could prematurely thin the top of the gate structure (230 shown in fig. 11). In accordance with the present invention, the pressure of the first etch process 300 is increased from less than 20mTorr in conventional processes to between about 40mTorr and about 100 mTorr. It can be observed that the increased process pressure of the third etch process 500 reduces the mean free path of carbon tetrafluoride, thereby mitigating lateral etching associated with the use of carbon tetrafluoride. The disclosed pressure range (i.e., between about 40mTorr and about 100 mTorr) is selected such that the pressure of the first etch process 300 is at least twice that of the conventional pressure range to ensure a detectable difference in etch characteristics. At the same time, the pressure range is selected such that the pressure of the first etch process 300 does not unduly decrease the mean free path and unduly decrease the etch rate. The increased process pressure at block 114 requires increased energy to ignite the plasma. In some embodiments, the first etch process 300 and the third etch process500 may include using an Inductively Coupled Plasma (ICP) with a power in a range between about 400W and about 3500W, or using a Capacitively Coupled Plasma (CCP) with a power in a range between about 500W and about 5500W. When the ICP or CCP power level falls below the disclosed range, the etch rate may be unduly reduced and the process time may be increased. An increase in process time will result in an increase in production costs. When the ICP or CCP power level is raised above the disclosed range, the etch rate may be unduly increased and the desired etch characteristics may be lost, resulting in an undesirable fin sidewall profile.
Although lateral etching may be a concern for the first etch process 300, the first etch process 300 does not use oxygen (O2), which is known to generate more by-products to passivate the sidewalls of the gate structure 230 (as shown in fig. 11). In some embodiments, the first etch process 300 may further include hydrogen bromide (HBr) and chlorine (Cl2) in addition to carbon tetrafluoride (CF 4). In some cases, the first etch process 300 includes 200 seem (standard cubic centimeters per minute) of hydrogen bromide and about 20 seem to 50 seem of carbon tetrafluoride. As shown in fig. 8, the first etch process forms a first trench 241 defined between two of the first plurality of hard mask features 2201, a second trench 242 defined between two of the second plurality of hard mask features 2202, and a third trench 243 defined between two of the third plurality of hard mask features 2203 at block 114. Each of the first, second, and third grooves 241, 242, 243 has a depth substantially equal to the second thickness T2. As described above, the second thickness T2 is about 90% to about 95% of the first thickness T1.
Referring to fig. 1, 9, and 10, the method 100 includes a block 116 in which a second etch process 400 is performed using the patterned hard mask 220 as an etch mask. Reference is first made to fig. 9. In some embodiments, the second etch process 400 is a soft landing etch process that etches from a height Z2 to a height Z3 at the top surface of the isolation feature 206 in a top-down manner. Unlike the first etching process 300, the second etching process 400 does not contain carbon tetrafluoride and includes oxygen (O) gas2) To do so byEnhancing lateral passivation. In some embodiments, the second etch process 400 may include using chlorine (Cl)2) Oxygen (O)2) And hydrogen bromide (HBr). In some cases, the process pressure for the second etch process 400 is also between about 40 millitorr (mTorr) and about 100mTorr for reasons similar to those described above with respect to block 114. As shown in fig. 9, the second etch process 400 extends the first trench 241, the second trench 242, and the third trench 243 to a height Z3 (i.e., the top surface of the isolation feature 206).
Reference is now made to fig. 10. In some embodiments, to prevent accidental damage to the plurality of fins 204, the second etch process 400 may optionally include a nitridation process 410, the nitridation process 410 including introducing a nitrogen-containing reagent, such as nitrogen (N) gas2) Or ammonia (NH)3) To nitride the dummy gate dielectric layer 207. In the case where the dummy gate dielectric layer 207 is formed of silicon oxide, the nitridation process 410 may introduce nitrogen into the dummy gate dielectric layer 207 such that at least an outer portion of the dummy gate dielectric layer 207 is formed of silicon oxynitride (SiON). Since the silicon oxynitride is etched at a slower etch rate than the silicon oxide during the second etch process 400, the nitridation process 410 may protect the fin 204 from damage due to the second etch process 400. The nitridation process 410 may be incorporated into the second etch process 400. In this regard, the second etch process 400 may include an etch period (i.e., using the above-described etchants, such as chlorine, hydrogen bromide, and oxygen) and a nitridation period (i.e., nitridation process 410). In one example, the second etch process 400 may begin with an etch cycle, followed by a nitridation cycle, followed again by another etch cycle. Other arrangements of etch periods and nitridation periods are fully contemplated.
Referring to fig. 1 and 11, the method 100 includes a block 118 in which a third etch process 500 is performed using the patterned hard mask 220 as an etch mask. In some embodiments, the third etch process 500 is an overetch process that etches in a top-down manner into the top surfaces of the isolation features 206. That is, the third etch process 500 extends the first trench 241, the second trench 242, and the third trench 243 further at least partially into the isolation feature 206. In thatAt the end of the operations of block 118, a gate structure 230 is substantially formed. As shown in fig. 11, the gate structures 230 include a first plurality of gate structures 2301 having a first pitch P1, a second plurality of gate structures 2302 having a second pitch P2, and a third plurality of gate structures 2303 having a third pitch P3. According to the present invention, the purpose of the third etch process 500 is to laterally etch sidewalls toward the bottom of the first trench 241, the second trench 242, and the third trench 243. In some embodiments, the third etch process 500 comprises chlorine gas (Cl) supplied between about 200sccm and about 500sccm2) The use of (1). To prevent accidental damage to the portions of the gate structure 230 that have been formed in the first and second etch processes 300 and 400, the third etch process 500 may last between about 10 seconds and about 20 seconds. In some embodiments, the third etch process 500 does not include the use of hydrogen bromide (HBr) and oxygen (O)2). The former has a lower etch rate than chlorine and the latter acts to enhance lateral passivation. In some cases, the third etch process 500 may also be performed at a pressure between about 40mTorr and about 100mTorr for reasons similar to those described above with respect to block 114. As described above, this increased pressure range may reduce the mean free path of the etchant and may reduce the etch rate.
Referring to fig. 1, the method 100 includes a block 120 in which additional processes are performed. The additional processes may include depositing a gate spacer over the gate structure 230, depositing an interlayer dielectric (ILD) layer over the workpiece 200, forming a source/drain trench adjacent to the gate structure 230, forming a source/drain epitaxial feature, depositing another ILD layer, replacing the gate stack with a functional gate structure, forming a source/drain contact to the source/drain epitaxial feature, and forming a gate contact to the functional gate structure. Since the functional gate structure replaces the gate structure 230, it substantially inherits the shape, size, and spacing of the gate structure 230. At the conclusion of the method 100, the functional gate structures of the semiconductor device 200 include a first plurality of functional gate structures that replace the first plurality of gate structures 2301, a second plurality of functional gate structures that replace the second plurality of gate structures 2302, and a third plurality of functional gate structures that replace the third plurality of gate structures 2303. As a result, the first plurality of functional gate structures may have a first pitch P1, the second plurality of functional gate structures may have a second pitch P2, and the third plurality of functional gate structures may have a third pitch P3.
The process of the present invention provides benefits. Examples of the process of the present invention include a first etching process, a second etching process, and a third etching process. The first etch process is a main etch process that etches through most of the depth of the gate material layer over the fins to form trenches. The first etching process includes using carbon tetrachloride (CF)4) For removing by-products over time and increasing the pressure to reduce lateral etching. The first etch process does not include the use of oxygen, which may cause more by-products to redeposit. The second etch process is a soft landing etch process that extends the trench to the top surface of the isolation feature. The second etch process includes using oxygen and may include a nitridation process to protect the fins from damage. The third etching process is an over-etching process that partially extends the trench into the isolation feature. The third etching process includes using chlorine gas (Cl)2) And shorter etching times. The process of the present invention can be used to etch through layers of gate material to form gate structures of different pitches without the need for additional photolithography steps.
In one aspect, the present invention provides a method. The method comprises the following steps: providing a workpiece comprising a substrate and a plurality of semiconductor fins located over the substrate, wherein each of the plurality of semiconductor fins is spaced apart from another of the plurality of semiconductor fins by an isolation feature; depositing a gate material layer over the workpiece, wherein the gate material layer comprises a first thickness over a top surface of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, wherein the patterned hard mask comprises a first plurality of elongated features and a second plurality of elongated features; performing a first etch process through the layer of gate material using the patterned hard mask as an etch mask to form trenches extending through about 90% and about 95% of the first thickness towards a top surface of the plurality of semiconductor fins; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first plurality of elongated members includes a first pitch and the second plurality of elongated members includes a second pitch that is greater than the first pitch. The first etch process includes using carbon tetrafluoride and a pressure between about 40mTorr and about 100mTorr, and the first etch process does not use oxygen.
In some embodiments, the first etching process further comprises using hydrogen bromide and chlorine. In some embodiments, the ratio of the second pitch to the first pitch is between about 1.1 and about 2.0. In some cases, the second etching process includes a dry etching process using chlorine, hydrogen bromide, or oxygen. In some embodiments, the second etch process comprises a nitridation process using a nitrogen-containing reagent. In some embodiments, the nitrogen-containing reagent comprises nitrogen (N)2). In some embodiments, the third etching process includes chlorine. In some embodiments, the third etching process does not use oxygen and hydrogen bromide.
In another aspect, the present invention provides a method. The method comprises the following steps: providing a workpiece, the workpiece comprising: a substrate; a plurality of semiconductor fins located over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and a dielectric layer conformally disposed over the plurality of semiconductor fins; depositing a gate material layer over the workpiece, wherein the gate material layer comprises a first thickness over a top surface of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, wherein the patterned hard mask comprises a first plurality of elongated features and a second plurality of elongated features; performing a first etch process using the patterned hard mask as an etch mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first plurality of elongated members includes a first pitch and the second plurality of elongated members includes a second pitch that is greater than the first pitch. The first etching process and the third etching process do not use oxygen, and the second etching process includes using oxygen.
In some embodiments, the first etching process includes using hydrogen bromide, carbon tetrafluoride, and chlorine. In some embodiments, the first etch process includes a pressure between about 40mTorr and about 100 mTorr. In some cases, the ratio of the second pitch to the first pitch is between about 1.1 and about 2.0. In some embodiments, the second etching process includes a dry etching process using chlorine, hydrogen bromide, or oxygen. In some embodiments, the third etching process includes chlorine. In some embodiments, the second etch process includes a nitridation process to introduce nitrogen into the dielectric layer. In some cases, the nitridation process includes the use of nitrogen (N)2)。
In another aspect, the present invention provides a method. The method comprises the following steps: providing a workpiece, the workpiece comprising: a substrate; a plurality of semiconductor fins located over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and a silicon oxide layer conformally disposed over the plurality of semiconductor fins; depositing a gate material layer over the workpiece, wherein the gate material layer comprises a first thickness over a top surface of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, wherein the patterned hard mask comprises a first plurality of elongated features and a second plurality of elongated features; performing a first etch process using the patterned hard mask as an etch mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first plurality of elongated members includes a first pitch and the second plurality of elongated members includes a second pitch that is about 1.1 times to about 2 times the first pitch. The first etching process includes carbon tetrafluoride and does not use oxygen. The third etching process does not use oxygen and hydrogen bromide and includes chlorine.
In some embodiments, the first etching process further comprises using hydrogen bromide and chlorine. In some embodiments, the first etch process includes a pressure between about 40mTorr and about 100 mTorr. In some cases, the second etch process includes a nitridation process to convert a portion of the silicon oxide layer to silicon oxynitride.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of forming a semiconductor device, comprising:
providing a workpiece comprising a substrate and a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature;
depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over top surfaces of the plurality of semiconductor fins;
forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features;
performing a first etch process through the layer of gate material using the patterned hard mask as an etch mask to form trenches extending through about 90% and about 95% of the first thickness towards the top surfaces of the plurality of semiconductor fins;
performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and
performing a third etch process using the patterned hard mask to extend the trench into the isolation feature;
wherein the first plurality of elongated members comprises a first pitch and the second plurality of elongated members comprises a second pitch that is greater than the first pitch;
wherein the first etch process comprises using carbon tetrafluoride and a pressure between 40mTorr and 100 mTorr;
wherein the first etching process does not use oxygen.
2. The method of claim 1, wherein the first etching process further comprises using hydrogen bromide and chlorine.
3. The method of claim 1, wherein a ratio of the second pitch to the first pitch is between 1.1 and 2.0.
4. The method of claim 1, wherein the second etching process comprises a dry etching process using chlorine, hydrogen bromide, or oxygen.
5. The method of claim 1, wherein the second etch process comprises a nitridation process using a nitrogen-containing reagent.
6. The method of claim 5, wherein the nitrogen-containing reagent comprises nitrogen gas (N)2)。
7. The method of claim 1, wherein the third etching process comprises chlorine.
8. The method of claim 7, wherein the third etching process does not use oxygen and hydrogen bromide.
9. A method of forming a semiconductor device, comprising:
providing a workpiece, the workpiece comprising:
a substrate;
a plurality of semiconductor fins located over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and
a dielectric layer conformally disposed over the plurality of semiconductor fins;
depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over top surfaces of the plurality of semiconductor fins;
forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features;
performing a first etch process using the patterned hard mask as an etch mask to form a trench extending through a majority of the first thickness;
performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and
performing a third etch process using the patterned hard mask to extend the trench into the isolation feature;
wherein the first plurality of elongated members comprises a first pitch and the second plurality of elongated members comprises a second pitch that is greater than the first pitch;
wherein the first and third etching processes do not use oxygen, and the second etching process includes using oxygen.
10. A method of forming a semiconductor device, comprising:
providing a workpiece, the workpiece comprising:
a substrate;
a plurality of semiconductor fins located over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and
a silicon oxide layer conformally disposed over the plurality of semiconductor fins;
depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over top surfaces of the plurality of semiconductor fins;
forming a patterned hard mask over the layer of gate material, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features;
performing a first etch process using the patterned hard mask as an etch mask to form a trench extending through a majority of the first thickness;
performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and
performing a third etch process using the patterned hard mask to extend the trench into the isolation feature;
wherein the first plurality of elongated members comprises a first pitch and the second plurality of elongated members comprises a second pitch that is 1.1 to 2 times the first pitch;
wherein the first etching process comprises carbon tetrafluoride and does not use oxygen;
wherein the third etching process does not use oxygen and hydrogen bromide and includes chlorine.
CN202011372171.9A 2020-02-25 2020-11-30 Method of forming semiconductor device Pending CN113380704A (en)

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