CN113365015B - Video data processing device and method - Google Patents
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- CN113365015B CN113365015B CN202110601940.6A CN202110601940A CN113365015B CN 113365015 B CN113365015 B CN 113365015B CN 202110601940 A CN202110601940 A CN 202110601940A CN 113365015 B CN113365015 B CN 113365015B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234381—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by altering the temporal resolution, e.g. decreasing the frame rate by frame skipping
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping
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Abstract
The invention discloses a video data processing device and a method, wherein the device adopts a cache block with small memory space, meets the requirement of different video data processing modes on the cache space by a mode of overlapping a plurality of cache blocks, and also presets the corresponding relation between different data processing modes and data transmission paths, thereby realizing the purpose of different algorithms by different data transmission modes. Thus, a variety of different video processing algorithms can be supported without changing the cache organization of the hardware.
Description
Technical Field
The present invention relates to the field of data storage, and in particular, to a video data processing apparatus and method.
Background
In the process of transmitting video data, based on the requirements of a terminal, it is generally necessary to perform interpolation processing on a video image for the purpose of enlargement or reduction, wherein in some systems, the video data needs to be buffered as operation metadata before the video image is enlarged or reduced.
At present, because different interpolation algorithms are different to the demand of metadata, bilinear interpolation operation for example, operation needs 4 metadata, two cubic interpolation operation at every turn, operation needs 16 metadata at every turn, in order to satisfy different interpolation algorithm's demand, a cache organizational structure has been designed to an algorithm among the prior art, like this, cache organizational structure is solidification, when needs carry out interpolation processing to video data, can't select more suitable algorithm. Moreover, if a plurality of algorithms are included at the same time, a large number of cache organization structures are required, which greatly increases the chip area.
Disclosure of Invention
In view of this, the embodiment of the present invention discloses a video data processing apparatus and method, which can support multiple different video processing algorithms without changing the cache organization structure of hardware
The embodiment of the invention discloses a video data processing device, which comprises:
the system comprises a controller, a plurality of cache blocks, a plurality of registers, a plurality of data selectors and an algorithm module;
the controller is respectively connected with each cache block;
each cache block is connected with the input and the output of the data selector respectively;
each register is respectively connected with the input and the output of each data selector;
each cache block is connected with each algorithm module respectively;
each register is respectively connected with each algorithm module;
the controller is used for acquiring a data transmission path corresponding to the data processing mode when the video data processing mode is determined, and sending video data to a corresponding cache block according to the data transmission path;
the algorithm module is used for reading video data from the buffer block according to algorithm requirements and processing the read video data;
the register is used for storing the operation result output by the algorithm module and sending the output operation result to the corresponding cache block through the data selector;
the buffer block is used for receiving the video data and transmitting the video data according to the data transmission path sent by the controller.
Optionally, when the video data processing mode is the first video data processing mode, the transmission path of the first video data processing mode includes:
the controller sends the video data to the first cache block or the fifth cache block;
if the first cache block receives video data, sending the video data to a second cache block through a first data selector connected with the first cache block, sending the video data to a third cache block through a second data selector connected with the second cache block, and sending the video data to a fourth cache block through a third data selector connected with the third cache block;
if the fifth cache block receives the video data, sending the video data to a sixth cache block through a fourth data selector connected with the fifth cache block, sending the data to a seventh cache block through the fifth data selector connected with the sixth cache block, and sending the data to an eighth cache block through the sixth data selector connected with the seventh cache block;
and a first algorithm module connected with the fourth cache block and the eighth cache block reads video data from the fourth cache block and the eighth cache block for interpolation processing.
Optionally, when the video data processing module is in the second video data processing mode, the transmission path of the second video data processing mode includes:
the controller respectively sends the video data to the first cache block or the fifth cache block;
after a first cache block receives video data, sending the video data to a second cache block through a first data selector connected with the first cache block, sending the video data to a third cache block through a second data selector connected with the second cache block, reading the video data from the third cache block by a second algorithm module connected with the third cache block and carrying out interpolation operation, sending a first result of the interpolation operation to a first register, sending the first result to a fourth cache block through a third data selector connected with the first register, and reading the first result from the fourth cache block by the third algorithm module and carrying out interpolation operation;
when a fifth cache block receives data, sending the video data to a sixth cache block through a fourth data selector connected with the fifth cache block, sending the video data to a seventh cache block through the fifth data selector connected with the sixth cache block, reading the video data from the seventh cache block by a second algorithm module connected with the seventh cache block and carrying out interpolation operation, sending a second result of the interpolation operation to a second register, sending the second result to an eighth cache block through the sixth data selector connected with the second register, and reading the second result from the eighth cache block by the third algorithm module and carrying out interpolation operation.
Optionally, when the video data processing module is in a third video data processing mode, the transmission path of the third video data processing mode includes:
the controller respectively sends the video data to a first cache block, a third cache block, a fifth cache block or a seventh cache block;
after a first cache block receives video data, the video data is sent to a second cache block through a first data selector connected with the first cache block;
after the third cache block receives video data, the video data is sent to a fourth cache block through a second data selector connected with the third cache block;
the fourth algorithm module is respectively connected with the second cache block and the fourth cache block and is used for reading the video data from the second cache block and the fourth cache block and carrying out interpolation operation;
after a fifth cache block receives video data, the video data is sent to a sixth cache block through a fourth data selector connected with the fifth cache block;
after the seventh cache block receives the video data, the video data is sent to an eighth cache block through a sixth data selector connected with the seventh cache block;
and the fourth algorithm module is respectively connected with the fifth cache block and the eighth cache block and is used for reading the video data from the fourth cache block and the eighth cache block and carrying out interpolation operation.
Optionally, when the video data processing module is in a fourth video data processing mode, the transmission path of the fourth video data processing mode includes:
the controller respectively sends video data to a first cache block, a second cache block, a fifth cache block and a sixth cache block;
after the first cache block receives video data, a fifth algorithm module reads the video data from the first cache block and performs interpolation operation, and sends an obtained third result to a third register connected with the fifth algorithm module;
after the second cache block receives video data, a sixth algorithm module connected with the second cache block reads the video data from the second cache block and performs interpolation operation, and sends a fourth result to a third register connected with the sixth algorithm module;
the third result and the fourth result are sent to a third cache block through a first data selector connected with the third register, the received third result and the received fourth result are sent to a fourth cache block through a second data selector connected with the third cache block, and a seventh algorithm module reads data from the fourth cache block and performs interpolation operation on the read data;
after a fifth cache block receives video data, a fifth algorithm module connected with the fifth cache block reads the video data from the fifth cache block and performs interpolation operation, and sends a fifth result to a fourth register connected with the fifth algorithm module;
after the sixth cache block receives video data, a sixth algorithm module connected with the sixth cache block reads the video data from the sixth cache block and performs interpolation operation, and sends a sixth result to a fourth register connected with the sixth algorithm module;
and sending the fifth result and the sixth result to a seventh cache block through a third data selector connected with the fourth register, sending the received fifth result and the received sixth result to an eighth cache block through a fourth data selector connected with the seventh cache block, and reading data from the eighth cache block by an eighth algorithm module and performing interpolation operation on the read data.
The embodiment of the invention also discloses a video data processing method, which comprises the following steps:
receiving a video to be processed;
detecting basic information of the video to be processed and acquiring output basic information;
determining a video data processing mode based on basic information of a video to be processed and output basic information;
and triggering the video data processing device to process the video to be processed based on the video data processing mode.
Optionally, the basic information of the video to be processed includes: a resolution of the video to be processed.
The embodiment of the invention discloses a video data processing device and a method, the device adopts a cache block with small memory space, meets the requirements of different video data processing modes on the cache amount in a mode of overlapping a plurality of cache blocks, and presets the corresponding relation between different data processing modes and data transmission paths, thereby realizing the purpose of different algorithms in different data transmission modes. Thus, a variety of different video processing algorithms can be supported without changing the cache organization of the hardware.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram illustrating a video data processing apparatus according to embodiment 1 of the present invention;
fig. 2 illustrates a transmission path of a single bilinear interpolation mode provided in an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a data transmission path in a twice bilinear reduction mode according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a data transmission path of a bilinear interpolation magnification mode according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a data transmission path of a dual cubic interpolation scheme provided by an embodiment of the present invention;
fig. 6 is a schematic flowchart illustrating a video data processing method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1, a schematic structural diagram of a video data processing apparatus according to embodiment 1 of the present invention is shown, and in this embodiment, the apparatus includes:
a controller 100, a plurality of cache blocks 200, a plurality of registers 400, a plurality of data selectors 300, and an algorithm module 500;
the controller 100 is connected to each of the cache blocks 200;
each cache block 200 is connected to the input and output of the data selector 300, respectively;
each register 400 is connected to the input and output of each data selector 300, respectively;
each cache block 200 is connected to each algorithm module 500;
each register 400 is connected to each algorithm module 500;
the controller 100 is configured to, when a video data processing mode is determined, obtain a data transmission path corresponding to the data processing mode, and send video data to a corresponding cache block according to the data transmission path;
the algorithm module 500 is configured to read video data from the buffer block according to an algorithm requirement, and process the read video data;
the register 400 is used for storing the operation result output by the algorithm module and sending the output operation result to the corresponding cache block through the data selector 300;
the buffer block 200 is used for receiving video data and transmitting the video data according to a data transmission path sent by the controller.
In this embodiment, after receiving the video, the controller determines the processing mode of the video to be processed according to the basic information of the video to be processed and the basic information of the video to be output.
The basic information of the video at least comprises the resolution of the video image, and the basic information of the output image at least comprises the resolution of the output video image.
In this embodiment, the controller determines a video conversion mode, that is, a data processing mode of the video, according to a resolution of an input video image and a resolution of an output video image, where a relationship between different data processing modes and data transmission paths is preset, and a corresponding data transmission path may be determined by the data processing module of the video, so that the data transmits the video data according to the determined data transmission path.
The data processing mode may include multiple types, which is not limited in this embodiment, and technicians may set different data processing modules according to requirements, for example. The data processing mode can be single bilinear interpolation, double bilinear interpolation for amplification, double bilinear interpolation for reduction, double cubic interpolation and the like.
In this embodiment, different data transmission paths may represent connection modes of different modules in the video data processing apparatus.
In this embodiment, different algorithm modules include different processing methods of video data, for example, an interpolation algorithm or a filtering algorithm, and a specific algorithm to be used is determined according to a data processing mode.
In this embodiment, the register is used to store intermediate data generated by the video data processing apparatus, for example, after the video data is processed by the algorithm module, the processing result of the video data may be stored in the register.
In this embodiment, the storage amount of each cache block may be the same or different, and the more cache blocks that are used, the larger the storage amount is, and the specific number of the used storage blocks is, which is not limited in this embodiment; to accommodate the memory requirements of many algorithms, preferably 8 cache blocks may be used.
In this embodiment, the cache block with a small storage amount is adopted, and the requirement of different video data processing modes on the cache amount is met by a mode of overlapping a plurality of cache blocks, and the corresponding relations between different data processing modes and data transmission paths are preset, so that the purpose of different algorithms is achieved by different data transmission modes. Thus, a variety of different video processing algorithms can be supported without changing the cache organization of the hardware.
In this embodiment, different data processing modes correspond to different transmission paths, and the following embodiments 2 to 5 respectively introduce different transmission paths corresponding to different data processing modes:
referring to embodiment 2 below, when the video processing mode is the first video data processing mode, the transmission path of the first video data processing mode includes:
the controller sends video data to the first cache block 201 or the fifth cache block 205;
if the first cache block 201 receives video data, sending the video data to a second cache block 202 through a first data selector 301 connected to the first cache block 201, sending the video data to a third cache block 203 through a second data selector 302 connected to the second cache block 202, and sending the video data to a fourth cache block 204 through a third data selector 303 connected to the third cache block 203;
if the fifth cache block receives the video data, sending the video data to a sixth cache block through a fourth data selector connected with the fifth cache block, sending the data to a seventh cache block through the fifth data selector connected with the sixth cache block, and sending the data to an eighth cache block through the sixth data selector connected with the seventh cache block;
the first algorithm module 501 connected to the fourth cache block and the eighth cache block reads video data from the fourth cache block and the eighth cache block for interpolation processing.
Wherein the first and fifth buffer blocks may alternately receive video data.
For example: the first cache block stores a row of metadata and then transmits the metadata to the fifth cache block, and when the fifth cache block stores a row of metadata, the fifth cache block transmits the metadata to the first cache block.
Then, based on the transmission path described above, when performing bilinear interpolation operation, the metadata of the upper and lower lines can be simultaneously fetched for interpolation processing.
As can be seen from the above description, in the first video data processing mode, there are two transmission paths, respectively including:
a first path:
the data processing device comprises a first cache block, a first data selector, a second cache block, a second data selector, a third cache block, a third data selector and a fourth cache block.
A second path:
a fifth cache block, a fourth data selector, a sixth cache block, a fifth data selector, a seventh cache block, a sixth data selector, and an eighth cache block.
Referring to fig. 2, a transmission path of a single bilinear interpolation mode provided by an embodiment of the present invention is shown, in which only one of two transmission paths (i.e., the first path) is shown.
In fig. 2, an arrow indicates a transmission direction of data, wherein after video data is input to a first cache block, output data out0 is input to a second cache block through a first data selector, data out1 output from the second cache block is input to a third cache block through a second data selector, data out2 output from the third cache block is input to a fourth cache block through a third data selector, and a first algorithm module obtains data out3 from an interpolation operation.
In this embodiment, the first algorithm module may be an interpolation algorithm module including an interpolation program.
In this embodiment, the single bilinear interpolation processing can be realized by the data transmission path described above.
Referring to embodiment 3 below, when the video data processing module is in the second video data processing mode, the transmission path of the second video data processing mode includes:
the controller 100 transmits video data to the first or fifth cache blocks 201 or 205, respectively;
when a first cache block 201 receives video data, sending the video data to a second cache block 202 through a first data selector 301 connected with the first cache block 201, sending the video data to a third cache block 203 through a second data selector 302 connected with the second cache block 202, reading the video data from the third cache block by a second algorithm module 502 connected with the third cache block 203 and performing interpolation operation, sending a first result of interpolation operation to a first register 401, sending the first result of interpolation operation to a fourth cache block 204 through a third data selector 303 connected with the first register 401, and reading the first result from the fourth cache block 204 by a third algorithm module 503 connected with the fourth cache block 204 and performing interpolation operation;
when a fifth cache block receives data, sending the video data to a sixth cache block through a fourth data selector connected with the fifth cache block, sending the video data to a seventh cache block through the fifth data selector connected with the sixth cache block, reading the video data from the seventh cache block by a second algorithm module connected with the seventh cache block and carrying out interpolation operation, sending a second result of the interpolation operation to a second register, sending the second result to an eighth cache block through the sixth data selector connected with the second register, and reading the second result from the eighth cache block by the third algorithm module and carrying out interpolation operation.
In this embodiment, the first and fifth buffer blocks 201 and 205 may alternately receive video data.
For example: the first cache block stores a line of metadata and then sends the metadata to the fifth cache block, and when the fifth cache block stores a line of metadata, the metadata is sent to the first cache block.
In this embodiment, after video data is sent to a first cache block 201 and a fifth cache block 205, data transmission is performed through two different transmission paths, but the modules on the two transmission paths and the connection relationship between the modules are corresponding, fig. 3 provided in this embodiment shows a schematic diagram of a data transmission path in a twice bilinear reduction mode provided in the embodiment of the present invention, in which a transmission path of data after data is sent to the first cache block is shown, where a controller inputs video data into the first cache block 201, data out0 output by the first cache block 201 passes through a first data selector 301 and is sent to a second cache block 202, data out1 output by the second cache block passes through a second data selector 302 and is sent to a third cache block 203, a second algorithm module 502 obtains video data from the third cache block 203 and processes the video data, a processing result is stored in a first register connected to the second algorithm module 502, the first algorithm module 401 selects a processing result from the third cache block 203 and sends the processing result to a fourth cache block 401, and calculates a fourth data out result from a fourth cache block 401 and a fourth cache block 503.
In this embodiment, the second algorithm module and the third algorithm module may be set according to requirements, and in this embodiment, the second algorithm module and the third algorithm module are not limited, and preferably, the second algorithm module and the third algorithm module are interpolation algorithm modules including an interpolation operation program.
In this embodiment, the storage capacities of the first, second, third, fourth, fifth, sixth, seventh and eighth cache blocks may be the same or different.
In this embodiment, the processing procedure of reducing the resolution of the video image by bilinear interpolation is realized by the method of the above embodiment 3.
In embodiment 4, when the video data processing module is in the fourth video data processing mode, referring to fig. 4, a schematic diagram of a transmission path in the twice bilinear interpolation amplification mode according to an embodiment of the present invention is shown, and includes:
after the first cache block 201 receives the video data, the fifth algorithm module 505 connected to the first cache block 201 reads the video data from the first cache block 201 and performs interpolation operation, and sends an obtained third result to the third register 403 connected to the fifth algorithm module 505;
after the second cache block 202 receives the video data, a sixth algorithm module 506 connected to the second cache block 202 reads the video data from the second cache block 202 and performs interpolation operation, and sends a fourth result to a third register 403 connected to the sixth algorithm module 506;
the third result and the fourth result are sent to a third cache block 203 through a first data selector 303 connected with the third register 403, the received third result and fourth result are sent to a fourth cache block 204 through a second data selector 302 connected with the third cache block 203, and a seventh algorithm module 507 reads data from the fourth cache block 204 and performs interpolation operation on the read data;
after a fifth cache block receives video data, a fifth algorithm module connected with the fifth cache block reads the video data from the fifth cache block, performs interpolation operation, and sends a fifth result to a fourth register connected with the fifth algorithm module;
after the sixth cache block receives video data, a sixth algorithm module connected with the sixth cache block reads the video data from the sixth cache block and performs interpolation operation, and sends a sixth result to a fourth register connected with the sixth algorithm module;
and sending the fifth result and the sixth result to a seventh cache block through a third data selector connected with the fourth register, sending the received fifth result and the received sixth result to an eighth cache block through a fourth data selector connected with the seventh cache block, and reading data from the eighth cache block by an eighth algorithm module and performing interpolation operation on the read data.
In this embodiment, the first, second, fifth, and sixth cache blocks alternately read video data from the controller.
In this embodiment, the fourth video data processing mode includes two transmission paths, and after video data is sent to the first cache block and the second cache block, a transmission process of the data is a transmission path; after the video data is sent to the fifth cache block and the sixth cache block, the transmission process of the data is another transmission path, where the connection modes of the modules of the two transmission paths are corresponding, and referring to fig. 4, a data transmission path in the bilinear interpolation amplification mode is shown, including: after the first cache block 201 receives the video data, the fifth algorithm module is connected to the output of the first cache block 201, reads the video data out0 output from the first cache block 201, performs interpolation operation to obtain a third result, and sends the obtained third result to the third register 403 connected to the fifth algorithm module 505; the second buffer block 202 receives the video data sent by the controller 100, the sixth algorithm module 506 is connected to the output of the second buffer block 202, reads the video data in the data ou1 output by the second buffer block to obtain a fourth result, and stores the fourth result in the third register 403, the third register 403 sends the third result and the fourth result to the third buffer block through the first data selector 301 and sends the third result and the fourth result to the fourth buffer block 204 through the second data selector 302 connected to the third buffer block, and the seventh algorithm module 507 is connected to the output of the fourth buffer block 204, and can read the output data out3 from the fourth buffer block 204.
In this embodiment, the fifth algorithm module, the sixth algorithm module and the seventh algorithm module may be set according to requirements, and in this embodiment, the setting is not limited, and preferably, the fifth algorithm module and the sixth algorithm module are interpolation algorithm modules including an interpolation operation program.
In this embodiment, the storage capacities of the first, second, third, fourth, fifth, sixth, seventh and eighth cache blocks may be the same or different.
In this embodiment, the processing procedure of enlarging the resolution of the video image by bilinear interpolation is realized by the method of the above embodiment 4.
In embodiment 5, when the video data processing module is in the third video data processing mode, the transmission path in the third video data processing mode includes:
the controller 100 sends video data to a first cache block 201, a third cache block 203, a fifth cache block 205 or a seventh cache block 207, respectively;
after a first cache block 201 receives video data, the video data is sent to a second cache block 202 through a first data selector 301 connected to the first cache block 201;
after the third cache block 203 receives the video data, the video data is sent to the fourth cache block 204 through the second data selector 302 connected to the third cache block 203;
a fourth algorithm module 504, connected to the second cache block 201 and the fourth cache block 204 respectively, for reading video data from the second cache block 202 and the fourth cache block 204 and performing interpolation operation;
after a fifth cache block receives video data, the video data is sent to a sixth cache block through a fourth data selector connected with the fifth cache block;
after receiving the video data, the seventh cache block sends the video data to an eighth cache block through a sixth data selector connected with the seventh cache block;
and the fourth algorithm module is respectively connected with the fifth cache block and the eighth cache block and is used for reading the video data from the fourth cache block and the eighth cache block and carrying out interpolation operation.
In this embodiment, the first cache block, the third cache block, the fifth cache block, or the seventh cache block alternately receives video data transmitted by the controller.
In this embodiment, the provided third video data processing mode includes two transmission paths, and after the video data is sent to the first cache block and the third cache block, a transmission process of the data is a transmission path; after the video data is sent to the fifth cache block and the seventh cache block, the transmission process of the data is another transmission path, where the connection modes of the modules of the two transmission paths are corresponding, and referring to fig. 5, a data transmission path in a dual cubic interpolation mode provided by an embodiment of the present invention is shown, including:
after the first cache block 201 receives the video data, the video data is sent to the second cache block 202 through the first data selector 301; after the third cache block 203 receives the video data, the video data is sent to the fourth cache block 204 through the second data selector 302; a fourth algorithm module 504, connected to the second cache block 201 and the fourth cache block 204 respectively, reads the video data from the second cache block 202 and the fourth cache block 204 and performs interpolation operation.
In this embodiment, the fourth algorithm module may be set according to a requirement, and is not limited in this embodiment, and preferably, the fourth algorithm module may be an interpolation algorithm module including an interpolation operation program.
In this embodiment, the storage capacities of the first, second, third, fourth, fifth, sixth, seventh and eighth cache blocks may be the same or different.
In this embodiment, the dual cubic interpolation mode is implemented by the method of embodiment 5.
Referring to fig. 6, a schematic flow chart of a video data processing method according to an embodiment of the present invention is shown, where the method includes:
s601: receiving a video to be processed;
s602: detecting basic information of the video to be processed and acquiring output basic information;
s603: determining a video data processing mode based on basic information of a video to be processed and output basic information;
s604: the video data processing apparatus disclosed in the above embodiments 1 to 5 processes the video to be processed based on the video data processing mode.
In this embodiment, the transmission path of video data is disclosed in embodiments 1 to 5, which are not described in detail herein.
The video processing modes that can be implemented in this embodiment at least include: single bilinear interpolation, two bilinear interpolations for amplification, two bilinear interpolations for reduction, bicubic interpolation and the like.
The method of the embodiment can realize the conversion of input and output videos in different modes, the video data processing device adopts the cache block with smaller memory space, meets the requirements of different video data processing modes on the cache space by the mode of overlapping a plurality of cache blocks, and also presets the corresponding relation between different data processing modes and data transmission paths, thereby realizing the purposes of different algorithms by different data transmission modes. Thus, a variety of different algorithms may be supported without changing the cache organization of the hardware.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A video data processing apparatus, comprising:
the system comprises a controller, a plurality of cache blocks, a plurality of registers, a plurality of data selectors and an algorithm module;
the controller is respectively connected with each cache block;
each buffer block is respectively connected with the input and the output of the data selector;
each register is respectively connected with the input and the output of each data selector;
each cache block is connected with each algorithm module respectively;
each register is respectively connected with each algorithm module;
the controller is used for acquiring a data transmission path corresponding to the data processing mode when the video data processing mode is determined, and sending the video data to a corresponding cache block according to the data transmission path;
the algorithm module is used for reading video data from the buffer block according to algorithm requirements and performing interpolation processing on the read video data;
the register is used for storing the operation result output by the algorithm module and sending the output operation result to the corresponding cache block through the data selector;
the buffer block is used for receiving the video data and transmitting the video data according to the data transmission path sent by the controller.
2. The video data processing apparatus according to claim 1, wherein when the video data processing mode is a first video data processing mode, the transmission path of the first video data processing mode includes:
the controller sends the video data to the first cache block or the fifth cache block;
if the first cache block receives video data, sending the video data to a second cache block through a first data selector connected with the first cache block, sending the video data to a third cache block through a second data selector connected with the second cache block, and sending the video data to a fourth cache block through a third data selector connected with the third cache block;
if the fifth cache block receives the video data, sending the video data to a sixth cache block through a fourth data selector connected with the fifth cache block, sending the data to a seventh cache block through the fifth data selector connected with the sixth cache block, and sending the data to an eighth cache block through the sixth data selector connected with the seventh cache block;
and a first algorithm module connected with the fourth cache block and the eighth cache block reads video data from the fourth cache block and the eighth cache block for interpolation processing.
3. The video data processing apparatus according to claim 1, wherein when the video data processing module is in the second video data processing mode, the transmission path of the second video data processing mode includes:
the controller respectively sends the video data to a first cache block or a fifth cache block;
after a first cache block receives video data, sending the video data to a second cache block through a first data selector connected with the first cache block, sending the video data to a third cache block through a second data selector connected with the second cache block, reading the video data from the third cache block by a second algorithm module connected with the third cache block and carrying out interpolation operation, sending a first result of the interpolation operation to a first register, sending the first result to a fourth cache block through a third data selector connected with the first register, and reading the first result from the fourth cache block by the third algorithm module and carrying out interpolation operation;
when a fifth cache block receives data, sending the video data to a sixth cache block through a fourth data selector connected with the fifth cache block, sending the video data to a seventh cache block through the fifth data selector connected with the sixth cache block, reading the video data from the seventh cache block by a second algorithm module connected with the seventh cache block and carrying out interpolation operation, sending a second result of the interpolation operation to a second register, sending the second result to an eighth cache block through the sixth data selector connected with the second register, and reading the second result from the eighth cache block by the third algorithm module and carrying out interpolation operation.
4. The video data processing apparatus according to claim 1, wherein when the video data processing module is in the third video data processing mode, the transmission path of the third video data processing mode includes:
the controller respectively sends the video data to a first cache block, a third cache block, a fifth cache block or a seventh cache block;
after a first cache block receives video data, the video data is sent to a second cache block through a first data selector connected with the first cache block;
after the third cache block receives video data, the video data is sent to a fourth cache block through a second data selector connected with the third cache block;
the fourth algorithm module is respectively connected with the second cache block and the fourth cache block, and is used for reading video data from the second cache block and the fourth cache block and carrying out interpolation operation;
after a fifth cache block receives video data, the video data is sent to a sixth cache block through a fourth data selector connected with the fifth cache block;
after the seventh cache block receives the video data, the video data is sent to an eighth cache block through a sixth data selector connected with the seventh cache block;
and the fourth algorithm module is respectively connected with the fifth cache block and the eighth cache block and is used for reading the video data from the fourth cache block and the eighth cache block and carrying out interpolation operation.
5. The apparatus according to claim 1, wherein when the video data processing module is in a fourth video data processing mode, the transmission path of the fourth video data processing mode comprises:
the controller respectively sends video data to a first cache block, a second cache block, a fifth cache block and a sixth cache block;
after the first cache block receives video data, a fifth algorithm module reads the video data from the first cache block and performs interpolation operation, and sends an obtained third result to a third register connected with the fifth algorithm module;
after the second cache block receives video data, a sixth algorithm module connected with the second cache block reads the video data from the second cache block and performs interpolation operation, and sends a fourth result to a third register connected with the sixth algorithm module;
the third result and the fourth result are sent to a third cache block through a first data selector connected with the third register, the received third result and the received fourth result are sent to a fourth cache block through a second data selector connected with the third cache block, and a seventh algorithm module reads data from the fourth cache block and performs interpolation operation on the read data;
after a fifth cache block receives video data, a fifth algorithm module connected with the fifth cache block reads the video data from the fifth cache block, performs interpolation operation, and sends a fifth result to a fourth register connected with the fifth algorithm module;
after the sixth cache block receives video data, a sixth algorithm module connected with the sixth cache block reads the video data from the sixth cache block and performs interpolation operation, and sends a sixth result to a fourth register connected with the sixth algorithm module;
and sending the fifth result and the sixth result to a seventh cache block through a third data selector connected with the fourth register, sending the received fifth result and the received sixth result to an eighth cache block through a fourth data selector connected with the seventh cache block, and reading data from the eighth cache block by an eighth algorithm module and performing interpolation operation on the read data.
6. A method of processing video data, comprising:
receiving a video to be processed;
detecting basic information of the video to be processed and acquiring output basic information;
determining a video data processing mode based on basic information of a video to be processed and output basic information;
triggering the video data processing apparatus of claim 1 to process the video to be processed based on the video data processing mode.
7. The method according to claim 6, wherein the basic information of the video to be processed comprises: a resolution of the video to be processed.
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| KR101034778B1 (en) * | 2004-09-23 | 2011-05-17 | 삼성전자주식회사 | Method of interpolation, computer readable medium storing thereof, apparatus for performing the same, display device, and apparatus and method for driving thereof |
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