CN101022546A - Interpolation arithmetic device and method - Google Patents
Interpolation arithmetic device and method Download PDFInfo
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Abstract
An operation device of interpolation is prepared as connecting bus interface, data storage unit, multi-path selector, data operation module, intermediate data buffer and data selection module all to controller and then receiving generated control signal of said controller by all said units connected with said controller.
Description
Technical field
The present invention relates to video file encoding and decoding field, especially relate to a kind of interpolation arithmetic device and method of in the video image encoding and decoding process, carrying out motion compensation.
Background technology
Digital video technology is widely used in fields such as communication, computer, radio and television, portable player, and what produce is the encoding and decoding standard of various video files thereupon, for example, MPEG2, MPEG4, H.264, VC-1 and AVS or the like.The application of these standards emphasizes particularly on different fields and is overlapped, and for example, the MPEG series standard is by more video storage, the field of broadcast televisions of being applied in; H.264 the Streaming Media field that is applied in real-time video communication, internet that standard is then more; VC-1 is mainly used on windows platform and the portable video; AVS is mainly used in high sharpness video transmission and storage application.Because various video standard and the situation of depositing can't disappear at short notice, if can realize multiple encoding and decoding standard in the coding/decoding system, the cost that increases thus is again in a controlled scope simultaneously, this can make corresponding product satisfy the demand of more areas so, thereby provide more vast market space for product.It is therefore, this that to possess strong compatible coding/decoding system be one of target of striving for of industry always.
On the other hand, in existing encoding and decoding field, the compress technique of all kinds of video files all is based on the motion video sequence to be had this feature of correlation and designs on room and time, the principle of compression generally is to utilize discrete cosine transform in the frame, quantification, entropy coding and infra-frame prediction to eliminate the spatial coherence of pixel in the same frame, utilize the temporal correlation that interframe movement is estimated, motion compensation technique is eliminated the interframe pixel, realize data compression.Referring to illustrated in figures 1 and 2, Fig. 1 shows a kind of comparatively typical cataloged procedure of the prior art, and Fig. 2 then shows a kind of comparatively typical decode procedure of the prior art, because these two processes are known prior art, does not give unnecessary details at this.In the Code And Decode process that Fig. 1 and Fig. 2 disclosed, interpolation arithmetic is the major part in the motion compensation process, it also is a bigger part of amount of calculation in the whole encoding-decoding process, therefore for improving the performance of whole coding/decoding system, designing a kind of interpolation arithmetic device, it is carried out special processing is very necessary.Yet, because MPEG2, MPEG4, H.264, interpolation arithmetic processing mode in the standard such as VC-1 and AVS has nothing in common with each other, if adopt a plurality of discrete interpolation arithmetic devices to adapt to various criterion, to make that then the structure of coding/decoding system is very complicated, though the compatibility of coding/decoding system is improved, but chip area will increase, and cost also can increase, and such defective obviously can reduce the competitiveness of product on market, especially in the portable player field, volume is little, the cost performance height is the main flow trend on the market.
Therefore, make full use of the common feature that has in the interpolation arithmetic processing of each encoding and decoding standard, by resource sharing, optimization process structure and control strategy design a kind of interpolation arithmetic device that can compatible various video coding standard and have big realistic meaning.
Summary of the invention
First purpose of the present invention provides a kind of interpolation arithmetic device that can carry out interpolation arithmetic under the various video encoding and decoding standard;
Second purpose of the present invention provides a kind of interpolation arithmetic method that can be applied to the various video encoding and decoding standard.
For realizing above-mentioned first purpose, interpolation arithmetic device interpolation arithmetic device of the present invention comprises:
Bus interface, it finishes the communication of external bus and internal data;
Controller, it produces multi-way control signals;
Data storage cell, an one input connects above-mentioned bus interface;
MUX, an one input connects the output of data storage cell;
The data operation module, this data operation module comprises data delay device, multiplier array and addition, displacement and the saturated processor of polyphone successively, the input of data delay device connects the output of MUX, and the input of addition, displacement and saturated processor connects the output of data storage cell;
It is characterized in that:
The intermediate data buffer, its output connects another input of MUX; And
Data are selected module, and these data select module to comprise:
The multichannel selected cell, it comprises a plurality of inputs and output, the output of above-mentioned data delay device, addition, displacement and saturated processor, data storage cell and the output of intermediate data buffer are connected to a plurality of inputs that data are selected module respectively, and the output of multichannel selected cell is connected to the input of intermediate data buffer and another input of data storage cell respectively;
Mean value and reconstruction operation unit, it is connected with above-mentioned multichannel selected cell;
Above-mentioned bus interface, data storage cell, MUX, data operation module, intermediate data buffer and data are selected module all to be connected with controller and are received the control signal of its generation.
With crossing the foregoing circuit structure, interpolation arithmetic device provided by the present invention can be finished MPEG2, MPEG4, H.264, the interpolation arithmetic of various video such as VC-1 and AVS encoding and decoding standard on the basis of resource sharing, has the advantage of optimization process structure and control strategy.
For realizing above-mentioned second purpose, interpolation arithmetic method of the present invention may further comprise the steps:
Step 1, according to interpolative mode, data storage cell (120) is exported the interpolation pixel data successively under controller (150) control;
Step 2, according to interpolative mode, a plurality of pending data that data delay device (141) output is suitable.
Step 3, according to interpolative mode, multiplier array (142) uses suitable coefficient to carry out corresponding filtering operation.
Step 4, addition, displacement and saturated processor (143) carry out accumulating operation, and to accumulation result round off computing and saturation arithmetic, this accumulating operation comprises: the accumulating operation that the two or more corresponding multiplication result of multiplier array 142 output is carried out, and be 5 sub-pixel interpolation pattern above accumulation result and accumulating operation from the dateout of data storage 120 when selected in the AVS type;
Step 5, according to interpolative mode, data select module (170) to select correct data to carry out corresponding mean value operation and/or reconstruction operation.
Step 6, according to interpolative mode, data select module (170) successively result to be outputed to corresponding memory device.
Step 7 judges whether interpolation finishes, if do not finish then return to re-execute step 1, if interpolation finishes, then termination routine provides the processing end mark.
Interpolation arithmetic method provided by the present invention can realize MPEG2 by resource sharing, MPEG4, and H.264, the interpolation arithmetic of various video encoding and decoding standards such as VC-1 and AVS has the advantage of optimization process structure and control strategy.
Concrete execution mode will be introduced in following embodiment in detail.
Description of drawings
Fig. 1 is a kind of comparatively typical cataloged procedure of the prior art;
Fig. 2 is a kind of comparatively typical decode procedure of the prior art;
Fig. 3 is the electrical block diagram of interpolation arithmetic device of the present invention;
Fig. 4 is a kind of execution mode of data storage cell internal structure among Fig. 3;
Fig. 5 is a kind of execution mode that data are selected the inside modules structure among Fig. 3;
Fig. 6 is that interpolation arithmetic device of the present invention adopts the structural representation after the data selection module among Fig. 5;
Fig. 7 is the interpolation process of interpolation arithmetic device of the present invention at the MPEG2 video encoding and decoding standard;
Fig. 8 is the interpolation process of interpolation arithmetic device of the present invention at the MPEG4 video encoding and decoding standard;
Fig. 9 is an interpolation arithmetic device of the present invention at the interpolation process of video encoding and decoding standard H.264;
Figure 10 is the interpolation process of interpolation arithmetic device of the present invention at the VC-1 video encoding and decoding standard;
Figure 11 is the interpolation process of interpolation arithmetic device of the present invention at the AVS video encoding and decoding standard;
Figure 12 is the flow chart of interpolation arithmetic method of the present invention.
Be described in further detail below in conjunction with embodiment and accompanying drawing thereof.
Embodiment
Interpolation arithmetic device of the present invention can be applicable to MPEG2, MPEG4, H.264, in the encoding-decoding process of various video encoding and decoding standards such as VC-1 and AVS.Referring to Fig. 3, the interpolation arithmetic device 100 that the present invention discloses comprises bus interface 110, data storage cell 120, MUX 130, data operation module 140, controller 150, intermediate data buffer 160 and data selection module 170, wherein, data select module 170 to comprise multichannel selected cell 178 and mean value and reconstruction operation unit 179.
Referring to Fig. 4, disclosed a kind of execution mode of data storage cell 120 internal structures among Fig. 4, data selector 123,124,125,126 shows that by Fig. 4 mode is connected the input and the output of data storage 121 and data storage 122.Write access A is the input signal channel from multichannel selected cell 178, and read channel A ' is for exporting to the output signal channel of MUX 130; Write access B is the input signal channel from bus interface 110, and read channel B ' is for exporting to the output signal channel of bus interface 110.The control signal control that write access A and read channel A ' are sent by controller 150, and write access B and read channel B ' are controlled by bus interface 110 guarantees that simultaneously controller 150 can not control identical data storage simultaneously with bus interface 110.When controller 150 passed through the data of read channel reading of data memory 121, bus interface 110 control data memory 122 simultaneously be carried out the input of next reference data piece.And same process can be exchanged between data storage 121 and data storage 122.Periodically, after in present clock, reading pending data from data storage 121 or data storage 122, at next clock two kinds of situations will be arranged: perhaps an interpolation result of having handled will be written to same data storage, and perhaps the intermediate object program of an interpolation is written to intermediate data buffer 160.The selection of above situation enables decision by the read-write of internal controller 150 control data memories 120 and intermediate data buffer 160.
Controller 150 can comprise the generative circuit of control register, data storage read-write and be used to control (figure do not show) such as generative circuits of inner other each unit controls signals.Control signal annexation between controller 150 and each element below makes introductions all round.
Two inputs of MUX 130 connect the output of data storage cell 120 and the output of intermediate data buffer 160 respectively.MUX 130 is connected with controller 150 and receives the selection signal that is produced by controller 150.
Data select module 170 to comprise multichannel selected cell 178 and mean value and reconstruction operation unit 179, data select module 170 to handle the mean value operation and/or the reconstruction operation of final stage in the interpolation processing process of all standards by mean value and reconstruction operation unit 179, and by multichannel selected cell 178 under the control of the control signal that controller 150 is sent, select correct transmission path so that result outputs to corresponding memory.Data select module 170 to comprise four groups of input signals, respectively from the output signal of data storage 120, and the output signal of data delay device 141, the output signal of addition, displacement and saturator 143, and the output signal of intermediate data buffer 160; Data are selected two groups of output signals of module 170 outputs, respectively as the input signal of data storage 120 and intermediate data buffer 160.
The control signal of multichannel selected cell 178 and mean value and reconstruction operation unit 179 is come self-controller 150, has comprised brightness, colourity sign and weight estimation parameter in the control signal.
Referring to Fig. 5, Fig. 5 has disclosed a kind of embodiment of data selection module 170 internal structures.After being reflected among Fig. 5, multichannel selected cell 178 among Fig. 4 can comprise five MUX 171,172,173,174,175.Mean value and reconstruction operation unit 179 described in reconstruction operation unit 176,177 composition diagrams 4 of mean value operating unit.H.264 mean value operating unit 177 is used to handle all types with mpeg 4 standard is 3,4 and 5 sub-pixel interpolation computing; Reconstruction operation unit 176 is used to handle forward direction and the back reconstruction computing when two reference data piece interpolation results of all standards.Reconstruction computing in the reconstruction operation unit 176 comprised H.264 with the AVS standard in the weight estimation calculating section that requires, and to import as it from the brightness of internal controller or colourity sign and weight estimation parameter.Each MUX 171,172,173,174,175 is input to pending data in mean value operating unit 177 and the reconstruction operation unit 176 under the control of controller 150, and result is transferred to corresponding memory device by correct path.
After the data that Fig. 5 is shown select module 170 to be applied in the interpolation arithmetic device of the present invention 100 that shows as Fig. 3, can obtain the interpolation arithmetic device 101 that Fig. 6 shows, obviously, those skilled in the art can select concrete data to select module 170 according to design of the present invention.
The read-write control signal of intermediate data buffer 160 derives from controller 150, writes data from multichannel selected cell 178, and institute's sense data exports data to and selects the input of module 170 and one of them input of MUX 130.
It more than is description to hardware configuration involved in the present invention, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 have then disclosed respectively on the basis of hardware configuration of the present invention and have realized MPEG2, MPEG4, H.264, the process of the interpolation arithmetic in five kinds of exemplary video encoding and decoding standards of VC-1 and AVS, and in Figure 12, summarize interpolation arithmetic method involved in the present invention.Because the interpolation arithmetic process of above-mentioned five kinds of standards is similar substantially, below only emphasis at Fig. 7 the interpolation process of MPEG2 video encoding and decoding standard is described in detail.
Referring to Fig. 7, interpolation arithmetic device 101 is as follows at the interpolation process of MPEG2 video encoding and decoding standard:
Earlier the reference data piece with the MPEG2 decoding writes data storage cell 120, opens interpolation processing then, judges the sub-pix type in step 71, if the sub-pix type is 3-5, does not then carry out any operation, the scope that does not belong to the present invention and implemented.If frame type is B frame and sub-pix type is 1, then execution in step 72, select data storage cell 120 by MUX 130, read in 16 bit data; The direction of judging interpolation then in step 73 is horizontal interpolation or vertical interpolation, if horizontal interpolation, then execution in step 731, the parallel displacement of 8 bit data in the data delay device 141, and the maximum shift of data is that 4 times and 8 bit data of selecting last three adjacent delays are as output; If vertical direction interpolation, the parallel displacement of 16 bit data in the data delay device 141, the maximum shift of data be 3 times and select displacement 2 times and 3 times 16 bit data as output.
After completing steps 731 or step 732, equal execution in step 74, multiplier array 142 carries out the coefficient multiplying in the bilinearity filtering, execution in step 75 then, the accumulating operation that addition, displacement and saturated processor 143 carry out in the bilinearity filtering, the addition of rounding (computing of rounding off) and shifting function and saturated processing made to obtain two 8 interpolation result in two clock cycle; Execution in step 76 then, judge whether to be last reference block interpolation, if last reference block interpolation, then execution in step 761, MUX 171 selects data from intermediate data buffer 160 as output E, execution in step 77 then, MUX 175 selects data from addition, displacement and saturated processor 143 as output, reconstruction operation unit 176 carries out reconstruction operation, the data that MUX 177 is selected reconstruction operation unit 176 are as output, and MUX 173 selects the output of MUX 174 as output.Execution in step 78 then, and data are write back to data storage cell 120, judge in step 79 then whether all data are handled, if also have data to be untreated, then return execution in step 72, if all data are all handled, then the end of output sign finishes interpolation.
If the judged result of step 76 is for denying, promptly, be not to be last reference block interpolation, then execution in step 762, and data are write back to intermediate data buffer 160, and judge in step 763 whether all data are handled, if judged result is " YES ", then return execution in step 71,, then return execution in step 72 if judged result is " NO ".
About the interpolation process of the MPEG4 among Fig. 8, among Fig. 9 interpolation process H.264, the interpolation process of VC-1 among Figure 10 and the AVS among Figure 11 interpolation process all with Fig. 7 in the interpolation process of MPEG2 similar, do not give unnecessary details at this.It is emphasized that, interpolation arithmetic device of the present invention and method can only be handled the sub-pix type when carrying out interpolation at MPEG2 be 1 and 2 situation, therefore need to judge the sub-pix type before the interpolation,, then do not carry out interpolation arithmetic if the sub-pix type is not 1 or 2.At the then applicable any sub-pix type of the interpolation arithmetic of other form.
Figure 12 summarizes interpolation arithmetic method of the present invention according to the interpolation process of above-mentioned five kinds of video standards:
After the beginning interpolation processing, at first execution in step 180, and according to interpolative mode, data storage cell 120 is exported the interpolation pixel data successively under controller 150 controls;
Step 186 judges whether interpolation finishes, if do not finish then return to re-execute step 180, if interpolation finishes, then termination routine provides the processing end mark.
The present invention is not limited only to the described execution mode of the foregoing description; for those skilled in the art; the present invention also exists the simple malformation of other; for example; H.263 interpolation arithmetic device of the present invention and method can also be applicable to and H.261 wait in the encoding and decoding standard, and suchlike minor alteration and equivalent transformation all should be included within the scope that claim of the present invention protects.
Claims (3)
1, interpolation arithmetic device comprises:
Bus interface (110), it finishes the communication of external bus and internal data;
Controller (150), it produces multi-way control signals;
Data storage cell (120), an one input connects above-mentioned bus interface (110);
MUX (130), an one input connects the output of data storage cell (120);
Data operation module (140), this data operation module (140) comprises data delay device (141), multiplier array (142) and addition, displacement and the saturated processor (143) of polyphone successively, the input of data delay device (141) connects the output of MUX (130), and the input of addition, displacement and saturated processor (143) connects the output of data storage cell (120);
It is characterized in that:
Intermediate data buffer (160), its output connects another input of MUX (130); And
Data are selected module (170), and these data select module (170) to comprise:
Multichannel selected cell (178), it comprises a plurality of inputs and output, the output of above-mentioned data delay device (141), addition, displacement and saturated processor (143), data storage cell 120 and the output of intermediate data buffer (160) are connected to a plurality of inputs that data are selected module (170) respectively, and the output of multichannel selected cell (178) is connected to the input of intermediate data buffer (160) and another input of data storage cell (120) respectively;
Mean value and reconstruction operation unit (179), it is connected with above-mentioned multichannel selected cell (178);
Above-mentioned bus interface (110), data storage cell (120), MUX (130), data operation module (140), intermediate data buffer (160) and data are selected module (170) all to be connected with controller (150) and are received the control signal of its generation.
2, interpolation arithmetic device according to claim 1 is characterized in that: described data storage cell (120) comprises two data memories (121,122).
3, according to the interpolation arithmetic method of the described interpolation arithmetic device of claim 1, may further comprise the steps:
Step 1, according to interpolative mode, data storage cell (120) is exported the interpolation pixel data successively under controller (150) control;
Step 2, according to interpolative mode, a plurality of pending data that data delay device (141) output is suitable.
Step 3, according to interpolative mode, multiplier array (142) uses suitable coefficient to carry out corresponding filtering operation.
Step 4, addition, displacement and saturated processor (143) carry out accumulating operation, and to accumulation result round off computing and saturation arithmetic, this accumulating operation comprises: the accumulating operation that the two or more corresponding multiplication result of multiplier array 142 output is carried out, and be 5 sub-pixel interpolation pattern above accumulation result and accumulating operation from the dateout of data storage 120 when selected in the AVS type;
Step 5, according to interpolative mode, data select module (170) to select correct data to carry out corresponding mean value operation and/or reconstruction operation.
Step 6, according to interpolative mode, data select module (170) successively result to be outputed to corresponding memory device.
Step 7 judges whether interpolation finishes, if do not finish then return to re-execute step 1, if interpolation finishes, then termination routine provides the processing end mark.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686392B (en) * | 2008-09-24 | 2011-06-08 | 安凯(广州)微电子技术有限公司 | Image interpolation method, mobile multimedia processor and multimedia player terminal |
| CN102348114A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Intra predictor structure in multimode video decoder |
| CN106507118A (en) * | 2016-11-28 | 2017-03-15 | 济南浪潮高新科技投资发展有限公司 | A kind of bimodulus brightness interpolating filter structure and method |
| CN113365015A (en) * | 2021-05-31 | 2021-09-07 | 龙迅半导体（合肥）股份有限公司 | Video data processing device and method |
-
2006
- 2006-10-01 CN CNB2006101226392A patent/CN100486333C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686392B (en) * | 2008-09-24 | 2011-06-08 | 安凯(广州)微电子技术有限公司 | Image interpolation method, mobile multimedia processor and multimedia player terminal |
| CN102348114A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Intra predictor structure in multimode video decoder |
| CN102348114B (en) * | 2010-07-30 | 2013-12-04 | 中国科学院微电子研究所 | Intra predictor structure in multimode video decoder |
| CN106507118A (en) * | 2016-11-28 | 2017-03-15 | 济南浪潮高新科技投资发展有限公司 | A kind of bimodulus brightness interpolating filter structure and method |
| CN106507118B (en) * | 2016-11-28 | 2019-10-11 | 浪潮集团有限公司 | A kind of bimodulus brightness interpolating filter structure and method |
| CN113365015A (en) * | 2021-05-31 | 2021-09-07 | 龙迅半导体（合肥）股份有限公司 | Video data processing device and method |
| CN113365015B (en) * | 2021-05-31 | 2022-10-11 | 龙迅半导体（合肥）股份有限公司 | Video data processing device and method |
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Address after: 519085 hi tech Zone, Guangdong, Zhuhai science and Technology Innovation Coast Road, No. four, No. 1 Patentee after: Juli Integrated Circuit Design Co., Ltd. Address before: 519085, No. 1, Da Ha Road, Tang Wan Town, Guangdong, Zhuhai, -15-A101 Patentee before: Juli Integrated Circuit Design Co., Ltd. |
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