CN113363226A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113363226A
CN113363226A CN202010147264.5A CN202010147264A CN113363226A CN 113363226 A CN113363226 A CN 113363226A CN 202010147264 A CN202010147264 A CN 202010147264A CN 113363226 A CN113363226 A CN 113363226A
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substrate
layer
forming
power rail
metal layer
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, forming a fin part and an isolation layer on the substrate, and etching the isolation layer and the substrate with partial thickness to form a power rail opening; continuously etching the substrate with partial thickness along the opening of the power rail to form a through hole; forming a first sacrificial layer in the power rail opening and the through hole; etching back the first sacrificial layer until the height of the first sacrificial layer accounts for 20% -80% of the height of the through hole; forming a first metal layer in the power rail opening and the through hole; thinning the back surface of the substrate until the first sacrificial layer is exposed from the back surface of the substrate; removing all the first sacrificial layers to expose the back surface of the first metal layer; and forming a second metal layer on the back surface of the first metal layer, wherein the back surface of the second metal layer is flush with the back surface of the substrate. According to the forming method of the semiconductor structure provided by the embodiment of the invention, the filling of the through hole with the high depth-to-width ratio can be realized while the back power distribution is formed, so that the performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor chips are developed to a higher integration level in order to achieve faster operation speed, larger data storage capacity, and more functions. The higher the integration of semiconductor chips, the smaller the Critical Dimension (CD) of the semiconductor device.
The power rail is used to supply power (e.g., V) to standard cells in an integrated circuitSS、VDD) Low resistance connection. Due to the continuous miniaturization of standard cells, a buried power rail partially embedded in a substrate is introduced into the standard cell, however, since the RC in the back end of the line is becoming higher as the technology node advances further, the buried power rail alone cannot provide enough power support, and therefore, a power distribution structure needs to be formed on the back side of the semiconductor wafer to provide enough power support for the standard cell.
Through Silicon Via (TSV) technology is a new integrated circuit manufacturing technology, a circuit manufactured on the upper surface of a silicon chip can be connected to the back surface of the silicon chip through metal filled in the TSV, and a back power distribution semiconductor structure can be formed by combining the TSV technology.
However, the quality of the metal layer filled in the high aspect ratio through silicon via still needs to be improved, thereby affecting the electrical performance of the semiconductor structure.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor structure and a forming method thereof, which can improve the alignment precision of an interconnection structure on the back of a semiconductor substrate and a power supply rail, and can realize metal filling of a through hole with a high depth-to-width ratio, thereby improving the electrical property of the filled through hole and improving the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent, and a plurality of fin parts are formed on the front surface of the substrate in the first area; forming an isolation layer on the front surface of the substrate, wherein the top of the isolation layer is higher than the top of the fin part; etching the isolation layer of the second area and the substrate with partial thickness to form a power rail opening; continuously etching the substrate with partial thickness along the power rail opening to form a through hole; forming a first sacrificial layer in the power rail opening and the through hole; etching back the first sacrificial layer until the height of the first sacrificial layer accounts for 20% -80% of the height of the through hole; forming a first metal layer in the power rail opening and the through hole; thinning the back surface of the substrate until the first sacrificial layer is exposed from the back surface of the substrate; removing all the first sacrificial layers to expose the back surface of the first metal layer; and forming a second metal layer on the back surface of the first metal layer, wherein the back surface of the second metal layer is flush with the back surface of the substrate.
Optionally, after forming the second metal layer, the method further includes: and etching back the back surface of the substrate to enable the back surface of the second metal layer to be higher than the back surface of the substrate.
Optionally, the material of the first sacrificial layer includes silicon dioxide, silicon nitride, or silicon carbide.
Optionally, a method for forming the first sacrificial layer includes a spin coating method, a chemical vapor deposition method, or an atomic layer deposition method.
Optionally, the method for etching back the first sacrificial layer includes one or two of a dry etching process and a wet etching process.
Optionally, the method for forming the through hole includes: forming a second sacrificial layer in the power rail opening, wherein the second sacrificial layer covers the surface of the isolation layer; forming a mask layer on the second sacrificial layer, wherein the mask layer exposes the second sacrificial layer above the power rail opening; etching the second sacrificial layer by taking the mask layer as a mask until the substrate at the bottom of the power rail opening is exposed; and continuously etching the substrate with partial thickness along the power rail opening to form a through hole.
Optionally, the material of the second sacrificial layer includes a carbon-containing compound or a spin-on oxide.
Optionally, the width of the through hole in the direction parallel to the extending direction of the fin portion is greater than or equal to the width of the through hole in the direction perpendicular to the extending direction of the fin portion.
Optionally, the step of forming the first metal layer includes: filling a first metal film in the opening of the power rail and the through hole, wherein the first metal film covers the surface of the isolation layer; carrying out chemical mechanical polishing on the first metal film until the top of the first metal film is flush with the surface of the top of the isolation layer; and etching back the first metal film to form a first metal layer.
Optionally, the material of the first metal layer includes copper, cobalt, tungsten, ruthenium, titanium, aluminum, magnesium, or an intermetallic compound formed by a plurality of metals thereof, or titanium nitride or copper manganese.
Optionally, the material of the second metal layer includes copper, cobalt, tungsten, ruthenium, titanium, aluminum, magnesium, or an intermetallic compound formed by a plurality of metals thereof, or titanium nitride or copper manganese.
Optionally, before thinning the back surface of the substrate, the method further includes: and providing a support substrate, and bonding the front surface of the substrate with the support substrate.
Optionally, before forming the first sacrificial layer, the method further includes: and forming a first insulating layer on the side wall of the opening of the power rail, the side wall of the through hole and the bottom surface.
Optionally, after forming the power rail opening and before forming the through hole, the method further includes: and forming a power rail opening insulating layer on the side wall and the bottom surface of the power rail opening.
Optionally, the first insulating layer is of a single-layer structure or a multi-layer structure.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above forming method, including: the substrate comprises a first area and a second area which are adjacent, and the front surface of the substrate in the first area is provided with a plurality of fin parts; the isolation layer is positioned on the substrate between the adjacent fin parts, and the top of the isolation layer is lower than the surface of the top of each fin part; a power rail opening located within the isolation layer and the substrate of the second region; a through hole in the substrate below the power rail opening; the first metal layer is positioned in the power rail opening and part of the through hole; and the second metal layer is positioned on the back surface of the first metal layer, and the back surface of the second metal layer is higher than the back surface of the substrate.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
after the power rail opening is formed, the substrate with partial thickness is continuously etched along the power rail opening to form a through hole, a first sacrificial layer is formed in the through hole, then the first sacrificial layer is etched back until the height of the first sacrificial layer accounts for 20% -80% of the height of the through hole, the first sacrificial layer with a certain height is reserved at the bottom of the through hole, and when a first metal layer is filled in the power rail opening and the through hole subsequently, due to the existence of the first sacrificial layer, the height of the through hole to be filled is reduced, namely the depth-to-width ratio of the through hole to be filled is reduced, the filling of the through hole with a high depth-to-width ratio can be realized, the quality of the filled first metal layer is improved, and the performance of the semiconductor structure is improved. And then the back of the substrate is thinned to expose the first sacrificial layer, the first sacrificial layer is removed to expose the back of the first metal layer, a second metal layer is formed on the back of the first metal layer, and a back power distribution structure is formed through the second metal layer, so that sufficient power support can be provided for the semiconductor device.
Furthermore, the back surface of the substrate is etched back, so that the back surface of the second metal layer is higher than the back surface of the substrate, the second metal layer protruding out of the back surface of the substrate can be used as an alignment reference to assist alignment, a wiring process is directly connected to the back surface of the second metal layer, the alignment precision of the back power distribution structure on the back surface of the substrate and the second metal layer is improved, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 15 are schematic structural diagrams corresponding to steps of a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As known in the background art, in the current back side of a semiconductor substrate, a through-silicon via process is used to connect a circuit fabricated on the top surface of a silicon chip to the back side of the silicon chip through a metal filled in the through-silicon via.
When the through hole has a high aspect ratio (greater than 10:1), on one hand, the filling capability of metal in the through hole is limited, so that the quality of metal filled and formed in the through hole with the high aspect ratio is poor, the performance of a subsequently formed interconnection structure is influenced, and the improvement of the performance of a semiconductor structure is not facilitated; on the other hand, when forming the back distribution structure, because do not aim at the reference, can cause the alignment precision of back distribution structure and power rail to be low, the condition of complete misalignment appears even to influence the connection structure in the semiconductor structure, influence the power supply performance of power rail, and then lead to semiconductor structure's performance relatively poor.
In order to solve the above problems, the inventors have studied and provided a method for forming a semiconductor structure, in which after forming a power rail opening, a substrate with a partial thickness is continuously etched to form a through hole, and before forming a first metal layer in the through hole, a first sacrificial layer is filled in the through hole, and then the first sacrificial layer is etched back until the height of the first sacrificial layer accounts for 20% -80% of the height of the through hole. The first sacrificial layer is removed by incomplete etching, and the first sacrificial layer with partial thickness is reserved at the bottom of the through hole, so that the height of the through hole during subsequent filling of the first metal layer can be reduced, namely the depth-to-width ratio of the through hole is reduced, the filling quality of the first metal layer is facilitated, the filling of the through hole with the high depth-to-width ratio is realized, and meanwhile, the performance of the semiconductor structure is facilitated to be improved; and subsequently, removing the first sacrificial layer, and forming a second metal layer on the back of the first metal layer, wherein the second metal layer can be used as an alignment reference to help alignment and improve alignment precision.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 15 are schematic structural diagrams corresponding to steps of a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region 101 and a second region 102 adjacent to each other, and a plurality of fins 110 are formed on the substrate 100 in the first region 101.
The substrate 100 provides a process platform for the formation of subsequent semiconductor structures. The substrate 100 may be used to form a finfet or may be used to form a planar transistor.
In this embodiment, the substrate 100 is used for forming a fin field effect transistor, and the forming method further includes: a plurality of fins 110 are formed on the substrate 100 in a discrete arrangement.
In this embodiment, one surface on which the fin portion 110 is formed is a front surface of the substrate 100, and one surface on which the fin portion is not formed, that is, the surface opposite to the front surface is a back surface of the substrate 100.
In this embodiment, the substrate 100 is a silicon substrate; in other embodiments, the substrate may also be a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, a silicon-on-insulator or germanium-on-insulator substrate, or the like.
In this embodiment, the fin 110 is made of silicon; in other embodiments, the material of the fin 110 may also be germanium or silicon germanium.
In this embodiment, the method of forming the fin 110 on the substrate 100 includes: forming a patterned layer (not shown) on the substrate 100, the patterned layer corresponding to a position of the substrate 100 where the fin 110 is to be formed; etching the substrate 100 with a part of thickness by using the patterning layer as a mask to form a plurality of fin parts 110 which are distributed separately; and removing the patterning layer.
The fins 110 may be formed with equal or unequal pitches.
With continued reference to fig. 1, in this embodiment, before forming the through hole, an isolation layer 200 is further formed on the substrate 100 adjacent to the fin 110, and a top of the isolation layer 200 is higher than a top surface of the fin 10.
In this embodiment, the isolation layer 200 is made of silicon dioxide; in other embodiments, the material of the isolation layer 200 may also be silicon oxynitride, silicon nitride, or the like.
In this embodiment, the isolation layer 200 is used to isolate the adjacent fins 110, so as to prevent the subsequent phenomena of leakage, short circuit, etc.
In this embodiment, the method for forming the isolation layer 200 includes: depositing a film of isolating material on the front side of the substrate 100 in the first region 101 and the second region 102, the film of isolating material covering the surface of the substrate 100, the sidewalls and the top surface of the fins 110 of the first region 101; the isolation material film is planarized to form the isolation layer 200.
In this embodiment, the isolation material film is deposited by a fluid chemical vapor deposition process, which enables the isolation material film to have a good filling property.
With continued reference to fig. 1, the isolation layer 200 and a portion of the thickness of the substrate 100 in the second region 102 are etched to form a power rail opening 210.
In this embodiment, the step-by-step etching is performed to etch the isolation layer 200 and the substrate 100 with a partial thickness, the isolation layer 200 in the second region 102 is etched first until the surface of the substrate 100 is exposed, and then the substrate 100 with a partial thickness is etched continuously to form the power rail opening 210.
After the power rail openings 210 are formed, vias are formed within the substrate 100.
Specifically, the step of forming the through-hole includes:
referring to fig. 2, a second sacrificial layer 211 is formed within the power rail opening 210, and the second sacrificial layer 211 covers a surface of the isolation layer 200.
In this embodiment, the material of the second sacrificial layer 211 is a carbon-containing compound; in other embodiments, the material of the second sacrificial layer 211 may also be spin-on oxide.
In this embodiment, a method for forming the second sacrificial layer 211 is spin coating; in other embodiments, the sacrificial layer 211 may be formed by a chemical vapor deposition method.
With continued reference to fig. 2, a mask layer 212 is formed on the second sacrificial layer 211, wherein the mask layer 212 exposes the second sacrificial layer 211 above the power rail opening 210.
The material of the mask layer 212 includes one or more of photoresist, bottom anti-reflection layer, inorganic anti-reflection layer, silicon-containing anti-reflection layer, carbon-containing silicon oxide, or silicon nitride. In this embodiment, the material of the mask layer 212 is photoresist.
In this embodiment, the mask layer 212 is formed by a chemical vapor deposition method.
Referring to fig. 3, the mask layer 212 is used as a mask to etch the second sacrificial layer 211 until the substrate 100 at the bottom of the power rail opening 210 is exposed.
After the second sacrificial layer 211 is etched, the mask layer 212 is removed by an ashing process.
In this embodiment, the method for etching the second sacrificial layer 211 is dry etching or a combination of dry etching and wet etching.
With continued reference to fig. 3, a portion of the thickness of the substrate 100 continues to be etched along the power rail opening 210, forming a via 220.
In this embodiment, the method for etching the substrate 100 includes one or two of dry etching and wet etching.
In this embodiment, the reason why the second sacrificial layer 211 is formed in the power rail opening 210 and then the through hole 220 is formed by etching is as follows: the second sacrificial layer 211 may serve as an alignment reference that may aid in alignment, aligning the formed via 220 with the power rail opening 210.
In this embodiment, the thickness of the substrate 100 is continuously etched within a range of
Figure BDA0002401196120000071
The thickness of the substrate 100 to be etched can be selected according to the actual process requirements.
Fig. 4 is a schematic cross-sectional structure view in the AA direction of fig. 2, and fig. 5 is a schematic cross-sectional structure view in the AA direction of fig. 3.
Referring to fig. 5 and 3, in the present embodiment, the width w1 of the via 220 parallel to the extending direction of the fin 110 is equal to the width w2 of the via 220 perpendicular to the extending direction of the fin 110.
In other embodiments, the width w1 of the via 220 in the direction parallel to the extending direction of the fin 110 may be greater than the width w2 of the via 220 in the direction perpendicular to the extending direction of the fin 110. When the space for forming the through hole 220 is not enough in the direction perpendicular to the extending direction of the fin 110, the width of the through hole 220 may be properly widened in the direction parallel to the extending direction of the fin 110, so as to improve the conductivity of the through hole 220, thereby improving the performance of the semiconductor structure.
Referring to fig. 6, after the through hole 220 is formed, the second sacrificial layer 211 is removed by an ashing process.
After the via hole 220 is formed, a first sacrificial layer is formed in the via hole 220.
With continued reference to fig. 6, in the present embodiment, before forming the first sacrificial layer, a first insulating layer 310 is formed on the sidewall of the power rail opening 210, the sidewall of the via 220, and the bottom surface.
The first insulating layer 310 is used to isolate the first metal layer formed in the through hole from the substrate 100 and the isolation layer 200.
The material of the first insulating layer 310 may be a nitride (e.g., silicon nitride) or an oxide.
A method of forming the first insulating layer 310 may be a chemical vapor deposition method or an atomic layer deposition method.
After the first insulating layer 310 is formed, a first sacrificial layer 320 is formed in the via hole 220.
In this embodiment, the first insulating layer 310 has a single-layer structure; in other embodiments, the first insulating layer 310 may also be a multi-layer structure.
It should be noted that after the power rail opening 210 is formed and before the via hole 220 is formed, a power rail opening insulating layer may be formed on the sidewall and the bottom surface of the power rail opening, and then after the via hole 220 is formed, a first insulating layer may be formed on the power rail opening insulating layer and the sidewall and the bottom surface of the via hole.
In this embodiment, referring to fig. 6, the first sacrificial layer 320 is formed by filling the power rail opening 210 and the through hole 220, and the first sacrificial layer 320 further covers the surface of the isolation layer 200.
In this embodiment, the material of the first sacrificial layer 320 includes silicon dioxide; in other embodiments, the material of the first sacrificial layer 320 may also be silicon nitride or silicon carbide.
In this embodiment, the first sacrificial layer 320 is formed by a spin coating method; in other embodiments, the first sacrificial layer 320 may also be formed by a chemical vapor deposition method or an atomic layer deposition method.
Referring to fig. 7, the first sacrificial layer 320 is etched back until the height (H) of the first sacrificial layer 320 is 20% to 80% of the height (H) of the through hole 220.
The method for etching back the first sacrificial layer 320 includes one or two of a dry etching process and a wet etching process.
It should be noted that in this embodiment, the height of the through hole 220 is H shown in the figure, however, when the first metal layer is filled in the through hole 220, the total height of the filling is the sum of the height H of the through hole 220 and the height of the power rail opening 210.
In this embodiment, the first sacrificial layer 320 is etched back until the height of the first sacrificial layer 320 accounts for 20% -80% of the height of the through hole 220, and the first sacrificial layer 320 with a certain height is reserved in the through hole 220, so that the height of the through hole to be filled is reduced, which is equivalent to reducing the depth-to-width ratio of the through hole 220, and when a first metal layer is subsequently filled in the through hole 220 to form the first metal layer, the total height to be filled by the first metal layer is reduced, the filling of the through hole with the high depth-to-width ratio is realized, the filling quality of the first metal layer is improved, and the performance of an interconnection structure in a semiconductor structure is improved.
After etching back the first sacrificial layer 320, a first metal layer is formed in the via 220.
Specifically, the step of forming the first metal layer includes:
referring to fig. 8, a first metal film 330 is filled in the power rail opening 210 and the via 220, and the first metal film 330 covers the surface of the isolation layer 200.
In this embodiment, the first metal film 330 is made of ruthenium; in other embodiments, the material of the first metal film 330 may also be copper, cobalt, tungsten, titanium, aluminum, magnesium, or an intermetallic compound formed by a plurality of metals thereof, or other conductive materials such as titanium nitride or copper manganese, and the intermetallic compound may be a copper-titanium intermetallic compound formed by copper and titanium, or an aluminum-titanium intermetallic compound formed by aluminum and titanium, or the like.
In this embodiment, the first metal film 330 is filled by an electrochemical plating method.
Referring to fig. 9, the first metal film 330 is chemically and mechanically polished until the top of the first metal film 330 is flush with the top surface of the isolation layer 200.
Referring to fig. 10, the first metal film 330 is etched back to form a first metal layer 300.
In this embodiment, the method for etching back the first metal layer 300 includes one or two of dry etching and wet etching.
In this embodiment, the first metal layer 300 in the power rail opening 210 acts as a power rail to supply power to the semiconductor structure; the first metal layer 300 in the via 220 is used to connect the power rail to a second metal layer formed on the back side of the substrate 100 to form a back side power distribution structure, thereby improving the power supply support of the semiconductor structure.
With continued reference to fig. 10, an interlayer dielectric layer 340 is formed on the first metal layer 300, wherein the top of the interlayer dielectric layer 340 is flush with the top of the isolation layer 200.
In this embodiment, the interlayer dielectric layer 340 is made of silicon dioxide; in other embodiments, the material of the interlayer dielectric layer 340 may also be silicon oxynitride or silicon nitride.
In this embodiment, the method for forming the interlayer dielectric layer 340 is a chemical vapor deposition method; in other embodiments, the interlayer dielectric layer 340 may also be formed by using an atomic layer deposition method.
In this embodiment, since the materials of the interlayer dielectric layer 340 and the isolation layer 200 are the same, the interlayer dielectric layer 340 and the isolation layer 200 may be considered to form a new isolation structure together.
Referring to fig. 11, the isolation layer 200 and the interlayer dielectric layer 340 are etched back so that the tops of the isolation layer 200 and the interlayer dielectric layer 340 are lower than the top surface of the fin 110.
In this embodiment, the method for etching back the isolation layer 200 and the interlayer dielectric layer 340 includes one or two of dry etching and wet etching.
In this embodiment, etching back the isolation layer 200 and the interlayer dielectric layer 340 to expose the top and a portion of the sidewall of the fin 110 further includes: forming a gate structure (not shown) crossing the fin portion, and forming a wiring layer on the front surface of the substrate 100. In this embodiment, the process of forming the gate structure and the wiring layer is a conventional process, and is not described herein again.
And thinning the back surface of the substrate 100 after the process of the front surface of the substrate 100 is finished.
Referring to fig. 12, before thinning the back surface of the substrate 100, providing a supporting substrate 400, bonding the front surface of the substrate 100 with the supporting substrate 400, and turning over the substrate 100 and the supporting substrate 400, so that the supporting substrate 400 supports the substrate 100, thereby ensuring the safety of the substrate 100 in the thinning process.
In this embodiment, the supporting substrate 400 is a silicon substrate; in other embodiments, the supporting substrate may also be a germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, or the like.
Referring to fig. 13, the back surface of the substrate 100 is thinned until the first sacrificial layer 320 is exposed from the back surface of the substrate 100.
In this embodiment, a chemical mechanical polishing process is used to thin the back surface of the substrate 100.
Referring to fig. 14, all of the first sacrificial layer 320 is removed to expose the back surface of the first metal layer 300.
The method for removing the first sacrificial layer 320 includes one or two of dry etching and wet etching.
Referring to fig. 15, a second metal layer 500 is formed on the back surface of the first metal layer 300, and the back surface of the second metal layer 500 is flush with the back surface of the substrate 100.
In this embodiment, the material of the second metal layer 500 is the same as that of the first metal layer 300, and is ruthenium; in other embodiments, the material of the second metal layer 500 may also be copper, cobalt, tungsten, titanium, aluminum, magnesium, or an intermetallic compound formed by a plurality of metals thereof, or other conductive materials such as titanium nitride or copper manganese, and the intermetallic compound may be a copper-titanium intermetallic compound formed by copper and titanium, or an aluminum-titanium intermetallic compound formed by aluminum and titanium, or the like.
In this embodiment, the second metal layer 500 is formed by an electrochemical plating method.
In this embodiment, the second metal layer 500 is subsequently led out from the back surface of the substrate 100 through an electrode, so as to form a back power distribution structure.
With continued reference to fig. 15, the back side of the substrate 100 is etched back such that the back surface of the second metal layer 500 is higher than the back surface of the substrate 100.
In this embodiment, the second metal layer 500 protrudes from the back surface of the substrate 100, and the second metal layer 500 is used as an alignment reference to assist alignment when a metal line connected to the second metal layer 500 is formed subsequently, so as to directly form an interconnection metal line on the second metal layer 500, thereby improving the alignment accuracy of the interconnection metal line and the second metal layer 500, avoiding the problem that electrical connection cannot be realized due to misalignment, forming a back power distribution structure, enhancing the power supply support of a semiconductor structure, and improving the performance of the semiconductor structure.
After the step of etching back the back surface of the substrate to make the back surface of the second metal layer 500 higher than the back surface of the substrate 100, the method further includes: interconnection metal lines (not shown) are formed on the back surface of the substrate 100, and the interconnection metal lines are electrically connected to the second metal layer 500.
In this embodiment, the interconnection metal line is made of ruthenium; in other embodiments, the material of the interconnection metal line may also be other conductive materials such as copper, cobalt, or tungsten.
In this embodiment, the interconnection metal lines are continuously formed on the basis of the second metal layer, and the power distribution structure is formed on the back surface of the substrate 100, so that the problem that sufficient power support cannot be provided due to further high RC is effectively solved.
The method for forming the semiconductor structure provided by the embodiment of the invention can solve the problem of filling the through hole with the high depth-to-width ratio in the process of forming the semiconductor structure with back power distribution, and improve the quality of metal filling in the through hole, thereby further improving the performance of the semiconductor structure.
Correspondingly, the embodiment of the invention also provides a semiconductor structure formed by adopting the forming method.
Referring to fig. 15, the semiconductor structure includes: the substrate comprises a substrate 100 and a plurality of first regions 101 and second regions 102, wherein the first regions 101 are adjacent to each other, and the front surface of the substrate 100 is provided with a plurality of fins 110; an isolation layer 200 located on the substrate 100 between adjacent fins 110, wherein the top of the isolation layer 200 is lower than the top surfaces of the fins 110; a power rail opening 210 located within the isolation layer 200 and the substrate 100 of the second region 102; a via 220 in the substrate 100 below the power rail opening 210; a first metal layer 300 located within the power rail opening 210 and a portion of the via 220; and a second metal layer 500 located on the back surface of the first metal layer 300, wherein the back surface of the second metal layer 500 is higher than the back surface of the substrate 100.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent, and a plurality of fin parts are formed on the front surface of the substrate in the first area;
forming an isolation layer on the front surface of the substrate, wherein the top of the isolation layer is higher than the top of the fin part;
etching the isolation layer of the second area and the substrate with partial thickness to form a power rail opening;
continuously etching the substrate with partial thickness along the power rail opening to form a through hole;
forming a first sacrificial layer in the power rail opening and the through hole;
etching back the first sacrificial layer until the height of the first sacrificial layer accounts for 20% -80% of the height of the through hole;
forming a first metal layer in the power rail opening and the through hole;
thinning the back surface of the substrate until the first sacrificial layer is exposed from the back surface of the substrate;
removing all the first sacrificial layers to expose the back surface of the first metal layer;
and forming a second metal layer on the back surface of the first metal layer, wherein the back surface of the second metal layer is flush with the back surface of the substrate.
2. The method of forming a semiconductor structure of claim 1, further comprising, after forming the second metal layer: and etching back the back surface of the substrate to enable the back surface of the second metal layer to be higher than the back surface of the substrate.
3. The method of forming a semiconductor structure of claim 1, wherein a material of the first sacrificial layer comprises silicon dioxide, silicon nitride, or silicon carbide.
4. The method of forming a semiconductor structure according to claim 3, wherein a method of forming the first sacrificial layer comprises a spin coating method or a chemical vapor deposition method or an atomic layer deposition method.
5. The method of claim 1, wherein the etching back of the first sacrificial layer comprises one or a combination of a dry etching process and a wet etching process.
6. The method of forming a semiconductor structure of claim 1, wherein the method of forming the via comprises:
forming a second sacrificial layer in the power rail opening, wherein the second sacrificial layer covers the surface of the isolation layer;
forming a mask layer on the second sacrificial layer, wherein the mask layer exposes the second sacrificial layer above the power rail opening;
etching the second sacrificial layer by taking the mask layer as a mask until the substrate at the bottom of the power rail opening is exposed;
and continuously etching the substrate with partial thickness along the power rail opening to form a through hole.
7. The method of forming a semiconductor structure of claim 6, wherein a material of the second sacrificial layer comprises a carbon-containing compound or a spin-on oxide.
8. The method of claim 6, wherein a width of the via in a direction parallel to an extending direction of the fin is greater than or equal to a width of the via in a direction perpendicular to the extending direction of the fin.
9. The method of forming a semiconductor structure of claim 1, wherein forming the first metal layer comprises:
filling a first metal film in the opening of the power rail and the through hole, wherein the first metal film covers the surface of the isolation layer;
carrying out chemical mechanical polishing on the first metal film until the top of the first metal film is flush with the surface of the top of the isolation layer;
and etching back the first metal film to form a first metal layer.
10. The method of claim 9, wherein a material of the first metal layer comprises copper, cobalt, tungsten, ruthenium, titanium, aluminum, magnesium, or an intermetallic compound formed of a plurality of metals thereof, or titanium nitride or copper manganese.
11. The method of claim 1, wherein a material of the second metal layer comprises copper, cobalt, tungsten, ruthenium, titanium, aluminum, magnesium, or an intermetallic compound formed of a plurality of metals thereof, or titanium nitride or copper manganese.
12. The method of forming a semiconductor structure of claim 1, further comprising, prior to thinning the back side of the substrate: and providing a support substrate, and bonding the front surface of the substrate with the support substrate.
13. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the first sacrificial layer: and forming a first insulating layer on the side wall of the opening of the power rail, the side wall of the through hole and the bottom surface.
14. The method of forming a semiconductor structure of claim 13, further comprising, after forming the power rail opening and before forming the via: and forming a power rail opening insulating layer on the side wall and the bottom surface of the power rail opening.
15. The method for forming a semiconductor structure according to claim 14, wherein the first insulating layer has a single-layer structure or a multi-layer structure.
16. A semiconductor structure, comprising:
the substrate comprises a first area and a second area which are adjacent, and the front surface of the substrate in the first area is provided with a plurality of fin parts;
the isolation layer is positioned on the substrate between the adjacent fin parts, and the top of the isolation layer is lower than the surface of the top of each fin part;
a power rail opening located within the isolation layer and the substrate of the second region;
a through hole in the substrate below the power rail opening;
the first metal layer is positioned in the power rail opening and part of the through hole;
and the second metal layer is positioned on the back surface of the first metal layer, and the back surface of the second metal layer is higher than the back surface of the substrate.
CN202010147264.5A 2020-03-05 2020-03-05 Semiconductor structure and forming method thereof Pending CN113363226A (en)

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