CN113345968B - Thin film transistor, manufacturing method of thin film transistor and display panel - Google Patents

Thin film transistor, manufacturing method of thin film transistor and display panel Download PDF

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Publication number
CN113345968B
CN113345968B CN202110598077.3A CN202110598077A CN113345968B CN 113345968 B CN113345968 B CN 113345968B CN 202110598077 A CN202110598077 A CN 202110598077A CN 113345968 B CN113345968 B CN 113345968B
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thin film
layer
active layer
film transistor
substrate
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CN113345968A (en
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罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Abstract

The invention provides a thin film transistor, a manufacturing method of the thin film transistor and a display panel, wherein the thin film transistor comprises: a substrate; a catalytic portion disposed on the substrate; an active layer disposed on the substrate and contacting the catalytic portion, a constituent material of the active layer including single crystal silicon and/or polycrystalline silicon. According to the scheme, in the process of preparing the active layer by adopting amorphous silicon, excimer laser annealing is not needed, and monocrystalline silicon and/or polycrystalline silicon can be obtained through catalysis of the catalysis part, so that the prepared thin film transistor can be applied to a large-size display panel, and the utilization rate of the thin film transistor is improved.

Description

Thin film transistor, manufacturing method of thin film transistor and display panel
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a manufacturing method of the thin film transistor and a display panel.
Background
With the development of Display technology, Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, and thin body, and become the mainstream of Display panels.
Thin-film transistors (TFTs) are the main driving elements in LCDs, and can be classified into amorphous silicon (a-Si) TFTs, Low Temperature Polysilicon (LTPS) TFTs, and single crystal silicon (single crystal silicon) TFTs according to the material of the active layer.
In the prior art, a TFT in a large-size display panel is complex in preparation process.
Disclosure of Invention
The invention aims to provide a thin film transistor, a manufacturing method of the thin film transistor and a display panel, and solves the problem that in the prior art, a TFT (thin film transistor) of a large-size display panel is complex in preparation process.
An embodiment of the present invention provides a thin film transistor, including:
a substrate;
a catalytic portion disposed on the substrate;
an active layer disposed on the substrate and contacting the catalytic portion, a constituent material of the active layer including single crystal silicon and/or polycrystalline silicon.
In an embodiment, the thin film transistor further includes a buffer layer on the substrate, the buffer layer has a groove, the catalytic portion and the active layer are disposed in the groove, the catalytic portion and the active layer are disposed on the same layer, and the active layer is disposed on one side of the catalytic portion.
In one embodiment, the width of the groove ranges from 1 micron to 10 microns.
In an embodiment, when the width of the groove ranges from 1 micrometer to 2 micrometers, the composition material of the active layer is the monocrystalline silicon, and when the width of the groove ranges from 2 micrometers to 10 micrometers, the composition material of the active layer is the polycrystalline silicon.
In one embodiment, the thin film transistor further includes a buffer layer on the substrate;
the catalytic part is disposed on the buffer layer, and the active layer is disposed on the catalytic part; or
The active layer is disposed on the buffer layer, and the catalytic portion is disposed on the active layer.
In one embodiment, when the active layer is disposed on the catalytic portion, a surface of the catalytic portion in contact with the active layer is non-planar;
when the catalytic portion is disposed on the active layer, a surface of the active layer in contact with the catalytic portion is a plane.
In one embodiment, the constituent material of the catalytic portion is a metal catalyst.
In one embodiment, the metal catalyst comprises one or a combination of indium, gallium, and tin.
The embodiment of the invention also provides a manufacturing method of the thin film transistor, which comprises the following steps:
providing a substrate;
forming a buffer layer on the substrate, the buffer layer having a groove;
forming a catalytic part on one side in the groove;
forming an amorphous silicon thin film layer on the buffer layer and the catalytic part to obtain a target substrate, wherein the amorphous silicon thin film layer comprises a target amorphous silicon thin film layer which is positioned in the groove and is in contact with the side part of the catalytic part;
and annealing the target substrate to convert the target amorphous silicon thin film layer into a monocrystalline silicon layer and/or a polycrystalline silicon layer under the catalysis of the catalytic part so as to obtain an active layer.
The embodiment of the invention also provides a display panel which comprises the thin film transistor.
In the thin film transistor, the manufacturing method of the thin film transistor and the display panel, monocrystalline silicon and/or polycrystalline silicon can be obtained through catalysis of the catalytic part in the process of preparing the active layer by adopting amorphous silicon, so that the prepared thin film transistor can be applied to a large-size display panel and is simple in process.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a first structure of a thin film transistor according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a second structure of the thin film transistor according to the embodiment of the present invention.
Fig. 3 is a schematic diagram of a third structure of the thin film transistor according to the embodiment of the invention.
Fig. 4 is a schematic diagram of a fourth structure of a thin film transistor according to an embodiment of the present invention.
Fig. 5 is a first flowchart of a method for manufacturing a thin film transistor according to an embodiment of the invention.
Fig. 6 is a second flowchart of a method for manufacturing a thin film transistor according to an embodiment of the invention.
Fig. 7 is a schematic view of a scene of a manufacturing method of a thin film transistor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "thickness," "upper," "lower," etc. indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features.
The embodiment of the invention provides a display panel. The display panel includes a thin film transistor. Referring to fig. 1, fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. As shown in fig. 1, the thin film transistor 1 includes a substrate 11, a catalytic portion 12, and an active layer 13. Next, components in the thin film transistor 1 will be described in detail.
The substrate 11 may be a flexible substrate or a rigid substrate, and specifically, may be a glass substrate, such as an aluminosilicate substrate, an aluminoborosilicate glass, and a quartz glass, and the specific material of the substrate 11 is not limited herein.
The catalytic portion 12 is provided on the substrate 11, and the constituent material of the catalytic portion 12 is a metal catalyst. In an embodiment, the metal catalyst may include one of indium In, gallium Ga, and tin Sn, and a combination thereof.
The active layer 13 is disposed on the substrate 11 and is in contact with the catalytic portion 12. The active layer 13 is made of a material including single crystal silicon and/or polycrystalline silicon. Note that the starting material of the active layer 13 is amorphous silicon, and the amorphous silicon is catalytically converted by the catalytic portion 12 during the annealing treatment to obtain single crystal silicon and/or polycrystalline silicon. Specifically, an amorphous silicon thin film is deposited (CVD) on the substrate 11 by Chemical Vapor Deposition, and the amorphous silicon thin film is brought into contact with the catalyst portion 12, thereby obtaining a target substrate. Then, the target substrate is placed in a high-temperature furnace and is subjected to annealing treatment under the protection of nitrogen N2 and inert gas such as argon Ar. Wherein the inert gas can prevent the amorphous silicon thin film from being oxidized. In the annealing process, the catalyst in the catalytic portion 12 converts amorphous silicon into single crystal silicon and/or polycrystalline silicon, thereby obtaining the active layer 13. Wherein the temperature range of the annealing treatment is between 150 ℃ and 400 ℃.
The active layer 13 may be disposed on the same layer as the catalytic portion 12, or may be disposed on the catalytic portion 12 in a stacked manner, for example, the active layer 13 is disposed on the catalytic portion 12, or the catalytic portion 12 is disposed on the active layer 13. Further, the contact surface between the active layer 13 and the catalytic portion 12 may be a flat surface or a non-flat surface. When the contact surface between the active layer 13 and the catalytic portion 12 is non-planar, the contact area between the active layer 13 and the catalytic portion 12 can be increased, and the catalytic efficiency of the catalytic portion 12 can be improved.
As shown in fig. 2, the active layer 13 includes a channel region 131 and a doped region 132, wherein the doped region 132 is disposed at both sides of the channel region 131. The doped region 132 may be doped with phosphorus or boron according to the product requirement to fabricate an N-type or P-type thin film transistor.
In one embodiment, the thin film transistor 1 further includes a buffer layer 14. Wherein the buffer layer 14 is disposed on the substrate 11.
In one embodiment, as shown in fig. 2, the buffer layer 14 has a groove 141. The groove 141 is used to prepare the active layer 13 and the catalytic portion 12. Specifically, the buffer layer 14 is exposed and etched to form the groove 141.
Specifically, a catalyst thin film is Physically Vapor Deposited (PVD) on the buffer layer 14, and then the catalyst thin film is exposed and etched, so that the catalyst portion 12 is disposed only on one side of the groove 141. It should be noted that, since the catalytic portion 12 is disposed on only one side of the groove 141, the amorphous silicon in the groove 141 is converted into single crystal silicon and/or polycrystalline silicon. Further, the amorphous silicon outside the groove 141 is removed by exposure and etching.
The size of the groove 141 is identical to that of the active layer 13 to be subsequently fabricated. In one embodiment, the width of the groove 141 may be set to range from 1 micron to 10 microns. When the width of the groove 141 is in the range of 1 to 2 micrometers, the amorphous silicon in the groove 141 is converted into monocrystalline silicon, i.e., the composition material of the active layer 13 is monocrystalline silicon. When the width of the groove 141 ranges from 2 micrometers to 10 micrometers, the amorphous silicon in the groove 141 is converted into polysilicon, i.e., the constituent material of the active layer 13 is polysilicon.
In one embodiment, as shown in fig. 3, the catalytic portion 12 is disposed on the buffer layer 14, and the active layer 13 is disposed on the catalytic portion 12. The surface of the catalytic part 12 in contact with the active layer 13 is non-planar, so that the contact area between the active layer 13 and the catalytic part 12 can be increased, and the catalytic efficiency of the catalytic part 12 can be improved.
In one embodiment, as shown in fig. 4, the active layer 13 is disposed on the buffer layer 14, and the catalytic portion 12 is disposed on the active layer 13. When the catalytic portion 12 is disposed on the active layer 13, a surface of the active layer 13 in contact with the catalytic portion 12 is a plane.
Further, the thin film transistor 1 further includes a gate insulating layer 15, a gate electrode layer 16, an interlayer insulating layer 17, a source electrode layer 18, and a drain electrode layer 19.
The gate insulating layer 15 is disposed on the buffer layer 14, the catalytic portion 12, and the active layer 13. The gate layer 16 is disposed on the gate insulating layer 15. An interlayer insulating layer 17 is disposed on the gate layer 16. A source layer 18 and a drain layer 19 are provided on the interlayer insulating layer 17. Wherein the gate insulating layer 15 and the interlayer insulating layer 17 both function as an insulator. Via holes are formed in the interlayer insulating layer 17 and the gate insulating layer 15, and the via holes are filled with a conductive material so that the source layer 18 and the drain layer 19 can be electrically connected to the active layer 13. It should be noted that the gate layer 16 may serve as a barrier layer for the channel region 131 during doping the active layer 13 to form the doped region 132.
According to the display panel and the thin film transistor, in the process of preparing the active layer by adopting the amorphous silicon, excimer laser annealing is not needed, the amorphous silicon can be catalyzed by the catalytic part to obtain monocrystalline silicon and/or polycrystalline silicon, so that the prepared thin film transistor can be applied to a large-size display panel, and the utilization rate of the thin film transistor is improved.
Furthermore, the embodiment of the invention also provides a manufacturing method of the thin film transistor. Fig. 5 is a schematic flow chart of a manufacturing method of a thin film transistor according to an embodiment of the present invention. The manufacturing method comprises the following steps:
step S101, a substrate is provided.
The substrate 11 may be a flexible substrate or a rigid substrate, and specifically, may be a glass substrate, such as an aluminosilicate substrate, an aluminoborosilicate glass, and a quartz glass, and the specific material of the substrate 11 is not limited herein.
Step S102, a catalyst portion is formed on the substrate.
The constituent material of the catalytic portion 12 is a metal catalyst. In an embodiment, the metal catalyst may include one of indium In, gallium Ga, and tin Sn, and a combination thereof.
Step S103 of forming an active layer on the substrate, wherein the active layer is in contact with the catalytic portion, and a constituent material of the active layer includes single crystal silicon and/or polycrystalline silicon.
The active layer 13 is disposed on the substrate 11 and is in contact with the catalytic portion 12. The active layer 13 is made of a material including single crystal silicon and/or polycrystalline silicon. It should be noted that the starting material of the active layer 13 is amorphous silicon, and the amorphous silicon is catalytically converted by the catalytic portion 12 during the annealing treatment to obtain single crystal silicon and/or polycrystalline silicon.
The active layer 13 may be disposed on the same layer as the catalytic portion 12, or may be disposed on the catalytic portion 12 in a stacked manner, for example, the active layer 13 is disposed on the catalytic portion 12, or the catalytic portion 12 is disposed on the active layer 13.
Specifically, when the active layer 13 may be disposed on the same layer as the catalyst portion 12, after the step of forming the catalyst portion 12 on the substrate 11, an amorphous silicon thin film is further deposited (Chemical Vapor Deposition, CVD) on the substrate 11, and the amorphous silicon thin film is brought into contact with the catalyst portion 12, so as to obtain a target substrate. When the active layer 13 is provided on the catalyst portion 12, an amorphous silicon thin film is first CVD-formed on the substrate 11, and then the catalyst portion 12 is formed on the amorphous silicon thin film, resulting in a target substrate. When the catalyst portion 12 is provided on the active layer 13, after the step of forming the catalyst portion 12 on the substrate 11, an amorphous silicon thin film is further CVD-formed on the catalyst portion 12, resulting in a target substrate.
Then, the target substrate is placed in a high temperature furnace, and annealing treatment is performed under the protection of nitrogen N2 and inert gas such as argon Ar. Wherein the inert gas can prevent the amorphous silicon thin film from being oxidized. During the annealing process, the catalyst in the catalytic portion 12 converts the amorphous silicon into single crystal silicon and/or polycrystalline silicon. Wherein the temperature range of the annealing treatment is between 150 ℃ and 400 ℃.
Further, the contact surface between the active layer 13 and the catalytic portion 12 may be a flat surface or a non-flat surface. When the contact surface between the active layer 13 and the catalytic portion 12 is non-planar, the contact area between the active layer 13 and the catalytic portion 12 can be increased, and the catalytic efficiency of the catalytic portion 12 can be improved.
As shown in fig. 2, the active layer 13 includes a channel region 131 and a doped region 132, wherein the doped region 132 is disposed at both sides of the channel region 131. The doped region 132 may be doped with phosphorus or boron according to the product requirement to fabricate an N-type or P-type thin film transistor.
In one embodiment, the buffer layer 14 may be formed on the substrate 11, and the catalytic portion 12 and the active layer 13 may be formed on the buffer layer 14.
As shown in fig. 3, the catalyst portion 12 is formed on the buffer layer 14, and the active layer 13 is formed on the catalyst portion 12. The surface of the catalytic part 12 in contact with the active layer 13 is non-planar, so that the contact area between the active layer 13 and the catalytic part 12 can be increased, and the catalytic efficiency of the catalytic part 12 can be improved.
As shown in fig. 4, the active layer 13 may be formed on the buffer layer 14, and the catalyst portion 12 may be formed on the active layer 13. When the catalytic portion 12 is disposed on the active layer 13, a surface of the active layer 13 in contact with the catalytic portion 12 is a plane.
The embodiment of the invention also provides another manufacturing method of the thin film transistor. Referring to fig. 6 and 7, fig. 6 is a schematic flow chart illustrating a method for manufacturing a thin film transistor according to an embodiment of the invention. Fig. 7 is a schematic view of a scene of a manufacturing method of a thin film transistor according to an embodiment of the present invention. The manufacturing method comprises the following steps:
in step S201, a substrate is provided.
The substrate 11 may be a flexible substrate or a rigid substrate, and specifically, may be a glass substrate, such as an aluminosilicate substrate, an aluminoborosilicate glass, and a quartz glass, and the specific material of the substrate 11 is not limited herein.
Step S202, a buffer layer is formed on the substrate, the buffer layer having a groove.
As shown in fig. 3, a buffer layer 14 is formed on a substrate 11. The buffer layer 14 has a groove 141. Specifically, the buffer layer 14 is exposed and etched to form the groove 141. The groove 141 is used to prepare the active layer 13, and thus the size of the groove 141 is identical to that of the active layer 13 to be prepared later. In one embodiment, the width of the groove 141 may be set to range from 1 micron to 10 microns.
In step S203, a catalytic portion is formed on one side in the groove.
The catalytic portion 12 is disposed at one side of the groove 141. The constituent material of the catalytic portion 12 is a metal catalyst. In an embodiment, the metal catalyst may include indium In, gallium Ga, and/or tin Sn. Specifically, a catalyst thin film is Physically Vapor Deposited (PVD) on the buffer layer 14, and then the catalyst thin film is exposed and etched, so that the catalyst portion 12 is disposed only on one side of the groove 141.
And S204, forming an amorphous silicon thin film layer on the buffer layer and the catalytic part to obtain a target substrate, wherein the amorphous silicon thin film layer comprises a target amorphous silicon thin film layer, and the target amorphous silicon thin film layer is positioned in the groove.
As shown in fig. 3, an amorphous silicon thin film layer a is formed on the buffer layer 14 and the catalyst portion 12 by chemical vapor deposition, and the target substrate 2 is obtained. The amorphous silicon thin film layer A comprises a target amorphous silicon thin film layer A1, and the target amorphous silicon thin film layer A1 is located in the groove 141.
Step S205, annealing the target substrate to convert the target amorphous silicon thin film layer into a monocrystalline silicon layer and/or a polycrystalline silicon layer under the catalysis of the catalytic portion, thereby obtaining an active layer.
The target substrate 2 is placed in a high temperature furnace and annealed under the protection of inert gases such as N2 and Ar. Wherein the inert gas can prevent the amorphous silicon thin film from being oxidized. During the annealing process described above, the catalyst in the catalytic portion 12 converts the amorphous silicon into single crystal silicon and/or polycrystalline silicon, and transfers the catalytic portion 12 from one side to the opposite side within the groove 141. It should be noted that the size of the catalytic portion 12 is smaller than that of the active layer 13, and the catalytic portion 12 is a metal catalyst and is located on one side of the active layer 13, so that the performance of the active layer 13 is less affected by the catalytic portion 12.
Further, since the catalytic portion 12 is disposed only on one side of the groove 141, the amorphous silicon in the groove 141 is converted into single crystal silicon and/or polycrystalline silicon. Wherein, when the width of the groove 141 ranges from 1 micron to 2 microns, the amorphous silicon in the groove 141 is converted into single crystal silicon. That is, the composition material of the active layer 13 is single crystal silicon, and when the width of the groove 141 ranges from 2 micrometers to 10 micrometers, amorphous silicon located in the groove 141 is converted into polycrystalline silicon. I.e., the constituent material of the active layer 13 is polysilicon.
Further, after the active layer 13 is prepared, other components of the thin film transistor may be further prepared, specifically as follows: firstly, amorphous silicon of the amorphous silicon thin film layer A outside the groove 141 is removed; next, a gate insulating layer 15 is formed on the buffer layer 14, the catalytic portion 12, and the active layer 13; a gate electrode layer 16 is then formed on the gate insulating layer 15. An interlayer insulating layer 17 is formed on the gate layer 16. Finally, a source layer 18 and a drain layer 19 are formed on the interlayer insulating layer 17, and both the source layer 18 and the drain layer 19 are electrically connected to the active layer 13.
Specifically, the amorphous silicon outside the groove 141 is removed by exposure and etching. Then, an insulating material is deposited on the buffer layer 14, the catalytic portion 12, and the active layer 13 to obtain a gate insulating layer 15, a conductive material is deposited on the gate insulating layer 15, and the conductive material is exposed and etched to obtain a gate electrode layer 16. Next, the active layer 13 is doped with the gate layer 16 as a blocking layer to form a doped region 132. Specifically, phosphorus or boron can be doped to prepare an N-type or P-type thin film transistor. Next, an insulating material is deposited on the gate electrode layer 16 and the gate insulating layer 15, resulting in an interlayer insulating layer 17. Via holes are then formed in the interlayer insulating layer 17 and the gate insulating layer 15. Finally, a conductive material is deposited on the interlayer insulating layer 17, resulting in a source layer 18 and a drain layer 19. Wherein the conductive material fills the via hole to electrically connect both the source layer 18 and the drain layer 19 to the active layer 13.
According to the manufacturing method of the thin film transistor, in the process of preparing the active layer by adopting the amorphous silicon, excimer laser annealing is not needed, the amorphous silicon can be catalyzed by the catalytic part to obtain monocrystalline silicon and/or polycrystalline silicon, so that the prepared thin film transistor can be applied to a large-size display panel, and the utilization rate of the thin film transistor is improved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The thin film transistor, the method for manufacturing the thin film transistor, and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (5)

1. A thin film transistor, comprising:
a substrate;
a catalytic portion disposed on the substrate;
an active layer disposed on the substrate and contacting the catalytic portion, a constituent material of the active layer including single crystal silicon or polycrystalline silicon;
the buffer layer is arranged above the substrate and provided with a groove, the catalytic part and the active layer are arranged in the groove, the catalytic part and the active layer are arranged on the same layer, and the active layer is arranged on one side of the catalytic part;
wherein when the width of the groove ranges from 1 micrometer to 2 micrometers, the composition material of the active layer is the monocrystalline silicon, and when the width of the groove ranges from 2 micrometers to 10 micrometers, the composition material of the active layer is the polycrystalline silicon.
2. The thin film transistor according to claim 1, wherein a constituent material of the catalytic portion is a metal catalyst.
3. The thin film transistor of claim 2, wherein the metal catalyst comprises one or a combination of indium, gallium, and tin.
4. A method for manufacturing a thin film transistor includes:
providing a substrate;
forming a buffer layer on the substrate, the buffer layer having a groove;
forming a catalytic part on one side in the groove;
forming an amorphous silicon thin film layer on the buffer layer and the catalytic part to obtain a target substrate, wherein the amorphous silicon thin film layer comprises a target amorphous silicon thin film layer which is positioned in the groove and is in contact with the side part of the catalytic part;
annealing the target substrate to convert the target amorphous silicon thin film layer into a monocrystalline silicon layer or a polycrystalline silicon layer under the catalysis of the catalytic part so as to obtain an active layer; when the width of the groove ranges from 1 micrometer to 2 micrometers, the composition material of the active layer is the monocrystalline silicon, and when the width of the groove ranges from 2 micrometers to 10 micrometers, the composition material of the active layer is the polycrystalline silicon.
5. A display panel comprising the thin film transistor according to any one of claims 1 to 3.
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