CN113341298A - Semiconductor circuit testing method, semiconductor circuit testing device, electronic apparatus, and computer storage medium - Google Patents
Semiconductor circuit testing method, semiconductor circuit testing device, electronic apparatus, and computer storage medium Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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Abstract
The invention discloses a semiconductor circuit testing method, wherein the semiconductor circuit comprises a U-phase upper bridge arm output end, a V-phase upper bridge arm output end, a W-phase upper bridge arm output end and a power supply input end, and the semiconductor circuit testing method comprises the following steps: under a normal-temperature static environment, the output end of a U-phase upper bridge arm, the output end of a V-phase upper bridge arm and the output end of a W-phase upper bridge arm are in short connection, and the output ends of the U-phase upper bridge arm, the V-phase upper bridge arm and the W-phase upper bridge arm are in short connection to form a first merging end; applying a first preset voltage to the power input end and the first merging end; after lasting for a first preset time, acquiring first leakage current of the UVW three-phase upper bridge arm; and judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current. In addition, the invention also discloses a semiconductor circuit testing device, electronic equipment and a computer storage medium.
Description
Technical Field
The present invention relates to the field of power semiconductor technologies, and in particular, to a method and an apparatus for testing a semiconductor circuit, an electronic device, and a computer storage medium.
Background
The semiconductor circuit is a power driving product combining power electronics and integrated circuit technology, integrates an intelligent control IC, high-power devices such as an IGBT, a MOSFET and an FRD for power output, and a plurality of resistance-capacitance elements, and is widely applied to the fields of industrial control, household appliances and the like.
A plurality of transistors are integrated in a semiconductor circuit, and the semiconductor circuit needs to be tested after being packaged, for example: leakage current testing, on-off testing, and the like. Specifically, the leakage current of the upper bridge arm of the U phase is tested firstly, if the upper bridge arm of the U phase is normal, the upper bridge arm of the V phase is tested, if the upper bridge arm of the V phase is normal, the upper bridge arm of the W phase is tested, and according to the method, the lower bridge arm of the UVW three phases is tested in sequence.
However, since the upper and lower arms of the UVW three-phase are required to be tested separately, the testing steps are many, and therefore, it takes a long time to perform a product test on the semiconductor circuit, which affects the production efficiency of the semiconductor circuit.
Disclosure of Invention
The invention mainly aims to provide a semiconductor circuit testing method, and aims to solve the technical problem that the existing semiconductor circuit testing method is long in time consumption.
In order to achieve the above object, the present invention provides a method for testing a semiconductor circuit, where the semiconductor circuit includes a U-phase upper arm output terminal, a V-phase upper arm output terminal, a W-phase upper arm output terminal, and a power input terminal, and the method includes:
under a normal-temperature static environment, the output end of a U-phase upper bridge arm, the output end of a V-phase upper bridge arm and the output end of a W-phase upper bridge arm are in short connection, and the output ends of the U-phase upper bridge arm, the V-phase upper bridge arm and the W-phase upper bridge arm are in short connection to form a first merging end;
applying a first preset voltage to the power input end and the first merging end;
after lasting for a first preset time, acquiring first leakage current of the UVW three-phase upper bridge arm;
and judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
Preferably, the semiconductor circuit further includes a U-phase lower arm output terminal, a V-phase lower arm output terminal, and a W-phase lower arm output terminal, and the semiconductor circuit testing method further includes:
if the leakage current test of the UVW three-phase upper bridge arm is normal, then the output end of the U-phase lower bridge arm, the output end of the V-phase lower bridge arm and the output end of the W-phase lower bridge arm are in short circuit, and a second merging end is formed after the output end of the U-phase lower bridge arm, the output end of the V-phase lower bridge arm and the output end of the W-phase lower bridge arm are in short circuit;
applying a second preset voltage to the first merging terminal and the second merging terminal;
after lasting for a second preset time, obtaining a second leakage current of the UVW three-phase lower bridge arm;
and judging whether the leakage current test of the UVW three-phase lower bridge arm is normal or not based on the second leakage current and the second reference leakage current.
Preferably, the semiconductor circuit further includes a U-phase upper arm input terminal, a V-phase upper arm input terminal, a W-phase upper arm input terminal, and a driver chip, and the semiconductor circuit testing method further includes:
if the leakage current test of the UVW three-phase lower bridge arm is normal, then the input end of the U-phase upper bridge arm, the input end of the V-phase upper bridge arm and the input end of the W-phase upper bridge arm are in short circuit, and a third merging end is formed after the input end of the U-phase upper bridge arm, the input end of the V-phase upper bridge arm and the input end of the W-phase upper bridge arm are in short circuit;
respectively inputting high and low levels to the driving chip through the third merging end, and applying a third preset voltage to the power input end and the first merging end;
the method comprises the steps of obtaining first detection voltages at two ends of a UVW three-phase upper bridge arm, and judging whether the on-off test of the UVW three-phase upper bridge arm is normal or not based on the first detection voltages and a first reference voltage.
Preferably, the semiconductor circuit further includes a U-phase lower arm input terminal, a V-phase lower arm input terminal, and a W-phase lower arm input terminal, and the method further includes:
if the on-off test of the UVW three-phase upper bridge arm is normal, then the input end of the U-phase lower bridge arm, the input end of the V-phase lower bridge arm and the input end of the W-phase lower bridge arm are in short circuit, and a fourth merging end is formed after the input end of the U-phase lower bridge arm, the input end of the V-phase lower bridge arm and the input end of the W-phase lower bridge arm are in short circuit;
inputting high and low levels to the driving chip through the fourth merging terminal, and applying a fourth preset voltage to the first merging terminal and the second merging terminal;
and acquiring second detection voltages at two ends of the UVW three-phase lower bridge arm, and judging whether the on-off test of the UVW three-phase lower bridge arm is normal or not based on the second detection voltages and a second reference voltage.
The present invention further provides a semiconductor circuit testing apparatus, wherein the semiconductor circuit includes a U-phase upper arm output terminal, a V-phase upper arm output terminal, a W-phase upper arm output terminal, and a power supply input terminal, the semiconductor circuit testing apparatus includes:
the first pressure application module is used for applying a first preset voltage to the power input end and the first merging end after the output end of the U-phase upper bridge arm, the output end of the V-phase upper bridge arm and the output end of the W-phase upper bridge arm are in short circuit to form the first merging end;
the first current obtaining module obtains a first leakage current of the UVW three-phase upper bridge arm after the first preset duration lasts;
and the first judgment module is used for judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
Preferably, the semiconductor circuit further includes a U-phase lower arm output terminal, a V-phase lower arm output terminal, and a W-phase lower arm output terminal, and the semiconductor circuit testing apparatus further includes:
the second pressure application module is used for applying a second preset voltage to the first merging end and the second merging end when the output end of the U-phase lower bridge arm, the output end of the V-phase lower bridge arm and the output end of the W-phase lower bridge arm are in short circuit to form the second merging end;
the second current obtaining module is used for obtaining a second leakage current of the UVW three-phase lower bridge arm after the second preset duration lasts;
and the second judgment module is used for judging whether the leakage current test of the UVW three-phase lower bridge arm is normal or not based on the second leakage current and the second reference leakage current.
Preferably, the semiconductor circuit further includes a U-phase upper arm input terminal, a V-phase upper arm input terminal, a W-phase upper arm input terminal, and a driver chip, and the semiconductor circuit testing apparatus further includes:
the third voltage application module is used for respectively inputting high and low levels to the driving chip through the third merging end when the input end of the U-phase upper bridge arm, the input end of the V-phase upper bridge arm and the input end of the W-phase upper bridge arm are in short circuit to form a third merging end, and applying a third preset voltage to the power input end and the first merging end;
and the third judgment module is used for acquiring first detection voltages at two ends of the UVW three-phase upper bridge arm and judging whether the on-off test of the UVW three-phase upper bridge arm is normal or not based on the first detection voltages and the first reference voltage.
Preferably, the semiconductor circuit further includes a U-phase lower arm input terminal, a V-phase lower arm input terminal, and a W-phase lower arm input terminal, and the semiconductor circuit testing apparatus further includes:
the fourth voltage applying module is used for respectively inputting high and low levels to the driving chip through the fourth merging end after the U-phase lower bridge arm input end, the V-phase lower bridge arm input end and the W-phase lower bridge arm input end are in short circuit to form a fourth merging end, and applying a fourth preset voltage to the first merging end and the second merging end;
and the fourth judgment module is used for acquiring second detection voltages at two ends of the UVW three-phase lower bridge arm and judging whether the on-off test of the UVW three-phase lower bridge arm is normal or not based on the second detection voltages and the second reference voltage.
The invention further proposes an electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the semiconductor circuit testing method described above when executing the computer program, the semiconductor circuit testing method comprising at least the steps of:
under a normal-temperature static environment, the output end of a U-phase upper bridge arm, the output end of a V-phase upper bridge arm and the output end of a W-phase upper bridge arm are in short connection, and the output ends of the U-phase upper bridge arm, the V-phase upper bridge arm and the W-phase upper bridge arm are in short connection to form a first merging end;
applying a first preset voltage to the power input end and the first merging end;
after lasting for a first preset time, acquiring first leakage current of the UVW three-phase upper bridge arm;
and judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
The present invention further provides a computer storage medium storing a computer program which, when executed by a processor, implements the semiconductor circuit testing method described above, the semiconductor circuit testing method comprising at least the steps of:
under a normal-temperature static environment, the output end of a U-phase upper bridge arm, the output end of a V-phase upper bridge arm and the output end of a W-phase upper bridge arm are in short connection, and the output ends of the U-phase upper bridge arm, the V-phase upper bridge arm and the W-phase upper bridge arm are in short connection to form a first merging end;
applying a first preset voltage to the power input end and the first merging end;
after lasting for a first preset time, acquiring first leakage current of the UVW three-phase upper bridge arm;
and judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
Compared with the prior art, the embodiment of the invention has the beneficial technical effects that:
the semiconductor circuit testing method provided by the invention has the advantages that the upper bridge arms of the UVW three phases are in short circuit, then the first preset voltage is applied between the short-circuited UVW three-phase upper bridge arms and the power supply input end, the combined test of the leakage current of the UVW three-phase upper bridge arms is carried out, and compared with the existing single-point test, the combined test can reduce the testing steps of the semiconductor circuit under the condition of not influencing the testing result, so that the testing time is reduced, and the production cost of the semiconductor circuit is reduced.
Drawings
FIG. 1 is a schematic circuit diagram of a semiconductor circuit according to the present invention;
FIG. 2 is a flow chart of a first embodiment of a method for testing a semiconductor circuit according to the present invention;
FIG. 3 is a flowchart illustrating a second embodiment of a method for testing a semiconductor circuit according to the present invention;
FIG. 4 is a flowchart illustrating a testing method for semiconductor circuits according to a third embodiment of the present invention;
FIG. 5 is a flowchart illustrating a fourth exemplary embodiment of a method for testing a semiconductor circuit according to the present invention;
FIG. 6 is a functional block diagram of a semiconductor circuit testing apparatus according to a first embodiment of the present invention;
FIG. 7 is a functional block diagram of a second embodiment of the testing apparatus for semiconductor circuits according to the present invention;
FIG. 8 is a functional block diagram of a testing apparatus for semiconductor circuits according to a third embodiment of the present invention;
fig. 9 is a schematic structural diagram of an electronic device according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present invention and should not be construed as limiting the present invention, and all other embodiments that can be obtained by one skilled in the art based on the embodiments of the present invention without inventive efforts shall fall within the scope of protection of the present invention.
The semiconductor circuit provided by the invention is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like together and is sealed and packaged on the outer surface, and is widely applied to the field of power electronics, such as the fields of frequency converters of driving motors, various inversion voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, Power semiconductor Module, Power Module, etc. In the following embodiments of the present invention, collectively referred to as a Modular Intelligent Power System (MIPS).
Referring to fig. 1, the MIPS includes a driving chip 01 and a UVW three-phase bridge arm, where the UVW three-phase bridge arm includes a U-phase upper bridge arm, a U-phase lower bridge arm, a V-phase upper bridge arm, a V-phase lower bridge arm, a W-phase upper bridge arm, and a W-phase lower bridge arm. The U-phase upper bridge arm and the U-phase lower bridge arm form a first inverter unit, the U-phase upper bridge arm is a first triode transistor 02 in the circuit, and the U-phase lower bridge arm is a fourth triode transistor 05 in the circuit. The V-phase upper bridge arm and the V-phase lower bridge arm form a second inverter unit, the V-phase upper bridge arm is a second triode transistor 03 in the circuit, and the V-phase lower bridge arm is a fifth triode transistor 06 in the circuit. The W-phase upper arm and the W-phase lower arm form a third inverter unit, the W-phase upper arm is a third triode transistor 04 in the circuit, and the W-phase lower arm is a sixth triode transistor 07 in the circuit.
Further, the upper side of the driving chip 01 is electrically connected with a U-phase upper bridge arm input end HIN1, a V-phase upper bridge arm input end HIN2, a W-phase upper bridge arm input end HIN3, a U-phase lower bridge arm input end LIN1, a V-phase lower bridge arm input end LIN2 and a W-phase lower bridge arm input end LIN3, and the lower side of the driving chip 01 is electrically connected with a U-phase upper bridge arm output end U, V, a U-phase upper bridge arm output end V, W, a phase upper bridge arm output end W, U, a V-phase lower bridge arm output end NV and a W-phase lower bridge arm output end NW. It should be noted that the above mentioned upper side and lower side are only used as reference for the position of the driving chip 01 shown in fig. 1, and do not limit the present invention.
Example one
An embodiment of the present invention provides a MIPS test method, which includes the following steps, with reference to fig. 2:
s10, under a normal-temperature static environment, short-circuiting the U-phase upper bridge arm output end U, V-phase upper bridge arm output end V, W-phase upper bridge arm output end W, and short-circuiting the U-phase upper bridge arm output end U, V-phase upper bridge arm output end V, W-phase upper bridge arm output end W to form a first merging end;
s20, applying a first preset voltage to the power input terminal and the first combining terminal;
s30, after lasting for a first preset time, obtaining a first leakage current of the UVW three-phase upper bridge arm;
and S40, judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
In this embodiment, before testing the MIPS, the U-phase upper arm output terminal U, V-phase upper arm output terminal V, W-phase upper arm output terminal W of the MIPS is short-circuited, and the short-circuited U-phase upper arm output terminal U, V-phase upper arm output terminal V, W-phase upper arm output terminal W forms a first merging terminal.
And after short circuit, applying a first preset voltage between the power supply input end and the first merging end in a normal-temperature static environment, and detecting a first leakage current of the UVW three-phase upper bridge arm through the current detection device after a first preset duration. The UVW three-phase upper bridge arm corresponds to a standard leakage current under a normal condition, namely the first reference leakage current mentioned above, and then the standard leakage current is used as a reference to be compared with the first leakage current.
Specifically, if the detected first leakage current is greater than the first reference leakage current, it indicates that the MIPS is abnormal, and if the detected first leakage current is less than the first reference leakage current, it indicates that the MIPS is normal. The comparison between the first leakage current and the first reference leakage current can be performed by a computer or a human, and those skilled in the art can design the comparison according to actual situations. If the comparison is carried out through the computer, the first leakage current obtained by detection is fed back to the computer through the current detection device, the comparison can be carried out through the computer according to the first reference leakage current stored in the computer and the first leakage current, the comparison result can be displayed through a display screen, can be broadcasted through a loudspeaker in a voice mode, and can be prompted through an audible and visual alarm.
Example two
Referring to fig. 3, the MIPS test method provided by the embodiment of the present invention further includes the following steps:
s50, if the leakage current test of the UVW three-phase upper bridge arm is normal, then short-circuiting the output end NU of the U-phase lower bridge arm, the output end NV of the V-phase lower bridge arm and the output end NW of the W-phase lower bridge arm, and forming a second merging end after the output end NU of the U-phase lower bridge arm, the output end NV of the V-phase lower bridge arm and the output end NW of the W-phase lower bridge arm are short-circuited;
s60, applying a second predetermined voltage to the first combining terminal and the second combining terminal;
s70, after lasting for a second preset time, obtaining a second leakage current of the UVW three-phase lower bridge arm;
and S80, judging whether the leakage current test of the UVW three-phase lower bridge arm is normal or not based on the second leakage current and the second reference leakage current.
In this embodiment, after the leakage current test of the UVW three-phase upper bridge arm is determined to be normal, the leakage current of the UVW three-phase lower bridge arm is continuously tested. Specifically, the output end NU of the U-phase lower bridge arm, the output end NV of the V-phase lower bridge arm, and the output end NW of the W-phase lower bridge arm are short-circuited, and the output end NU of the U-phase lower bridge arm, the output end NV of the V-phase lower bridge arm, and the output end NW of the W-phase lower bridge arm are short-circuited to form a second merging end.
And after short circuit, applying a second preset voltage between the first merging end and the second merging end in a normal-temperature static environment, and detecting a first leakage current of the UVW three-phase lower bridge arm through the current detection device after a second preset duration. And the UVW three-phase lower bridge arm is correspondingly provided with a standard leakage current under the normal condition, namely the second reference leakage current, and then the standard leakage current is used as a reference to be compared with the second leakage current.
Specifically, if the detected second leakage current is greater than the second reference leakage current, it indicates that the MIPS is abnormal, and if the detected second leakage current is less than the second reference leakage current, it indicates that the MIPS is normal. The comparison between the second leakage current and the second reference leakage current can be performed by a computer or a human, and those skilled in the art can design the comparison according to actual situations. If the comparison is carried out through the computer, the second leakage current obtained by detection is fed back to the computer through the current detection device, the comparison can be carried out through the computer according to the second reference leakage current stored in the computer and the second leakage current, the comparison result can be displayed through a display screen, can be broadcasted through a loudspeaker in a voice mode, and can be prompted through an audible and visual alarm.
EXAMPLE III
Referring to fig. 4, the MIPS test method provided by the embodiment of the present invention further includes the following steps:
s90, if the leakage current test of the UVW three-phase lower bridge arm is normal, then short-circuiting the U-phase upper bridge arm input end HIN1, the V-phase upper bridge arm input end HIN2 and the W-phase upper bridge arm input end HIN3, and short-circuiting the U-phase upper bridge arm input end HIN1, the V-phase upper bridge arm input end HIN2 and the W-phase upper bridge arm input end HIN3 to form a third merging end;
s100, respectively inputting high and low levels to the driving chip 01 through a third merging end, and applying a third preset voltage to the power input end and the first merging end;
s200, first detection voltages at two ends of the UVW three-phase upper bridge arm are obtained, and whether the on-off test of the UVW three-phase upper bridge arm is normal or not is judged based on the first detection voltages and a first reference voltage.
In the embodiment, after the leakage current test of the UVW three-phase lower bridge arm is confirmed to be normal, the U-phase upper bridge arm input end HIN1, the V-phase upper bridge arm input end HIN2 and the W-phase upper bridge arm input end HIN3 are in short circuit, and the U-phase upper bridge arm input end HIN1, the V-phase upper bridge arm input end HIN2 and the W-phase upper bridge arm input end HIN3 are in short circuit to form a third merging end.
After short circuit, high and low levels are respectively input to the driving chip 01 through the third merging end, and a third preset voltage is applied between the power input end and the third merging end. Namely: the third merging terminal on the upper side of the driving chip 01 is used for inputting a driving signal for driving the UVW three-phase upper bridge arm to operate, specifically, controlling the on/off of a triode transistor corresponding to the UVW three-phase upper bridge arm, when a high level is input through the third merging terminal, the UVW three-phase upper bridge arm should be in a conducting state, and when a low level is input through the third merging terminal, the UVW three-phase upper bridge arm should be in a closing state.
After the high level is input, a third preset voltage is applied to the power input end and the first merging end, preferably, the third preset voltage mentioned in this embodiment is 5V, and then the first detection voltage at two ends of the UVW three-phase upper bridge arm is obtained through detection by the voltage detection device. Comparing the first detection voltage with the first reference voltage, if the first detection voltage is less than 1.5V (the first reference voltage), determining that the UVW three-phase upper bridge arm is in a conducting state, that is, the on-off test of the UVW three-phase upper bridge arm is normal, and if the first detection voltage is greater than 1.5V (the first reference voltage), determining that the UVW three-phase upper bridge arm is failed, that is, the on-off test of the UVW three-phase upper bridge arm is abnormal, because when a high level is input, the UVW three-phase upper bridge arm is normally in a conducting state, and the first detection voltage detected in the state should be less than 1.5V.
After the low level is input, a third preset voltage is applied to the power input end and the first merging end, preferably, the third preset voltage mentioned in this embodiment is still 5V, and then the first detection voltage at two ends of the UVW three-phase upper bridge arm is obtained through detection by the voltage detection device. Comparing the first detection voltage with the first reference voltage, if the first detection voltage is greater than 4.9V (the first reference voltage), determining that the UVW three-phase upper bridge arm is in an off state, that is, the on-off test of the UVW three-phase upper bridge arm is normal, and if the first detection voltage is less than 4.9V (the first reference voltage), determining that the UVW three-phase upper bridge arm fails, that is, the on-off test of the UVW three-phase upper bridge arm is abnormal, because when a low level is input, the UVW three-phase upper bridge arm is normally in the off state, and a second detection voltage detected in the state should be greater than 4.9V.
It should be noted that, the reference voltage values of the first reference voltage provided by this embodiment are different when a high level and a low level are input, because when a high level is input, the UVW three-phase upper bridge arm is in a conducting state, and in the conducting state, the 5V voltage applied between the power input end and the first merging end is divided by the circuit corresponding to the UVW three-phase upper bridge arm, so that the voltage between the power input end and the first merging end decreases, that is, the voltage between the power input end and the first merging end is obviously smaller than 5V and decreases, specifically, corresponds to the aforementioned 1.5V.
When a low level is input, the UVW three-phase upper bridge arm is in an off state, and in the off state, the 5V voltage applied between the power input end and the first merging end is not divided by the circuit corresponding to the UVW three-phase upper bridge arm, and only a part of the power is lost, so that the voltage between the power input end and the first merging end is substantially 5V, but based on the consideration of the power loss, the detected voltage may be less than 5V, specifically corresponding to the aforementioned 4.9V.
Example four
Referring to fig. 5, the MIPS test method provided by the embodiment of the present invention further includes the following steps:
s300, if the on-off test of the UVW three-phase upper bridge arm is normal, then short-circuiting the U-phase lower bridge arm input end LIN1, the V-phase lower bridge arm input end LIN2 and the W-phase lower bridge arm input end LIN3, and short-circuiting the U-phase lower bridge arm input end LIN1, the V-phase lower bridge arm input end LIN2 and the W-phase lower bridge arm input end LIN3 to form a fourth merging end;
s400, respectively inputting high and low levels to the driver chip 01 through the fourth merging terminal, and applying a fourth preset voltage to the first merging terminal and the second merging terminal;
s500, second detection voltages at two ends of the UVW three-phase lower bridge arm are obtained, and whether the on-off test of the UVW three-phase lower bridge arm is normal or not is judged based on the second detection voltages and a second reference voltage.
In this embodiment, after the on-off test of the UVW three-phase upper bridge arm is determined to be normal, the U-phase lower bridge arm input end LIN1, the V-phase lower bridge arm input end LIN2, and the W-phase lower bridge arm input end LIN3 are short-circuited, and the U-phase lower bridge arm input end LIN1, the V-phase lower bridge arm input end LIN2, and the W-phase lower bridge arm input end LIN3 are short-circuited to form a third merging end.
After short circuit, high and low levels are respectively input to the driving chip 01 through the third merging end, and a third preset voltage is applied between the power input end and the third merging end. Namely: the third merging terminal on the upper side of the driving chip 01 is used for inputting a driving signal for driving the UVW three-phase lower bridge arm to operate, specifically, controlling the on/off of a triode transistor corresponding to the UVW three-phase lower bridge arm, when a high level is input through the third merging terminal, the UVW three-phase lower bridge arm should be in an on state, and when a low level is input through the third merging terminal, the UVW three-phase lower bridge arm should be in an off state.
After the high level is input, a fourth preset voltage is applied to the first merging terminal and the second merging terminal, preferably, the fourth preset voltage mentioned in this embodiment is 5V, and then a second detection voltage at two ends of the UVW three-phase lower bridge arm is detected by the voltage detection device. And comparing the second detection voltage with a second reference voltage, if the second detection voltage is less than 1.5V (the second reference voltage), judging that the UVW three-phase lower bridge arm is in a conducting state, namely, the on-off test of the UVW three-phase lower bridge arm is normal, and if the second detection voltage is greater than 1.5V (the second reference voltage), judging that the UVW three-phase lower bridge arm fails, namely, the on-off test of the UVW three-phase lower bridge arm is abnormal, because when a high level is input, the UVW three-phase lower bridge arm is normally in the conducting state, and the second detection voltage detected in the state is less than 1.5V.
After the low level is input, a fourth preset voltage is applied to the first merging terminal and the second merging terminal, preferably, the fourth preset voltage mentioned in this embodiment is still 5V, and then a second detection voltage at two ends of the UVW three-phase lower bridge arm is detected by the voltage detection device. And comparing the second detection voltage with a second reference voltage, if the second detection voltage is greater than 4.9V (the second reference voltage), judging that the UVW three-phase lower bridge arm is in a turn-off state, namely, the on-off test of the UVW three-phase lower bridge arm is normal, and if the second detection voltage is less than 4.9V (the second reference voltage), judging that the UVW three-phase lower bridge arm fails, namely, the on-off test of the UVW three-phase lower bridge arm is abnormal, because when a low level is input, the UVW three-phase lower bridge arm is normally in the turn-off state, and the second detection voltage detected in the state is greater than 4.9V.
It should be noted that, in the embodiment, the reference voltage values of the second reference voltage when the high and low levels are input are different, because when the high level is input, the UVW three-phase lower bridge arm is in the on state, and in the on state, the voltage of 5V applied between the first merging end and the second merging end is divided by the circuit corresponding to the UVW three-phase lower bridge arm, so that the voltage between the first merging end and the second merging end is decreased, that is, the voltage between the first merging end and the second merging end is obviously smaller than 5V and is decreased, specifically corresponding to the aforementioned 1.5V.
When a low level is input, the UVW three-phase lower bridge arm is in an off state, and in the off state, the 5V voltage applied between the first merging terminal and the second merging terminal is not divided by the circuit corresponding to the UVW three-phase lower bridge arm, and only a part of the electric energy is lost, so that the voltage between the first merging terminal and the second merging terminal is substantially 5V, but based on consideration of the electric energy loss, the detected voltage may be less than 5V, specifically corresponding to the aforementioned 4.9V.
EXAMPLE five
Based on the aforementioned proposed MIPS testing method, referring to fig. 6, the present invention also proposes a MIPS testing apparatus, which includes:
the first voltage application module 10 is configured to apply a first preset voltage to the power input end and the first merging end after the U-phase upper bridge arm output end U, V and the V, W phase upper bridge arm output end W are short-circuited to form the first merging end;
the first current obtaining module 20 obtains a first leakage current of the UVW three-phase upper bridge arm after the first preset duration;
the first determining module 30 is configured to determine whether a leakage current test of the UVW three-phase upper bridge arm is normal based on the first leakage current and the first reference leakage current.
EXAMPLE six
Referring to fig. 7, the MIPS test apparatus according to the embodiment of the present invention further includes:
the second voltage application module 40 is configured to apply a second preset voltage to the first combining end and the second combining end when the U-phase lower bridge arm output end NU, the V-phase lower bridge arm output end NV, and the W-phase lower bridge arm output end NW are short-circuited to form the second combining end;
the second current obtaining module 50 is configured to obtain a second leakage current of the UVW three-phase lower bridge arm after the second preset duration is reached;
and a second judging module 60, configured to judge whether the leakage current test of the UVW three-phase lower bridge arm is normal based on the second leakage current and the second reference leakage current.
EXAMPLE seven
Referring to fig. 8, the MIPS test apparatus provided in the embodiment of the present invention further includes:
the third voltage application module 70 is configured to respectively input high and low levels to the driver chip 01 through a third merging terminal when the U-phase upper bridge arm input terminal HIN1, the V-phase upper bridge arm input terminal HIN2, and the W-phase upper bridge arm input terminal HIN3 are short-circuited to form the third merging terminal, and apply a third preset voltage to the power input terminal and the first merging terminal;
the third judging module 80 is configured to obtain first detection voltages at two ends of the UVW three-phase upper bridge arm, and judge whether the on-off test of the UVW three-phase upper bridge arm is normal based on the first detection voltages and the first reference voltage.
Example eight
Referring to fig. 8, the MIPS test apparatus provided in the embodiment of the present invention further includes:
the fourth voltage application module 90 is configured to, after a fourth merging terminal is formed by short-circuiting the U-phase lower bridge arm input terminal LIN1, the V-phase lower bridge arm input terminal LIN2, and the W-phase lower bridge arm input terminal LIN3, respectively input high and low levels to the driver chip 01 through the fourth merging terminal, and apply a fourth preset voltage to the first merging terminal and the second merging terminal;
and the fourth judging module 100 is configured to obtain a second detection voltage at two ends of the UVW three-phase lower bridge arm, and judge whether the on-off test of the UVW three-phase lower bridge arm is normal based on the second detection voltage and a second reference voltage.
Example nine
Based on the aforementioned proposed MIPS test method, referring to fig. 9, the present invention also proposes an electronic device, including:
a memory 1005 for storing a computer program;
the processor 1001 is configured to implement the MIPS testing method described in the foregoing embodiments 1 to 4 when executing the computer program, where the MIPS testing method at least includes the following steps:
s10, under a normal-temperature static environment, short-circuiting the U-phase upper bridge arm output end U, V-phase upper bridge arm output end V, W-phase upper bridge arm output end W, and short-circuiting the U-phase upper bridge arm output end U, V-phase upper bridge arm output end V, W-phase upper bridge arm output end W to form a first merging end;
s20, applying a first preset voltage to the power input terminal and the first combining terminal;
s30, after lasting for a first preset time, obtaining a first leakage current of the UVW three-phase upper bridge arm;
and S40, judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
The electronic device provided by the embodiment of the invention can be a robot or a PC. As shown in fig. 9, the electronic device may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, a communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the electronic device configuration shown in fig. 9 does not constitute a limitation of the device and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 9, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a computer program.
In the electronic device shown in fig. 9, the network interface 1004 is mainly used for connecting to a backend server and performing data communication with the backend server; the user interface 1003 is mainly used for connecting a client (user side) and performing data communication with the client; and the processor 1001 may be used to invoke computer programs stored in the memory 1005.
Example ten
Based on the aforementioned proposed MIPS testing method, the present invention further provides a computer storage medium, where a computer program is stored, and when the computer program is executed by a processor, the MIPS testing method described in the foregoing embodiments 1 to 4 is implemented, where the MIPS testing method at least includes the following steps:
s10, under a normal-temperature static environment, short-circuiting the U-phase upper bridge arm output end U, V-phase upper bridge arm output end V, W-phase upper bridge arm output end W, and short-circuiting the U-phase upper bridge arm output end U, V-phase upper bridge arm output end V, W-phase upper bridge arm output end W to form a first merging end;
s20, applying a first preset voltage to the power input terminal and the first combining terminal;
s30, after lasting for a first preset time, obtaining a first leakage current of the UVW three-phase upper bridge arm;
and S40, judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only a part of or preferred embodiments of the present invention, and neither the text nor the drawings should be construed as limiting the scope of the present invention, and all equivalent structural changes, which are made by using the contents of the present specification and the drawings, or any other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A semiconductor circuit test method, the semiconductor circuit includes U phase upper bridge arm output end, V phase upper bridge arm output end, W phase upper bridge arm output end and power input end, characterized by that, the semiconductor circuit test method includes:
under a normal-temperature static environment, the output end of a U-phase upper bridge arm, the output end of a V-phase upper bridge arm and the output end of a W-phase upper bridge arm are in short connection, and the output ends of the U-phase upper bridge arm, the V-phase upper bridge arm and the W-phase upper bridge arm are in short connection to form a first merging end;
applying a first preset voltage to the power input end and the first merging end;
after lasting for a first preset time, acquiring first leakage current of the UVW three-phase upper bridge arm;
and judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
2. The semiconductor circuit test method according to claim 1, the semiconductor circuit further comprising a U-phase lower arm output terminal, a V-phase lower arm output terminal, and a W-phase lower arm output terminal, wherein the semiconductor circuit test method further comprises:
if the leakage current test of the UVW three-phase upper bridge arm is normal, then the output end of the U-phase lower bridge arm, the output end of the V-phase lower bridge arm and the output end of the W-phase lower bridge arm are in short circuit, and a second merging end is formed after the output end of the U-phase lower bridge arm, the output end of the V-phase lower bridge arm and the output end of the W-phase lower bridge arm are in short circuit;
applying a second preset voltage to the first merging terminal and the second merging terminal;
after lasting for a second preset time, obtaining a second leakage current of the UVW three-phase lower bridge arm;
and judging whether the leakage current test of the UVW three-phase lower bridge arm is normal or not based on the second leakage current and the second reference leakage current.
3. The semiconductor circuit test method according to claim 2, the semiconductor circuit further comprising a U-phase upper arm input terminal, a V-phase upper arm input terminal, a W-phase upper arm input terminal, and a driver chip, wherein the semiconductor circuit test method further comprises:
if the leakage current test of the UVW three-phase lower bridge arm is normal, then the input end of the U-phase upper bridge arm, the input end of the V-phase upper bridge arm and the input end of the W-phase upper bridge arm are in short circuit, and a third merging end is formed after the input end of the U-phase upper bridge arm, the input end of the V-phase upper bridge arm and the input end of the W-phase upper bridge arm are in short circuit;
respectively inputting high and low levels to the driving chip through the third merging end, and applying a third preset voltage to the power input end and the first merging end;
the method comprises the steps of obtaining first detection voltages at two ends of a UVW three-phase upper bridge arm, and judging whether the on-off test of the UVW three-phase upper bridge arm is normal or not based on the first detection voltages and a first reference voltage.
4. The semiconductor circuit test method according to claim 3, wherein the semiconductor circuit further includes a U-phase lower arm input terminal, a V-phase lower arm input terminal, and a W-phase lower arm input terminal, and wherein the semiconductor circuit test method further includes:
if the on-off test of the UVW three-phase upper bridge arm is normal, then the input end of the U-phase lower bridge arm, the input end of the V-phase lower bridge arm and the input end of the W-phase lower bridge arm are in short circuit, and a fourth merging end is formed after the input end of the U-phase lower bridge arm, the input end of the V-phase lower bridge arm and the input end of the W-phase lower bridge arm are in short circuit;
inputting high and low levels to the driving chip through the fourth merging terminal, and applying a fourth preset voltage to the first merging terminal and the second merging terminal;
and acquiring second detection voltages at two ends of the UVW three-phase lower bridge arm, and judging whether the on-off test of the UVW three-phase lower bridge arm is normal or not based on the second detection voltages and a second reference voltage.
5. A semiconductor circuit testing device, the semiconductor circuit includes U looks upper bridge arm output, V looks upper bridge arm output, W looks upper bridge arm output and power input, characterized by that, the semiconductor testing device includes:
the first pressure application module is used for applying a first preset voltage to the power input end and the first merging end after the output end of the U-phase upper bridge arm, the output end of the V-phase upper bridge arm and the output end of the W-phase upper bridge arm are in short circuit to form the first merging end;
the first current obtaining module obtains a first leakage current of the UVW three-phase upper bridge arm after the first preset duration lasts;
and the first judgment module is used for judging whether the leakage current test of the UVW three-phase upper bridge arm is normal or not based on the first leakage current and the first reference leakage current.
6. The semiconductor circuit test apparatus according to claim 5, the semiconductor circuit further comprising a U-phase lower arm output terminal, a V-phase lower arm output terminal, and a W-phase lower arm output terminal, wherein the semiconductor circuit test apparatus further comprises:
the second pressure application module is used for applying a second preset voltage to the first merging end and the second merging end when the output end of the U-phase lower bridge arm, the output end of the V-phase lower bridge arm and the output end of the W-phase lower bridge arm are in short circuit to form the second merging end;
the second current obtaining module is used for obtaining a second leakage current of the UVW three-phase lower bridge arm after the second preset duration lasts;
and the second judgment module is used for judging whether the leakage current test of the UVW three-phase lower bridge arm is normal or not based on the second leakage current and the second reference leakage current.
7. The semiconductor circuit test device according to claim 6, the semiconductor circuit further comprising a U-phase upper arm input terminal, a V-phase upper arm input terminal, a W-phase upper arm input terminal, and a driver chip, wherein the semiconductor circuit test device further comprises:
the third voltage application module is used for respectively inputting high and low levels to the driving chip through the third merging end when the input end of the U-phase upper bridge arm, the input end of the V-phase upper bridge arm and the input end of the W-phase upper bridge arm are in short circuit to form a third merging end, and applying a third preset voltage to the power input end and the first merging end;
and the third judgment module is used for acquiring first detection voltages at two ends of the UVW three-phase upper bridge arm and judging whether the on-off test of the UVW three-phase upper bridge arm is normal or not based on the first detection voltages and the first reference voltage.
8. The semiconductor circuit test apparatus according to claim 7, the semiconductor circuit further comprising a U-phase lower arm input terminal, a V-phase lower arm input terminal, and a W-phase lower arm input terminal, wherein the semiconductor circuit test apparatus further comprises:
the fourth voltage applying module is used for respectively inputting high and low levels to the driving chip through the fourth merging end after the U-phase lower bridge arm input end, the V-phase lower bridge arm input end and the W-phase lower bridge arm input end are in short circuit to form a fourth merging end, and applying a fourth preset voltage to the first merging end and the second merging end;
and the fourth judgment module is used for acquiring second detection voltages at two ends of the UVW three-phase lower bridge arm and judging whether the on-off test of the UVW three-phase lower bridge arm is normal or not based on the second detection voltages and the second reference voltage.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the semiconductor circuit testing method of any one of claims 1-4 when executing the computer program.
10. A computer storage medium, characterized in that it stores a computer program which, when executed by a processor, implements the semiconductor circuit testing method of any one of claims 1 to 4.
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