CN113328746A - Sample-and-hold amplifying circuit - Google Patents

Sample-and-hold amplifying circuit Download PDF

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CN113328746A
CN113328746A CN202010131514.6A CN202010131514A CN113328746A CN 113328746 A CN113328746 A CN 113328746A CN 202010131514 A CN202010131514 A CN 202010131514A CN 113328746 A CN113328746 A CN 113328746A
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negative
capacitor
voltage
terminal
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CN113328746B (en
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何俊达
闵绍恩
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication

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  • Theoretical Computer Science (AREA)
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Abstract

A sample-and-hold amplification circuit, comprising: positive and negative side capacitor arrays, positive and negative side switch arrays, and differential output circuits. The second ends of the capacitors of the positive and negative side capacitor arrays are electrically coupled to the positive and negative output terminals, respectively. The positive and negative terminal switching arrays each receive a polarity input voltage from the first terminal of each bit capacitor for gain adjustment relative to a common mode input voltage in accordance with a first bit combination connection during a sampling time, and receive an offset adjustment voltage from the first terminal of each bit capacitor for offset adjustment relative to the common mode input voltage in accordance with a second bit combination connection during a holding time to generate positive and negative output voltages at the positive and negative output terminals, respectively. The differential output circuit outputs the positive and negative output voltages as a pair of differential output signals.

Description

Sample-and-hold amplifying circuit
Technical Field
The present invention relates to a sample-and-hold amplifying technique, and more particularly, to a sample-and-hold amplifying circuit.
Background
In a signal processing circuit for processing an image in YPrPb format, it is necessary to receive an ac-coupled signal. In order to correctly input a signal into a circuit at the back end, such as but not limited to an analog-to-digital conversion circuit, so that the signal has a full-amplitude output (full swing), the signal needs to be adjusted. Without an effective adjustment mechanism, the back-end circuit may receive a result that one of the positive and negative signals is compressed and distorted.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a sample-and-hold amplifying circuit to improve the background art.
The present invention comprises a Sample and Hold Amplifier (SHA) circuit, one embodiment of which comprises: the differential amplifier comprises a positive side capacitor array, a negative side capacitor array, a positive side switching array, a negative side switching array and a differential output circuit. The positive side capacitor array and the negative side capacitor array each include a plurality of bit capacitors each having a first end and a second end, wherein the second ends of the bit capacitors of the positive side capacitor array are electrically coupled to the positive output end and the second ends of the bit capacitors of the negative side capacitor array are electrically coupled to the negative output end. The positive side switching array and the negative side switching array are respectively configured to enable the bit capacitors to receive a polarity input voltage from the first ends of the bit capacitors according to a first bit combination connection relationship to perform gain adjustment relative to a common mode input voltage in a sampling time, and are respectively configured to enable the bit capacitors to receive an offset adjustment voltage from the first ends of the bit capacitors according to a second bit combination connection relationship to perform offset adjustment relative to the common mode input voltage in a holding time, and generate a positive output voltage and a negative output voltage at a positive output end and a negative output end respectively. The differential output circuit is configured to output the positive output voltage and the negative output voltage as a pair of differential output signals.
The features, practical operation and efficacy of the present invention will be described in detail with reference to the accompanying drawings.
Drawings
FIG. 1A is a circuit diagram of a sample-and-hold amplifier circuit and an analog-to-digital converter circuit according to an embodiment of the invention;
FIG. 1B is a more detailed schematic diagram of the positive side capacitor array and the positive side switch array in accordance with one embodiment of the present invention;
FIG. 1C is an enlarged schematic diagram of a switching circuit and a corresponding bit capacitor according to an embodiment of the invention;
FIG. 2 is a circuit diagram illustrating the positive side capacitor array and the positive side switch array operating at sample time according to an embodiment of the present invention; and
FIG. 3 is a circuit diagram illustrating the positive side capacitor array and the positive side switch array operating at hold time in one embodiment of the invention.
Detailed Description
An objective of the present invention is to provide a sample-and-hold amplifier circuit, which effectively adjusts the gain and offset of an input signal with respect to a common-mode input voltage, and conforms to the input range of a back-end circuit.
Please refer to fig. 1A. Fig. 1A is a circuit diagram of a Sample and Hold Amplifier (SHA) circuit 100 and an analog-to-digital conversion circuit 160 according to an embodiment of the invention.
In one embodiment, the sample-and-hold amplifying circuit 100 and the analog-to-digital converting circuit 160 can be applied to a signal processing circuit for processing YPrPb-formatted images, for example, but not limited thereto. The sample-and-hold amplifier circuit 100 is configured to adjust the gain and offset of the input analog signal to enhance the input analog signal, and adjust the common mode voltage level of the input analog signal to meet the input requirement of the analog-to-digital converter circuit 160.
The sample-and-hold amplification circuit 100 includes a positive side capacitor array 110, a negative side capacitor array 120, a positive side switch array 130, a negative side switch array 140, and a differential output circuit 150.
Please refer to fig. 1B. FIG. 1B is a more detailed schematic diagram of the positive side capacitor array 110 and the positive side switch array 130 according to an embodiment of the invention.
The positive side capacitor array 110 includes a plurality of bit capacitors CL0To CLnAnd CM0To CMnAnd a gain adjustment capacitance Cg.
Bit capacitance CL0To CLnAnd CM0To CMnEach having a first end and a second end. In one embodiment, bit capacitor CL0To CLnAnd CM0To CMnDivided into high-order capacitors CM0To CMnAnd low-order capacitance CL0To CLn. Wherein, the bit capacitance CMnThe capacitance of the highest position has the largest adjustment amplitude for gain and offset. Relative, bit capacitance CL0The lowest order capacitor has the smallest adjustment for gain and offset.
In one embodiment, the high bit potentialCapacity CM0To CMnThe second terminal phase of the capacitor is electrically coupled to the positive output terminal PT and the low-order bit capacitor CL0To CLnThe second terminal is electrically coupled to the positive output terminal PT through the middle capacitor Cb.
The gain-adjusting capacitor Cg has a first end and a second end, wherein the second end of the gain-adjusting capacitor Cg is electrically coupled to the positive output terminal PT.
The negative side capacitor array 120 has a symmetrical structure with the positive side capacitor array 110, except for the bit capacitance CM0To CMnAnd CL0To CLnThe second terminal of the gain adjusting capacitor Cg and the second terminal of the gain adjusting capacitor Cg are electrically coupled to a negative output terminal NT. The detailed structure thereof will not be described herein.
The positive side switching array 130 includes a plurality of switching circuits SL0To SLnAnd SM0To SMn. Switching circuit SL0To SLnAnd SM0To SMnRespectively corresponding to bit capacitors CL0To CLnAnd CM0To CMnAnd (4) setting.
Please refer to fig. 1C. FIG. 1C shows a switching circuit SL according to an embodiment of the invention0And corresponding bit capacitance CL0Is shown schematically in enlarged scale.
Switching circuit SL0To SLnAnd SM0To SMnEach having a first selection cell S1, a second selection cell S2, and a third selection cell S3. In one embodiment, the first selection unit S1 of each switching circuit is controlled by the gain control signal GL0To GLnAnd GM0To GMnAnd (5) controlling. To switch the circuit SL0For example, the first selection unit S1 is controlled by the gain control signal GL0And (5) controlling. The second selection unit S2 is controlled by the offset control signal OL0To OLnAnd OM0To OMnAnd (5) controlling. To switch the circuit SL0For example, the second selection unit S2 is controlled by the offset control signal OL0And (5) controlling. The third selection unit S3 is controlled by the mode control signal CKM.
The gain selection unit Sg is set corresponding to the gain adjustment capacitor Cg and controlled by the mode control signal CKM.
The negative side switch array 140 has a symmetrical structure with the positive side switch array 130. The detailed structure thereof will not be described herein.
The first selection unit S1, the second selection unit S2, the third selection unit S3, and the gain selection unit Sg may interleave operation in operation modes of a sampling time and a holding time. The bit capacitor CM including 10 bits will be described below0To CM4And CL0To CL4And a switching circuit SM comprising corresponding bit capacitances0To SM4And SL0To SL4The positive side switch array 130 is illustrated as an example.
Please refer to fig. 2. FIG. 2 is a circuit diagram of the positive side capacitor array 110 and the positive side switch array 130 operating at sample time according to an embodiment of the present invention.
During the sampling time, the first selection unit S1 is configured to control the signal GL according to the gain control signal GL0To GLnAnd GM0To GMnThe control of (1) receiving a polarity input voltage in a selected state or receiving a common mode input voltage Vcmi in an unselected state. The polarity input voltage corresponding to the positive side switch array 130 is a positive input voltage Vip, and the common mode input voltage Vcmi is a dc voltage.
The third selection unit S3 electrically couples the first selection unit S1 to a corresponding capacitor (e.g., a corresponding switch circuit SM) according to the mode control signal CKM0To SM4And SL0To SL4Bit capacitance CM0To CM4And CL0To CL4) The first end of (a).
The gain selection unit Sg makes the gain adjustment capacitor Cg receive a polarity input voltage of the positive input voltage Vip according to the mode control signal CKM.
Therefore, in the operation mode of the sampling time, the sample-hold amplifying circuit 100 can be switched according to the switching circuit SM included in the positive terminal switching array 1300To SM4And SL0To SL4A first selection unit S1 and a third selection unit S3 respectively arranged on the bit capacitance CM of the positive side capacitor array 1100To CM4And CL0To CL4The gain adjustment of the positive input voltage Vip with respect to the common mode input voltage Vcmi is performed.
For example, when the connection to be made is represented by a bit (1001000100), the switching circuit SM4、SM1And SL2The first selection unit S1 makes the bit capacitances CM corresponding to the 10 th, 7 th and 3 rd bits respectively4、CM1And CL2To a selected state to receive the positive input voltage Vip, and other switching circuits to make other bit capacitances to an unselected state to receive the common mode input voltage Vcmi.
In one embodiment, when all bit capacitors CM are present0To CM4And CL0To CL4The connection of (a) is 1 (e.g. 1111111 of 10 bits), i.e. the total gain will be 1 when receiving the positive input voltage Vip. When all bit capacitors CM0To CM4And CL0To CL4The connection relationships of (a) are all 0 (e.g. 10-bit 0000000000), that is, the total gain will be 0 when receiving the common mode input voltage Vcmi. Thus, all different bit combinations from high to low, up to 2M+NThe amount of gain adjustment of the step size.
In addition, by setting the capacitance value of the gain adjustment capacitor Cg, the gain of the positive input voltage Vip can be doubled. Therefore, when the required total gain is a value in the range of one time to two times, the capacitance of the gain adjustment capacitor Cg can generate two times of gain for the positive input voltage Vip, and then the bit capacitor CM0To CM4And CL0To CL4The connection relation of (c) is adjusted down to the desired value.
Similarly, the sample-and-hold amplifier circuit 100 can switch the switching circuit SM included in the array 140 according to the negative terminal0To SMnAnd SL0To SLnThe first selection unit S1 and the third selection unit S3 respectively comprise, and a bit capacitor CM of the negative side capacitor array 120 is arranged0To CMnAnd CL0To CLnFor negative input voltage VinAnd adjusting the line gain. And will not be described in detail herein.
Please refer to fig. 3. FIG. 3 is a circuit diagram illustrating the positive side capacitor array 110 and the positive side switch array 130 operating at hold time according to an embodiment of the present invention.
During the hold time, the second selection unit S2 is configured to control the signal OL according to the offset0To OL4And OM0To OM4The control unit receives the offset adjustment voltage in the selected state or receives the common mode input voltage Vcmi in the unselected state. The offset adjustment voltage is a difference between the first adjustment voltage Vrt and the second adjustment voltage Vrb.
In more detail, in an embodiment, the sample-and-hold amplifying circuit 100 further includes an adjustment selecting unit 170 configured to select the first adjustment voltage Vrt and the second adjustment voltage Vrb according to different polarities for input. When the adjustment of the forward offset from the common-mode input voltage Vcmi is to be performed, the adjustment selecting unit 170 enables the second selecting unit S2 to receive the positive adjustment voltage Vrt-Vrb generated by subtracting the second adjustment voltage Vrb from the first adjustment voltage Vrt as the offset adjustment voltage. When the negative offset adjustment is to be performed with respect to the common-mode input voltage Vcmi, the adjustment selecting unit 170 enables the second selecting unit S2 to receive the negative adjustment voltage Vrb-Vrt generated by subtracting the first adjustment voltage Vrt from the second adjustment voltage Vrb as the offset adjustment voltage.
The third selection unit S3 electrically couples the second selection unit S2 to a corresponding capacitor (e.g., a corresponding switch circuit SM) according to the mode control signal CKM0To SM4And SL0To SL4Bit capacitance CM0To CM4And CL0To CL4) The first end of (a).
The gain selection unit Sg enables the gain adjustment capacitor Cg to receive the common mode input voltage Vcmi according to the mode control signal CKM.
Therefore, in the hold-time operation mode, the sample-and-hold amplifying circuit 100 can be switched according to the switching circuit SM included in the positive terminal switching array 1300To SM4And SL0To SL4A second selection unit S2 and a third selection unit S3 respectively provided with a positive terminalBit capacitance CM of capacitor array 1100To CM4And CL0To CL4The offset of the positive input voltage Vip with respect to the common mode input voltage Vcmi is adjusted by the bit combination connection relationship of (1).
For example, when the connection to be made is represented by a bit (0111101111), the switching circuit SM3To SM0And SL3To SL0The first selection unit S1 makes the bit capacitances CM corresponding to the 9 th to 6 th and 4 th to 1 st bits respectively3To CM0And CL3To CL0The other switching circuits make the other bit capacitors in the unselected state to receive the common mode input voltage Vcmi.
In one embodiment, when all bit capacitors CM are present0To CM4And CL0To CL4The connection of (a) is all 1 in bit (e.g., 1111111111 of 10 bits), i.e., when all receiving the offset adjustment voltage, the total adjustment amount will be the value of the offset adjustment voltage (Vrt-Vrb or Vrb-Vrt). When all bit capacitors CM0To CM4And CL0To CL4The connection relationships of (a) are all 0 (e.g. 10-bit 0000000000), that is, when the common mode input voltage Vcmi is received, the total adjustment amount will be 0. Thus, all different bit combinations from high to low, up to 2M+NOffset adjustment of step size.
Similarly, the sample-and-hold amplifier circuit 100 can switch the switching circuit SM included in the array 140 according to the negative terminal0To SMnAnd SL0To SLnA second selection unit S2 and a third selection unit S3 respectively provided with a bit capacitor CM of the negative side capacitor array 1200To CMnAnd CL0To CLnThe offset of the negative input voltage Vin is adjusted according to the bit combination connection relation. And will not be described in detail herein.
After the gain adjustment of the sampling time and the offset adjustment of the holding time, the positive side capacitor array 110 and the negative side capacitor array 120 will generate a positive output voltage Vp and a negative output voltage Vn from the positive output terminal PT and the negative output terminal NT electrically coupled to the second terminal of each bit capacitor.
The differential output circuit 150 is configured to output the positive output voltage Vp and the negative output voltage Vn as a pair of differential output signals Vop and Von.
In one embodiment, the differential output circuit 150 includes an amplifier 180, a first coupling capacitor CP1, a second coupling capacitor CP2, and first to sixth switches SW1 to SW 6.
The amplifier 180 includes a positive amplifier input terminal (denoted by the '+' sign in fig. 1A), a negative amplifier input terminal (denoted by the '-' sign in fig. 1A), a positive amplifier output terminal (denoted by the '+' sign in fig. 1A), and a negative amplifier output terminal (denoted by the '-' sign in fig. 1A).
The positive amplifier input terminal is electrically coupled to the negative output terminal NT for receiving the negative output voltage Vn. The amplifier input negative terminal is electrically coupled to the positive output terminal PT for receiving the positive output voltage Vp. The amplifier output positive terminal and the amplifier output negative terminal are configured to output the pair of differential output signals Vop and Von according to the positive output voltage Vp and the negative output voltage Vn.
The first coupling capacitor CP1 and the second coupling capacitor CP2 each include a first terminal and a second terminal, the first terminal of the first coupling capacitor CP1 is electrically coupled to the negative amplifier input terminal, and the first terminal of the second coupling capacitor CP2 is electrically coupled to the positive amplifier input terminal.
As shown in fig. 2, during the sampling time, the first switch SW1 and the second switch SW2 are respectively configured to make the amplifier input positive terminal and the amplifier input negative terminal receive the common mode input voltage Vcmi according to the control of the mode control signal CKM.
The third switch SW3 and the fourth switch SW4 are respectively configured to enable the second terminals of the first coupling capacitor CP1 and the second coupling capacitor CP2 to receive the common mode output voltage Vcmo according to the control of the mode control signal CKM.
Further, as shown in fig. 3, during the hold time, the fifth switch SW5 and the sixth switch SW6 are respectively configured to electrically couple the second terminal of the first coupling capacitor CP1 to the positive amplifier output terminal and the second terminal of the second coupling capacitor CP2 to the negative amplifier output terminal according to the control of the mode control signal CKM.
In one embodiment, the positive side capacitor array 110 and the negative side capacitor array 120 have a first equivalent capacitance value according to the bit combination connection relationship during the sampling time. The first coupling capacitor and the second coupling capacitor have coupling capacitance values respectively. The positive side capacitor array 110 and the negative side capacitor array 120 generate a gain of the first equivalent capacitance value relative to the coupling capacitance value.
The positive side capacitor array 110 and the negative side capacitor array 120 have a second equivalent capacitance value in the bit combination connection relationship during the hold time. The first coupling capacitor and the second coupling capacitor have coupling capacitance values respectively. The positive side capacitor array 110 and the negative side capacitor array 120 are offset by a ratio of the second equivalent capacitance to the coupling capacitance.
In more detail, the difference Vop-Von of the differential output signals Vop and Von can be expressed as:
Vop-Von ═ (Vip-Vin) × GA ± (Vrt-Vrb) × OFF (formula 1)
Wherein GA and OFF are gain and offset, respectively, and can be further expressed as:
GA＝(CGMSB+(CGLSB)/(CTLSB+ Cb))/Cf (formula 2)
OFF＝(COMSB+(COLSB)/(CTLSB+ Cb))/Cf (formula 3)
Wherein, CG isMSBAnd COMSBThe gain adjustment capacitor and the high-order bit capacitor respectively have a total capacitance value under a one-bit combination connection relationship:
CGMSB＝Cg+CMn×gMn+CMn-1×gMn-1+…CM0×gM0(formula 4)
COMSB＝Cg+CMn×oMn+CMn-1×oMn-1+…CM0×oM0(formula 5)
CGLSBAnd COLSBThe total capacitance values of the low-order bit capacitors under the one-bit combination connection relation respectively are as follows:
CGLSB＝CLn×gLn+CLn-1×gLn-1+…CL0×gL0(formula 6)
COLSB＝CLn×oLn+CLn-1×oLn-1+…CL0×oL0(formula 7)
gMn、gMn-1、…gM0And gLn、gLn-1、…gL0Respectively, the unit bit gain of each bit capacitor. It is 1 when the bit capacitance is selected to adjust the gain and 0 when the bit capacitance is not selected to adjust the gain. oMn、oMn-1、…oM0And oLn、oLn-1、…oL0The unit bit offset amounts of the respective bit capacitors are respectively. It is 1 when the bit capacitance is selected to adjust the offset and 0 when the bit capacitance is not selected to adjust the offset.
CTLSBThe sum of the capacitance values of all low-level capacitors:
CTLSB＝CLn+CLn-1+…CL0(formula 8)
Cb is the capacitance of the intermediate capacitor Cb. Cf is a capacitance value of each of the first coupling capacitor CP1 and the second coupling capacitor CP 2.
When the Cb value is C, CLnIs 2LnC、CMnIs 2McC. Cf is 2Ln+1C and Cg/Cf is gc, and Mn、Mn-1、…M0To Ln、Ln-1、…L0When the mappings are K, K-1, … 0, (equation 2) and (equation 3) can be simplified as follows:
GA＝gc+gK/21+gK-1/22+gk-2/23+…g0/2K+1(formula 9)
OFF＝oK/21+oK-1/22+ok-2/23+…o0/2K+1(formula 10)
Therefore, after the gain GA and the offset OFF are substituted back to (equation 1), the following results are obtained:
Vop-Von＝(Vip-Vin)×(gc+gK/21+gK-1/22+gk-2/23+…g0/2K+1)±(Vrt-Vrb)×(oK/21+oK-1/22+ok-2/23+…o0/2K+1) (formula 11)
In one embodiment, the sample-and-hold amplifying circuit 100 further includes a control circuit 190 configured to determine a difference between the pair of differential output signals Vop and Von with respect to the voltage input range RAN of the analog-to-digital converting circuit 160, so as to generate the gain control signal GL according to the difference0To GLn、GM0To GMnAnd offset control signal OL0To OLnAnd OM0To OMnAnd the adjustment is carried out through a feedback mechanism.
It should be noted that the above-mentioned embodiments are only examples. In other embodiments, one of ordinary skill in the art can make modifications without departing from the spirit of the present invention.
In summary, the sample-and-hold amplifier circuit of the present invention can effectively adjust the gain and offset of the input signal with respect to the common-mode input voltage, and is in line with the input range of the back-end circuit.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
[ notation ] to show
100: sample-and-hold amplifying circuit
110: positive side capacitor array
120: negative side capacitor array
130: positive side switching array
140: negative side switching array
150: differential output circuit
160: analog-to-digital conversion circuit
170: adjustment selection unit
180: amplifier with a high-frequency amplifier
190: control circuit
Cb: intermediate capacitor
Cg: gain adjusting capacitor
CKM: mode control signal
CL0To CLn、CM0To CMn: bit capacitor
CP 1: first coupling capacitor
CP 2: second coupling capacitor
GL0To GLn、GM0To GMn: gain control signal
NT: negative output end
OL0To OLn、OM0To OMn: offset control signal
PT: positive output terminal
RAN: voltage input range
S1: first selection unit
S2: second selection unit
S3: third selection unit
SL0To SLn、SM0To SMn: switching circuit
SW1 to SW 6: first to sixth switches
Vcmi: common mode input voltage
Vcmo: common mode output voltage
Vin: negative input voltage
Vip: positive input voltage
And Vn: negative output voltage
Vop, Von: differential output signal
Vp: positive output voltage
Vrb: second regulated voltage
Vrt: a first regulated voltage.

Claims (10)

1. A sample-and-hold amplification circuit, comprising:
a positive side capacitor array and a negative side capacitor array each comprising a plurality of bit capacitors each having a first end and a second end, wherein the second ends of the bit capacitors of the positive side capacitor array are electrically coupled to a positive output end and the second ends of the bit capacitors of the negative side capacitor array are electrically coupled to a negative output end;
a positive side switching array and a negative side switching array, each configured to enable the equipotential capacitors to receive a polarity input voltage from the first end of each equipotential capacitor according to a first bit combination connection relationship for gain adjustment relative to a common mode input voltage during a sampling time, and each configured to enable the equipotential capacitors to receive an offset adjustment voltage from the first end of each equipotential capacitor according to a second bit combination connection relationship for offset adjustment relative to the common mode input voltage during a holding time, and to generate a positive output voltage and a negative output voltage at the positive output terminal and the negative output terminal, respectively; and
a differential output circuit configured to output the positive output voltage and the negative output voltage as a pair of differential output signals.
2. The sample-and-hold amplification circuit of claim 1, wherein the positive side switching array and the negative side switching array each comprise a plurality of switching circuits each having:
a first selection unit configured to receive the polarity input voltage in a selected state or the common mode input voltage in an unselected state according to a control of a gain control signal during the sampling time, wherein the polarity input voltages corresponding to the positive side switching array and the negative side switching array are a positive input voltage and a negative input voltage, respectively;
a second selection unit configured to selectively receive the offset adjustment voltage in the selected state or the common mode input voltage in the unselected state during the holding time according to control of an offset control signal; and
a third selection unit configured to electrically couple the first selection unit to the first terminal of a corresponding one of the capacitors during the sampling time according to a control of a mode control signal, and to electrically couple the second selection unit to the first terminal of a corresponding one of the capacitors during the holding time.
3. The sample-and-hold amplifier circuit of claim 2 wherein the positive side capacitor array and the negative side capacitor array further comprise a gain-adjusting capacitor having a first end and a second end, respectively, the second end of the gain-adjusting capacitor of the positive side capacitor array being electrically coupled to the positive output end, the second end of the gain-adjusting capacitor of the negative side capacitor array being electrically coupled to the negative output end;
the positive side switching array and the negative side switching array respectively comprise a gain selection unit configured to enable the gain adjustment capacitor to receive the polarity input voltage for gain adjustment relative to the common mode input voltage during the sampling time, and enable the gain adjustment capacitor to receive the common mode input voltage during the holding time;
the capacitance values of the positive terminal gain capacitor and the negative terminal gain capacitor enable the polar input voltage to generate more than one time of gain.
4. The sample-and-hold amplifier circuit as recited in claim 2, wherein the differential output circuit is electrically coupled to an analog-to-digital converter circuit, the sample-and-hold amplifier circuit further comprising a control circuit configured to determine a difference between the pair of differential output signals with respect to a voltage input range of the analog-to-digital converter circuit, and to generate the gain control signal and the offset control signal according to the difference.
5. The sample-and-hold amplifier circuit of claim 2, wherein the differential output circuit comprises:
an amplifier, comprising:
an amplifier input positive terminal electrically coupled to the negative output terminal for receiving the negative output voltage;
an amplifier input negative terminal electrically coupled to the positive output terminal for receiving the positive output voltage; and
an amplifier output positive terminal and an amplifier output negative terminal configured to output the pair of differential output signals according to the positive output voltage and the negative output voltage;
a first switch and a second switch respectively configured to enable the amplifier input positive terminal and the amplifier input negative terminal to receive the common mode input voltage according to the control of the mode control signal during the sampling time;
a first coupling capacitor and a second coupling capacitor, each of which includes a first end and a second end, the first end of the first coupling capacitor is electrically coupled to the negative input terminal of the amplifier, and the first end of the second coupling capacitor is electrically coupled to the positive input terminal of the amplifier;
a third switch and a fourth switch respectively configured to enable the second ends of the first coupling capacitor and the second coupling capacitor to receive a common-mode output voltage according to the control of the mode control signal during the sampling time; and
a fifth switch and a sixth switch respectively configured to electrically couple the second terminal of the first coupling capacitor to the positive amplifier output terminal and the second terminal of the second coupling capacitor to the negative amplifier output terminal during the hold time according to the control of the mode control signal.
6. The sample-and-hold amplifier circuit as recited in claim 5, wherein the positive side capacitor array and the negative side capacitor array have a first equivalent capacitance and a second equivalent capacitance in the first bit combinational connection and the second bit combinational connection, respectively, the first coupling capacitor and the second coupling capacitor have a coupling capacitance, respectively, the positive side capacitor array and the negative side capacitor array generate a gain of the first equivalent capacitance relative to the coupling capacitance, and the positive side capacitor array and the negative side capacitor array generate an offset of the second equivalent capacitance relative to the coupling capacitance.
7. The sample-and-hold amplifier circuit of claim 1, further comprising an adjustment selection unit configured to cause the second selection unit to receive a positive adjustment voltage generated by subtracting a second adjustment voltage from a first adjustment voltage as the offset adjustment voltage when a positive offset adjustment is performed with respect to the common-mode input voltage during the holding time, and to cause the second selection unit to receive a negative adjustment voltage generated by subtracting the first adjustment voltage from the second adjustment voltage as the offset adjustment voltage when a negative offset adjustment is performed with respect to the common-mode input voltage during the holding time.
8. The sample-and-hold amplifier circuit as recited in claim 1, wherein the positive side capacitor array and the negative side capacitor array each comprise an equivalent capacitor divided into a set of high-side capacitors and a set of low-side capacitors, the second ends of the equivalent capacitors of the set of high-side capacitors are directly electrically coupled to the positive output terminal or the negative output terminal, and the second ends of the equivalent capacitors of the set of low-side capacitors are electrically coupled to the positive output terminal or the negative output terminal through an intermediate capacitor.
9. The sample-and-hold amplifier circuit as in claim 1, wherein the number of said equipotential capacitors is N to generate 2NGain of order and offset.
10. The sample-and-hold amplifier circuit as in claim 1, wherein the maximum gain produced by the equipotential capacitors is 1.
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