TW200822531A - Very-high-speed low-power low-hold pedestal fully differential CMOS sample-and-hold circuit - Google Patents

Abstract

A low-hold-pedestal sample-and-hold circuit is a fully differential CMOS low-power very-high-speed sample-and-hold circuit. This sample-and-hold circuit is bases on linearized input switch to achieve high sampling linearity. The linearized switch on-resistance is nearly constant and small. Fully differential structure results in reduction of common-mode hold pedestal and noise. This allows smaller hold capacitances than in conventional single-ended case, thereby relaxing the trade-off between the sampling speed and sampling precision.

Description

200822531 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a sample storage circuit (Sample_and-Hold Circuit). This kind of sampling and holding circuit can not only operate very-high-speed, but also has a low-storage substrate (1〇\¥-11〇1 (1-卩6(1631&1), low power (1(^ Fully0^^1*) fully differential sample-and-hold circuit. _ [Prior Art] Figure 1 shows a traditional Miller-Capacitance_based Sample 100 -and_Hold circuit, the details are detailed in the following two papers: / brother J.Cz> CM rule, ν〇1·26, ρρ·643-651, April 1991 and / now five 7>ωlike. (10) CfrcWb iSys /ew-/, vol. 45, ρρ· 198-201, February 1998), which includes two gold-oxide half (MOS) switches 102 and l〇4 for sampling, two holding electric φ capacitances 1〇6 and 1 〇8, a single-ended amplifier with a gain of A (where a is a value), and a high input-impedance unity-gain buffer 112. Capacitance of Figure 1. 114 and 116 are the parasitic capacitances of the storage capacitors 108 and 1 〇 6. The conventional Miller capacitance sampling and holding circuit 00 is in a sampling mode (sample M〇de) and a hold mode have different equivalent storage capacitor values. In this sampling mode, the equivalent storage capacitor value is small, which is convenient for fast sampling. In the save mode, The value of the equivalent storage capacitor is large, which ensures that the voltage stored in the circuit 100 has a lower storage base (4) d 0955-A21636TWF(N2); g|〇ri〇uSJien 5 200822531 • pedestal), the goal is 5 The Le Capacitance Sample Preservation Circuit (10) can be quickly sampled and has considerable accuracy. However, the non-linear effect of the on-resistance (〇n._e) of the above MOS switches (10) and 1〇4), the parasitic capacitance of the switch (10), P_tlC Capacitor, And the signal phase_off charge injection effect (^ignal dependent SWltch charge is the sampling of the Miller capacitance sampling and holding circuit (10). The above-mentioned Μ(10) spray 1G2) is used to save the electricity of the ^^^ and the stabilization time (the stability of the (four) effect, especially the apparent resistance must be small and the conductive switch of the sample switch is the 电 电 wire _1GG_ Single-ended: structure: = source noise and charge injection effect _, sub-Asia has no significant function. [Summary] The present invention proposes a novel ultra-high-speed low-power low-storage substrate all-different 'complementary metal oxygen The half-sampling save circuit, which is a linearized open I. The switch is used for sampling' and uses the fully-differential structure (10) to effectively eliminate the common mode storage substrate h* pedest umbrella and Noise. The linear ultra-high-speed, low-power, low-accommodating, and low-powered-in-the-middle-mode-constructed-type gold-oxygen half-sampling storage has a smaller storage capacity than the conventional sampling and storage circuit. Compared with the conventional sampling and holding circuit 1 , the present invention

〇 955-A21636TWF (N2); glorj〇us_tien X 6 200822531 := The sampling and saving circuit has a faster sampling speed and better. The new sampling system can be applied to the low power range. The ultra-high-speed, low-power, low-storage substrate of the road that is revealed by Haoyue is fully differential. The pre-sampling circuit is a fully differential core. The wheel-in terminal of the sample-save circuit is driven by the positive end of the signal. The composition, and the sample protection number negative -P ^ ^ ^ ^ to the private circuit output 柒 is composed of a round of signal output (four) negative end. The sample-storage circuit includes a fully differential amplifier, and the fully-differential 4-visitor 抑 目 峪 includes a positive wheel input terminal, a negative input terminal, a positive output terminal, and a negative Output. In the circuit, a -the "wire" is connected between the full-shift amplifier and the -th node, and a second capacitor is coupled to the all-signal negative input and the first node A third capacitor is connected between the negative output of the input amplifier and the second node, and the king: the light is connected to the positive input of the fully differential amplifier and the first y = between. The first capacitor has the same capacitance value as the third capacitor, and the second capacitor has the same capacitance value as the fourth capacitor. Furthermore, the present invention includes a first linearization switch, a first complementary transfer switch, a parametric switch, and a second complementary transfer switch. The first and the 哕: the on-resistance of the linearized switch is approximately _ small fixed value. The first line = the coupling is coupled between the positive end of the input signal and the first node. The first complementary transfer switch is coupled between the positive output of the fully differential amplifier and the negative input of the differential amplifier. The second linearization switch is coupled between the negative end of the input signal and the second node. The second complementary transmission is "coupled" to the negative output of the fully differential amplifier and the fully differential: open 0955-A21636TWF (N2); glorious_tien-7 200822531 = between the two ends of the input. Still package -... The first buffer is the first buffer of the wheel ginger to pick up the first point and the output money positive end. The drive and the wheel ^ respectively light and output the object _ the second node and the: out Wheeled end

Far more than high speed, low power, low storage base, all poor:, /:. The sample circuit can be in the -sampling mode as well as - the gold-supplied oxygen-half-the second linearization switch and the above-mentioned first - invitation: wood. When the upper switches are all turned on, the sample preserving circuit is at:;;; complementary transmission of the first-and second linearization switches and the first mode described above. When the upper switch is non-conducting, the sample preserving circuit is transmitted for the above and other purposes of the present invention. It is to be understood that the preferred embodiments are set forth below, and that they can be used in the following embodiments. . Evaluation [Embodiment], Fig. 2 is an embodiment of the ultra-high-speed, low-power, low-protection, silk-bottom fully differential mutual-type gold-oxygen half-sampling circuit of the present invention. Ultra-high speed low power low security sub-base differential differential gold-oxygen half-sampling save circuit 2 (8) includes an input L唬正jr and Vin+, an input signal negative terminal Vin•, an output signal positive terminal V〇m+, an output a signal negative terminal Vout_, a full differential amplifier 2〇2, a first electric valley C1, a second capacitor C2, a third capacitor C3, a fourth electric valley c4, a first linearization switch Sn, A second linearization switch s, 2, a first complementary transfer switch Sn, a second complementary transfer switch Si2, a first buffer 204, and a second buffer 2〇6. The fully differential amplifier 202 has a gain value of a and has a positive 0955-A21636TWF (N2); g|〇ri〇us_tien 8 200822531, an input terminal Va_in+, a negative input terminal Va_in_, and a positive output terminal Va_〇 +, and a negative output Va_. ,. The far brother, the electric valley C, has the same capacitance value as the third capacitor c3. The e-Hidden Valley C2 has the same capacitance value as the fourth capacitor C4. The first capacitor C is coupled between the positive output terminal Va_〇+ of the fully differential amplifier 202 and a first node Vx+. The second capacitor c2 is coupled between the negative input terminal va_mJ of the fully differential amplifier 202 and the first node vx+. The third capacitor C3 is connected to the negative output terminal Va_· of the fully differential amplifier 202. - between • and a second node vx-. The fourth capacitor C4 is coupled between the positive input terminal va_m+a of the fully differential amplifier 202 and the second node vx_. In Fig. 2, capacitors C1B, C2B, C3B, and C4B are the parasitic bottom capacitances of the above-mentioned capacitors Ci, C2, C3, and C4, respectively (the parasitic b〇tt〇n>piate capacitance) ° the first linearization switch sn surface Connected between the positive terminal vin+ of the input signal and the first node Vx+. The second linearization switch S/2 is coupled between the input signal negative terminal vin_ and the second node vx_. The first complementary transmission 10 switch is connected to the positive terminal va of the fully differential amplifier 202. + and between the negative input terminal Va_in_ of the fully differential amplifier 202. The second complementary transfer switch Sc | is connected to the negative output terminal Va_ of the fully differential amplifier 202. - and between the positive input terminal Va of the fully differential amplifier 202. The input end and the output end of the first buffer 204 are respectively coupled to the first node vx+ and the output signal positive terminal v. ·. The input end and the output end of the second buffer 206 are respectively coupled to the second node Vx- and the output signal negative terminal V011t_. The above-mentioned brothers and brothers can be a single input impedance single gain slow 0955-A21636TWF (N2); glorious_tien 9 200822531 (high input-impedance unity-gain buffer). The first or second buffer may be a source follower. When the above switches (Sn, S, 2, Sn, and Sc) are all turned on, the take-off save circuit 200 is in a sampling mode (sampie m〇(je). The action of the fully differential amplifying 202 is like a single gain (unity_gain) circuit,

A virtual short is provided between the input and output of the fully differential amplifier 202. The sampling and holding circuit 2 samples the differential input voltage between the positive terminal vm+ of the input signal and the negative terminal Vm_ of the input signal to the capacitors (Ci, C2, C3, and Q), and then passes through the first And the second buffers 204 and 206 are delivered to the positive end v of the output signal. Repair and the input: signal negative terminal VQut_. When the upper pass switches (Sn, So, Sn, and Sw) are not turned on, the sample save circuit 200 is in a save mode (h〇ld m〇de). The above capacitors (q, C2, c: 3 and Co and the fully differential amplifier 2〇2) constitute a feedback amplifier. Based on a Miller feedback effect, the equivalent storage capacitor of the sample preserving circuit 200 The value will be much larger than the equivalent 2 storage capacitor value in the sampling mode. Since the linearization off S/i and the on-resistance are small and approximate to a certain value, the high-frequency sampling distortion of the sampling and holding circuit 2〇〇 can be Improved. The above linearization switches 8/1 and & 2 can reduce signal-dependent charge injection. Since the sample-and-hold circuit 2 uses a fully differential architecture, The charge injection and the clock penetration effect. The error voltage generated by the "feedthrough" can be offset by the sample-storing power supply 'differential output terminal (V〇ut+, V〇ut_). Therefore, the traditional sampling of the road to the 0955-A21636TWF (N2); gl〇ri〇us^tien 10 200822531 - can save the substrate and noise problems can be greatly improved. The capacitance required for the sample holding circuit 2 is therefore smaller than that of the conventional sample holding circuit. In an embodiment of the invention, the fully differential amplifier 2〇2 further includes an amplifier circuit, a capacitor neutralization circuit, a common mode feedback circuit, and an output buffer circuit. The amplifying circuit is for amplifying the signals of the positive wheel input va in+ and the negative input terminal va"n_. The amplified signals are transmitted to a third node and a fourth node, respectively. The capacitor neutralization circuit is coupled to the amplification circuit to eliminate the Miller capacitance effect generated by the amplification circuit at the input of the fully differential amplifier 2〇2#. The common mode feedback circuit is used to control the level of a common mode voltage of the third node and the fourth node. The output buffer circuit has a high input impedance and a low turn-off impedance for transmitting signals of the third node and the fourth node to the negative output terminal Va_0_ and the positive output of the fully differential amplifier 202, respectively. end

Va_0+. - Figure 3 is a complementary MOS inverter 300 comprising an NMOS transistor Mn and a pM 〇s transistor. The charge carriers of the electric crystals Mp and Mn are respectively - and μρ, the single-value area capacitance of the oxide layer is c_ and the effective overnight width/length are Wn/Ln and Wp/Lp L, respectively. ^^.Wn/Ln, /V=/vCoxp'Wp/Lp. When A is , the small signal voltage gain of the CMOS inverter 300 is a fixed value. The CMOS inverter operates in class AB and therefore consumes less power. Fig. 4 is an embodiment of the above amplifying circuit and capacitor neutralizing circuit. The amplifying circuit can be implemented by a first CM 〇s inverter Ιηνι and a second 0955-A21636TWF(N2); g!ohous_tien 200822531 CMOS inverter InV2. The small signal voltage gains of the above CMOS inverters Iim and Inv2 are fixed values. The capacitor neutralization circuit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, a first PMOS transistor Mpl, and a second pmS transistor Mp2. The positive input terminal va_m+ of the fully differential amplifier 200 is coupled to the first CMOS inverter Invii input terminal, and the negative input terminal Va"n_ is coupled to the input terminal of the second CMOS inverter Inv2. The source and the drain of the first nm 〇S transistor Mnli and the source and the drain of the first PMOS transistor Mpl are coupled to the output of the second CMOS inverter lnV2. The first nm 〇S transistor Mn1 is coupled to the first PMOS transistor Mpl2 to the positive input terminal va"n+. The source and the drain of the second NMOS transistor mii2 and the source and the drain of the second pmS transistor MP2 are coupled to the output of the first CM〇s inverter Ιηνι. The second NMOS transistor and the second PMOS transistor Mp22 are coupled to the negative wheel terminal. The aspect ratio (W/L) of the first NM 〇 s - I 体 body Mn1 is half of the width-to-length ratio of the Nm 〇s transistor of the first CM 〇 s inverter InVi. The width-to-length ratio of the first:NM〇s transistor Mu is -half of the aspect ratio of the NM〇s transistor of the second CMOS inverter. The width-to-length ratio of the first-PMOS transistor is half of the aspect ratio of the PM-S transistor of the first-C]y[〇s inverter_. The width-to-length ratio of the second PM〇s transistor Mp2 is -half of the aspect ratio of the second CM〇s inverter. The capacitance neutralization circuit composed of the above transistors HA and Mp2 can greatly improve the preservation substrate error. Figure 5 is an embodiment of a fully differential amplifier of the present invention. A full-embedding amplifier 5GG uses the amplification circuit shown in Figure 4 and the capacitance 0955-A21636TWF(N2); gloriousJien 200822531

Neutralization circuit. The fully differential amplifier 500 further includes a common mode feedback circuit 502 including a third CMOS inverter Inv3, a fourth CMOS inverter I11V4, a fifth CMOS inverter Inv5, and a sixth CMOS counter. Phaser Inv6. The common mode feedback circuit 502 and the output end of the first CMOS inverter Iirv are connected to a third node Vint-, and the output end of the second CMOS inverter Inv2 is coupled to a fourth node Vmt+ . The input terminal of the third CMOS inverter Inv3 is coupled to the third node Vmt_, and the output terminal and the input and output terminals of the fourth CMOS inverter Inv4 are coupled to the fourth node Vmt+. The input end of the sixth CMOS inverter Inv6 is coupled to the fourth node Vint+, and the output end and the input and output terminals of the fifth CMOS inverter inV5 are coupled to the third node Vint_. The common mode feedback circuit 502 is used to control the common mode (c〇mmon-mode) voltage level of the younger brother Villt+ and the brother Erlang point Vin. For the sake of simplicity, the above CMOS inverter Inv3 is assumed. I11V4, I11V5, and Inv6 can have matched circuit characteristics. It is assumed that the NMOS and PMOS transistors used in these CMOS inverters Inv3, Inv4, jnV5, and inV6 are all operated in strong inversion and saturation regions. The relationship between the output current of each of the above-mentioned CM〇s inverters Inv3, I11V4, Invs, and Inv6 and its input voltage (Vin) is: Iout=gm.(Vin-Vc), where a single inverter is used. Transconductance gm and voltage % are as follows:

+ L, Vtll and Vtp are divided into gm two/5inv. (Vdd+Vtp-Vtn), Vc> is the threshold voltage of the NMOS transistor and the PMOS transistor. "When! ^^ voltage". For the phase device, 0955-A21636TWF(N2); glorious_fien 200822531 V —匕〆"Ά 〇C 2 The relationship between the output currents of the above CMOS inverters Inv3, Inv4, Ιην5 and ιην6 and their input voltages are: I〇 3 = gm3.(Vmt,VC), I〇4 - gm4'(Vint+ - Vc), I〇5 = gm5.(Vint,Vc), I〇6 = gm6,(Vint+ - Vc) 0 The fourth nodes Vint_ and Vint+ can be expressed as Vint-- and Vint+-Vintc+Vintd/2', wherein the internal common-mode voltage is Vinct, internal differential-mode voltage It is Vindd. Therefore, the following relationship can be obtained: I〇3 + I〇4 = (gm3 + gm4)( Vintc - Vc) + (gm4 - gm3) ·%福/2, I〇5 + 1. 6 II ( Gm5 + gm6)( Vmtc - Vc) — (gm5 - gm6) ·Υιηί(1/2 〇如弟5图不的'The above CMOS inverters I11V4 and Inv5 are connected as resistors at the fourth node vmt+, third Between the point Vlnt_ and the common mode voltage Vc, the resistance values are gm4 and 丨/gm5, respectively. The CMOS inverters I11V3 and inV6 respectively inject currents gm3.dVmt) and gmdVc-VmnO into the above-mentioned resistors. In terms of the output signal, there is a virtual load on the second point Vint_ (vjrtuai i〇a(j), whose value is l/(gm5 + gm6) · 'The virtual load on the fourth node Vmt+ is l/( Gnl3+gm4) For the differential output number, if gm3 = gm4 and = gm6, the third and fourth nodes (vmt- and Vmt+) are unloaded. In an embodiment of the invention, the above CMOS Inverter InV3, 0955-A21636TWF(N2); gl〇rious_tien 14 200822531

The circuit characteristics of Inv4, hiv5, and Inv6 are perfectly matched and the voltage sources are both vdd, thus having the same transduction (gm3 = gm4 = gm5 = gm6). The common mode feedback circuit 502 provides a low ohmic load for the common mode output signal, and the common mode feedback circuit 502 provides an approximately open load for the differential mode output signal. Static common mode voltage

(quiescent common-mode voltage) will be Vc. If the above CMOS

The assumptions of inverters In", In%, Invs, and InV6 (/3n=/5p=/5mv) are not true, but the circuit characteristics are still perfectly matched. For common mode signals, the load resistance is nonlinear: For the differential signal, all even (even) and odd (odd) nonlinear terms are eliminated. Details are detailed in this paper. IEEE J· Solid-State Circuits, νο\· 27, ρρ Ά2

February 1992 0 ′ As shown in Figure 5, the full-amplifier amplifier's turn-out buffer circuit consists of a -first-source follower Buffi and a second source-coupled crying-resistant f2. The third node V′′ is connected to the first source and is crying; The output of the first-source follower is reduced. • The input is connected to the negative output of the dynamic amplifier 500. The fourth section of the second source is connected to the input of the lighter. The second source If Buff2 is connected to V:_ of the fully differential amplifier 5 (10). ^Because the source of the face-to-face screamer has a low beta: beta, it will cause the fully differential amplifier '5(8) to have a larger bandwidth^Help, „the ultra-high speed, low power, low storage base, all the difference The sampling speed of the dynamic complementary to oxygen half-sampling preserving circuit. The linear linear 6 diagram is the linearization of the case - an embodiment of the method 0955-A21636TWF (N2); g|〇rj〇us_tien 15 200822531 The switch 600 includes - The third transistor Μ 4, one 箆 $ two S transistor Μ 3 3, ~ the fourth NM 〇 s electric Japanese and Japanese limbs Mn4 弟 five NMOS electric $ _ M, a kinky crystal Μ 6, a 筮 winter ΧΤΛ electric day limbs, One brother six NMOS: 116 brother seven NM 〇 S transistor Μ η7, - third PMOS 曰脰 mp3, a source follower 6 〇 2. The source of the day and the pole are coupled respectively 哕Λ A $ crystal V.,.. The fourth difficulty =: switch input... wheel output third NM0S Gong Yan carving A n4 source ground, the pole is coupled to the

The Japanese version of the n3 gate. The voltage of the fourth NM 〇s gate is controlled by a clock signal 反相 卩 轳 Mn Mn Mn Mn 。 。 。 。 。 。 。 。 。 。). The input end and the output end of the source with the coupling 602 are respectively coupled to the source and the gate of the third (4) I, so that the voltage difference between the gate and the source of the third NMOS transistor Mn3 Is a fixed value. The eosinophilic and the third P_s electro-crystal/M iNM〇S transistor Mn5 is the output terminal ;2; the source of the five L; the coffee line _^^ h _ MOS transistor Mn5 source and the The third PM0S transistor Mp3 has no face, the sixth surface s transistor

Record of Mn6. The source of the sixth NMOS transistor I is grounded. The gate voltage of the fifth NM0 S transistor Μn5 is controlled by the inverse signal (4) of the above clock signal. The gate galvanic dust of the sixth NMOS transistor I and the third pM 〇s transistor My is controlled by the clock signal. The source of the seventh NMOS transistor Mn7 consumes the voltage source Vdd, the drain is connected to the output terminal ν_ of the linearization switch 600, and the gate is lightly connected to the sixth NM 〇s transistor 及 ό and the extreme. The seven-NMOS transistor yjn7 is used to eliminate the signal-dependent feedthrough effect of the gate-drain overlap capacitance of the second NMOS transistor 〇α 〇0955-A21636TWF ( N2);glorious_tien 200822531 brothers 7, 8, 9, 10 and 11 are the super-idle low-power low-storage substrate full differential complementary metal-oxygen half-sampling preservation circuit 200 using the fully differential amplifier 500 and the The simulation result of the linearization switch 600 is Synopsys Hspice, and the simulation process is TSMC 〇.35/xm MIXED MODE (2P4M, 3.3V/5V) POLYCIDE. As shown in Figure 7

The peak-to-peak swing of the input differential sine wave (sinus〇idal) signal 7〇2 of the sampling and holding circuit is 1.2V, and the frequency is 8^24MHZ (f^=80.24MHz). . The frequency of the clock signal 706 used by the sample preserving circuit is 330 MHz, and the transition time (ts) of the clock signal 7〇6 is (Uns. The output differential signal generated by the sample preserving circuit is a signal. 704. The younger brother is the result of the model, the horizontal axis is the differential voltage difference between the positive and negative ends of the input signal (Vin+, Vm_), and the vertical axis is the positive and negative ends of the output signal (vout+, v〇ut0). The measured differential storage base (4) d Ped_(10) changes. Obviously, when the transition time is ο -, in the range of difference = input voltage side 6V 'the differential preservation substrate is differential input =. The big _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The sample-storage circuit is compared to the 'sample-storage circuit of the present invention' and the sample-save circuit of the present invention can achieve super-return speed and has a low-storage substrate. Ground = two is a storage substrate measured at different end points Reporting the differential measured by the positive and negative ends (V_+, V-) Preservation base 0955-A21636TWF(N2);g|〇rj〇us__tjen 17 200822531 * The base 902 is smaller than the single-end round-out signal terminal (ν_+ or ν__). Figure 10 shows the output differential. The result of the fast Fourier Transfom (FFT) signal (vQUt+, v.^). The frequency of the input differential signal 702 (fm = 80.24 MHz, 1.2 Vpp) results in a columnar spectrum labeled 1002. A third-order harmonic (|;hird_〇rder harmonic) is labeled as a columnar frequency of 1104. As shown in Figure 1, the fully differential architecture of the present invention substantially reduces even-order harmonics. The spectral wave, and the Total Harmonic Distortion (THD) is -68.3 dB. Figure 11 shows the frequency of the input differential signal 702 from ΙΟΜΉζ to 120 MHz (fln=10~120MHz, L2Vpp), The output differential signal is subjected to fast Fourier transform. When the frequency of the input differential signal 702 is 90 MHz, the total harmonic distortion amount is -67.98 dB, and the linearity of the sample holding stroke is equivalent to 11 effective bits. (eIYective nuni|3er 0f bits). At lower round-in frequency range , The linearity of the sample and hold circuits even better. • In order to compare the present invention with the performance of other traditional techniques, the present invention in a Figure of Ment (F.aM) value as a basis for comparison. Among them, the calculation method of F.O.M is: F.O.M 二一^^,

2 face X 八 ENOB is the effective value element (effect|ve number 〇f biis), forbearing the sampling frequency, P is the power consumption of the sample preservation circuit. The references mentioned in Figure i include: Macquarie Document 1 'A. B〇m, A Pierazzi, and c M〇 (4) di, “A (7) 匕 0955-A21636TWF (N2); glorious_t}en 200822531 • 185MS/s Track-and-hold in 0.35- //m CMOS/5 IEEE J. Solid-State Circuits, vol. 36? pp. 195-203, Feb. 2001 ; Reference 2, A· Baschirotto, “A low-voltage sample -and_hold circuit in standard CMOS technology operating at 40 Ms/s,'' IEEE Trans, on Circuits and Systems-II, vol. 48, pp. 394-399, Apr. 2001; and reference 3, Τ·S· Lee And C. C· Lu, “A 1.5V 50MHz Pscudo~Diffcrcxiti3.1 CIViOS S3, rtiplc~3, rici-PJ〇J (J Circuit \vith Lu Low Hold Pedestal, IEEE Transactions on Circuits and /, vol· 52, No. 9, pp·1752-1757, 2005. As can be seen from the graph 1, the performance of the sampling and holding circuit of the present invention far exceeds the conventional sampling and holding circuit. In this simulation, the operating voltage source voltage is 3V, the present invention The sampling and saving circuit has a sampling frequency of up to 33〇MHz, and the full-scale differential input range is up to 22Vpp. When the frequency of the number is 80.24MHz, the total harmonic distortion amount is _68 3dB, and the effective bit number is more than 11 bits. The differential wheel storage substrate of the present invention is below 〇.8mV. The F.aM of the present invention is 3.9G6x1 (r2 (MW/MHz).

Reference 1 Reference De 2 Process 0.35-/xm CMOS 〇.5-μπι CMOS sampling frequency 185MHz 40MHz 0955-A21636TWF(N2);g|〇ri〇us_tien ^ 200822531 foll-scale differential input range ι.〇νρρ 〇. 6Fpp 0.8 Vpp 12VPP Preservation substrate ^5.0mV ^0.8mV ^0.8mV drow rate ^1.0mV/us —1.2mV/us ^0.8mV/us Total harmonic distortion 45MHz 2MHz at 2.5MHz 80.24MHz -63dB -50dB -58.2dB -68.3dB Voltage Source 3.3V 1.2V 1.5 V 3V Power Consumption 70mW 1.2mW 2.6mW 26.4mW ENOB(bit) 10 8 9 11 FOM (μΨ/ΜΗζ) 3.695X10'1 1.171X10' 1 1.015xl0_1 3.906xl0"2 Figure 1 The present invention is disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention, and those skilled in the art, without departing from the spirit and scope of the present invention, A number of changes and modifications may be made, and the scope of the present invention is defined by the scope of the appended claims. 0955-A21636TWF(N2);glorious_tien 20 200822531 [Simplified illustration] # / A traditional Miller capacitor sampling and saving circuit; Complementary gold and oxygen half-turn = ^ speed low power Jianxian bottom full differential mutual 杈 save An embodiment of the circuit; ί:t: complementary CMOS (CMOS) inverter; ^ amplifying circuit and capacitor neutralization circuit of the invention & ^^ implementation mode;

Figure 5 is a full differential amplifier of the present invention = an implementation of the linearized switch of the present invention. Figure 2 is a simulation result of the embodiment of the present invention. [Main component symbol description] 100~ traditional Miller capacitor sampling and saving circuit; 102, HM~MOS switch; 106, 1〇8~ save capacitor, · 110~ gain single-ended amplifier of A; 112~ input impedance single gain Buffer; 114, 116~ save the parasitic capacitance of capacitors 1〇6 and 1〇8; 200~ ultra-high speed low power low-storage substrate full differential complementary gold-oxygen half-sampling save circuit of the invention; 202~ full differential Amplifier; 204, 206~ buffer; 300~CMOS inverter; 500~ fully differential amplifier; 0955-A21636TWF(N2); gl〇rious_tien 21 200822531 - 502~ common mode feedback circuit; 600~ linearization Switch; 602 ~ source follower; 702 ~ input differential signal; 704 ~ output differential signal; 706 ~ clock signal; 902 ~ output signal positive and negative (ν_+, Vout_) measured difference Dynamically save the substrate; • 1002~ The effect of the frequency of the input differential signal 702 (fm=80.24MHz) on the spectrum of Figure 10; The effect of the 1004~3rd harmonic generation on the spectrum of Figure 10 Buffi, Buff] ~ source with light device;

Ci, c2, c3, c4~ capacitor;

CiB, C2B, 〇3Β and C4B~capacitors Cl, C2, C3, C4 parasitic backplane capacitance; ck~clock signal; Xin Invrlnv6~CMOS inverter;

Mn, Mnl-Mn7~NMOS transistor;

Mp, Mpl-Mp3~PMOS transistor; S/l, S/2~ linearization switch; si2~complementary transfer switch; va_m+~ positive input terminal;

Va_in_~ negative input; va. +~ positive output; 0955-A21636TWF(N2);glonous_tien 22 200822531 . Vai~ negative output;

Vin+~ input signal positive terminal; Vin_~ input signal negative terminal; Vmt+~ fourth node;

Vlllt_~ third node; V〇ut+~ output signal positive terminal; V〇ut_~ output signal negative terminal; vx+~ first node; 10 vx_~ second node. 0955-A21636TWF(N2);glonous_t!en

Claims (1)

200822531 . X. Patent application scope: 1. An ultra-high speed, low power, low-storage substrate fully differential complementary gold-oxygen half-sampling circuit, including: an input signal positive terminal and an input signal negative terminal; And a negative end of the output signal; a fully differential amplifier having a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal; a first capacitor, a second capacitor, and a third The capacitor and the fourth Φ capacitor have the same capacitance value, the second capacitor and the fourth capacitor have the same capacitance value, and the two ends of the first capacitor are respectively coupled to the full differential The positive output end of the amplifier and a first node, the two ends of the second capacitor are respectively coupled to the negative input terminal of the fully differential amplifier and the first node, and the two ends of the third capacitor are respectively coupled to the fully differential a negative output end of the amplifier and a second node, the two ends of the fourth capacitor are respectively coupled to the positive input terminal of the fully differential amplifier and the second node; a first linearization switch and a first complementary transmission a first linearization switch coupled between the positive terminal of the input signal and the first node, the first complementary transfer switch coupled to the positive output of the fully differential amplifier and the fully differential Between the negative input of the amplifier; a second linearization switch and a second complementary transfer switch, the second linearization switch is coupled between the negative end of the input signal and the second node, the second complementary a transfer switch coupled between the negative output of the fully differential amplifier and the positive input of the fully differential amplifier; and a first buffer and a second buffer, the first buffer of the input 0955-A21636TWF (N2); glorious_tien 24 200822531 The input end and the output end respectively _ the $- node and the input and output end of the second buffer respectively consume the second; the second: the negative end of the signal; the younger one point and the point When the second second-and second linearization switch and the first-disc-type transfer switch are both turned on, the ultra-high speed low-power low-meter base full differential complementary metal-oxygen half-sampling saves the electric-and-reduction type, When the above - and Two switches and the first linearization: 4: Complement = transfer switch are both non-conducting when the mutual ultrahigh Fully differential to each other Μ X Low power low to save the substrate The dynamic complement to the milk half sampling save circuit is in the - save mode. 2_ The ultra-high-speed low-power low-storage substrate full differential complementary gold-oxygen half-sampling storage circuit as described in claim 1 of the patent application scope, the full differential amplifier of the above-mentioned towel further comprises: a port-amplifying circuit, To amplify the signals of the positive input terminal and the negative input terminal, the amplified signals are respectively transmitted to a third node and a fourth node; a capacitor neutralization circuit is coupled to the amplifying circuit to eliminate the amplifying circuit in the whole a Miller capacitance effect generated at the input of the differential amplifier; a common mode feedback circuit for controlling the level of a common mode voltage of the third node and the fourth node; and an output buffer circuit having a high input The impedance and the low output impedance are used to transmit the signals of the 5th and the four nodes to the negative output and the positive output of the fully differential amplifier, respectively. 3 · The ultra-high speed low power low-storage substrate fully differential complementary gold-oxygen half-sampling preservation circuit as described in the second paragraph of the patent scope, wherein the above amplification circuit comprises: 0955-A21636TWF (N2); gloriousJien 25 200822531 a complementary gold-oxygen half-phase n, the input end and the wheel-out end are respectively coupled to the positive input terminal of the fully differential amplifier and the third node, and the first-complementary MOS inverter has a fixed The small signal voltage gain::: and . ' - the second complementary type of gold-oxygen half-inverter, the transmission is coupled to the full differential amplification, the crying self-钤λ W Han rebellion order and the flute-m into The wheel-in terminal and the fourth node, the brother-complementary half-reactor have a fixed small signal voltage core. 4. If the second base of the patent application scope is the third differentially-transfer type, the semi-sampling saves the Wei, the pot force ^ = the neutralization circuit includes: 〃甲上逑弘四节 I brother-n-type gold oxygen The semi-transistor, its source": and its idle pole is connected to the full differential amplifier of the "di-n ϋ ϋ gold-milk semi-transistor, the source of the new pole is pure two: two: and its gate coupling Connected to the negative wheel of the fully differential amplifier:; jin-di-, ρ-type gold-oxygen half m its key to the second and fourth point, sub-and its gate _ the full differential amplifier · And gossip, A - second P-type MOS semi-transistor, which has three poles of the touch pole, and its gate _ the negative wheel of the full differential amplifier = music 5. If you apply for the fourth section of Weiwei The force ς base differential differential complementary gold-oxygen half-sampling preservation circuit, the width-to-length ratio of the first type of gold-oxygen semi-transistor of the neutralization circuit is the n-type gold-oxygen half of the gold-oxygen half-reactor The width-to-length ratio of the complementarity second n-type MOS transistor of the transistor is the second complementary gold: half: 0955-Α21636TWF(N2); glorious_tien 26 200822531 phase η The width-to-length ratio of the aspect ratio of the gold-oxygen semi-transistor is -half of the aspect ratio of the oxygen-crystal of the first-complementary gold-gas semi-inverter, and the second ^^^^^^^^^ = Complementary gold-oxygen semi-inverting...type gold-oxygen semi-electrolytic substrate ==== =, the feedback circuit includes ·· ^ sampling and holding circuit, wherein the above-mentioned common mode second complementary MOS inverter has its wheel The third node of the third node is connected to the fourth node; a fourth complementary gold-oxygen half-reactor is coupled to the fourth node at both the wheel end and the output end; a semi-inverter, wherein the wheel-in end and the wheel-out end are connected to the third node; and a sixth complementary-type MOS inverter, the wheel-in end of which is coupled to the fourth node, and the output end is coupled The third node. 7. The ultra-high speed, low power, low-storage substrate fully differential complementary gold-oxygen half-sampling storage circuit as described in claim 6 wherein said third, fourth, fifth, and sixth complementary gold oxides The half inverter has the same transduction. 8. The ultra-high speed low power low-storage substrate full differential complementary metal-oxygen half-sampling storage circuit according to claim 2, wherein the above-mentioned wheel snubber circuit comprises a first source core device and a first The second source is coupled with the light, the third node is coupled to the input end of the first source follower, the first source 0955-Α21636TWF(N2); glorious Jien 27 200822531, the output of the follower is coupled a negative output of the fully differential amplifier, the fourth node is coupled to the input end of the second source follower, and the output of the second source follower is coupled to the positive of the fully differential amplifier Output. 9. The ultra-high speed low power low-storage substrate full differential complementary metal-oxygen half-sampling preservation circuit according to claim 1, wherein the first or second linearization switch comprises: a third n-type gold An oxygen semi-transistor, the source and the drain of the third n-type MOS transistor are respectively an input end and an output end of the linearization switch; φ a fourth n-type MOS semi-transistor, the source is grounded The gate of the third n-type MOS transistor is not coupled to the gate of the third n-type MOS transistor, and the voltage of the gate is controlled by an inverted signal of a clock signal; a source follower, the input end and the output end are respectively coupled Connecting the source and the gate of the third n-type MOS transistor so that the voltage difference between the gate and the source of the third n-type MOS transistor is constant; a fifth n-type gold oxide a semi-transistor, a sixth n-type MOS transistor and a third p-type MOS transistor, the drain of the fifth n-type MOS transistor 10 and the third p-type MOS The source of the crystal is coupled to the output end of the linearization switch, the source of the fifth n-type MOS transistor and the third p-type gold The oxygen semi-transistor> and the pole are connected to the drain of the six-n-type gold-milk semi-transistor, and the source of the sixth n-type gold-oxide semi-transistor is grounded, wherein the fifth n-type gold oxide The gate voltage of the semi-transistor is controlled by the inverted signal of the clock signal, and the gate voltages of the sixth n-type MOS transistor and the third p-type MOS transistor are controlled by the clock signal And a seventh n-type MOS transistor, the source of which is coupled to a voltage source, 汲0955-A21636TWF(N2); glorious_tien 28 200822531 is coupled to the output of the linearization switch, and the gate is coupled to the gate The η extreme of the sixth n-type MOS transistor. 10. The ultra-high speed, low power, low-storage substrate fully differential complementary metal-oxygen half-sampling save circuit of claim 1, wherein the first or second buffer is a source follower. 0955-A21636TWF(N2);glorious_tien