CN113328035B

CN113328035B - Semiconductor structure and forming method thereof

Info

Publication number: CN113328035B
Application number: CN202010129511.9A
Authority: CN
Inventors: 汪昌州; 刘继全
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-02-28
Filing date: 2020-02-28
Publication date: 2024-04-23
Anticipated expiration: 2040-02-28
Also published as: CN113328035A

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming an electrode layer on the substrate; forming a first seed layer on the electrode layer, the step of forming the first seed layer comprising: forming an initial seed layer on the electrode layer; performing first cooling treatment on the initial seed layer; after the first cooling treatment is carried out, carrying out second cooling treatment on the initial seed layer, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment; a magnetic tunnel junction stack structure is formed on the first seed layer. According to the embodiment of the invention, the first cooling treatment and the second cooling treatment are carried out on the initial seed layer, so that the first seed layer has higher adhesiveness and roughness at the same time, the magnetic tunnel junction laminated structure has higher magnetic resistance ratio, the patterned magnetic tunnel junction laminated structure is further carried out, and the formed magnetic tunnel junction unit has higher magnetic resistance ratio.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

The MRAM (Magnetic Random Access Memory, MRAM) is a non-volatile MRAM that can remain intact after power is turned off. MRAM devices possess high-speed read and write capabilities for Static Random Access Memory (SRAM), a solid state memory that is "full kinetic energy", and high integration for Dynamic Random Access Memory (DRAM), and can be written to substantially indefinitely. Therefore, the application prospect is very considerable, and the next generation memory market is expected to be dominant.

MRAM is a memory device that includes an array of MRAM cells, each of which uses a resistance value instead of a charge to store a bit of data. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ) cell whose resistance can be adjusted to represent a logical "0" or a logical "1". The MTJ cell includes a fixed magnetic layer, a tunneling barrier layer, and a magnetic free layer. The resistance of the MTJ cell may be adjusted by changing the direction of the magnetic moment of the magnetically free layer relative to the fixed magnetic layer. In particular, when the magnetic moment of the magnetic free layer is parallel to the magnetic moment of the fixed magnetic layer, the resistance of the MTJ cell is low, corresponding to a logic 0, whereas when the magnetic moment of the magnetic free layer is not parallel to the magnetic moment of the fixed magnetic layer, the resistance of the MTJ cell is high, corresponding to a logic 1. The MTJ cell is connected between top and bottom electrodes and a current flowing through the MTJ cell from one electrode to the other can be detected to determine the resistance and thus the logic state.

The Tunnel Magnetoresistance (TMR) effect in Magnetic Tunnel Junctions (MTJs) is key to the development of Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and new types of programmable logic devices.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor and a forming method thereof, and improves the electrical performance of a semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming an electrode layer on the substrate; forming a first seed layer on the electrode layer, the step of forming the first seed layer comprising: forming an initial seed layer on the electrode layer; performing first cooling treatment on the initial seed layer; after the first cooling treatment is carried out, carrying out second cooling treatment on the initial seed layer, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment; a magnetic tunnel junction stack structure is formed on the first seed layer.

Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; an electrode layer on the substrate; the first seed layer is positioned on the electrode layer, and is formed by sequentially carrying out first cooling treatment and second cooling treatment, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment; and a magnetic tunnel junction unit located on the first seed layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming a semiconductor structure provided by the embodiment of the invention, a first seed layer is formed on the electrode layer, and the forming step of the first seed layer includes: forming an initial seed layer on the electrode layer; performing first cooling treatment on the initial seed layer, wherein the first cooling treatment is slow cooling, so that crystals in the initial seed layer slowly shrink, and the deformation of crystal grains is small, so that the top surface of the initial seed layer has excellent adhesiveness, the formation quality of the magnetic tunnel junction laminated structure is good, the subsequent patterning of the magnetic tunnel junction laminated structure is performed, and the tunneling magnetic resistance of the formed magnetic tunnel junction unit is high; in addition, after the first cooling treatment is performed, the initial seed layer is subjected to second cooling treatment, the cooling rate of the second cooling treatment is larger than that of the first cooling treatment, so that the initial seed layer is changed from a crystalline state to an amorphous state, grains in the initial seed layer are thinned, the roughness of the top surface of the first seed layer is smaller, the roughness of the interface of the corresponding first seed layer and the magnetic tunnel junction laminated structure is smaller, the interface roughness of each film layer in the magnetic tunnel junction laminated structure is smaller, and the magnetic tunnel junction unit has higher magnetic resistance ratio. In summary, the first seed layer is beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction cell, and can enable the semiconductor structure to have excellent electrical properties.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

The semiconductor structure formed at present still has the problem of poor performance. The reason for the poor performance of the semiconductor structure is analyzed by combining a structural schematic diagram of the semiconductor structure.

Fig. 1 shows a schematic structural diagram of a semiconductor structure.

Referring to fig. 1, the semiconductor structure includes: a first electrode (not shown in the figure); a seed layer 1 on the first electrode; a fixed magnetic layer 2 is located on the seed layer 1, the fixed magnetic layer comprising: a first antiferromagnetic layer 3, a first coupling layer 4 on the first antiferromagnetic layer 3, a second antiferromagnetic layer 5 on the first coupling layer 4, a second coupling layer 6 on the second antiferromagnetic layer 5, and a pinned layer 7 on the second coupling layer 6; a tunneling barrier layer 8 on the fixed magnetic layer 2; a free magnetic layer 9 on the tunneling barrier layer 8; a cap layer 10 is located on the free magnetic layer 9.

The fixed magnetic layer 2, the tunneling barrier layer 8, and the free magnetic layer 9 form a magnetic tunnel junction, and the magnetic tunnel junction is usually annealed to increase the magnetoresistance ratio of the magnetic tunnel junction.

Typically the material of the seed layer 1 comprises Ta, which in the annealing process tends to diffuse into the tunnel barrier layer 8 through the fixed magnetic layer 2, so that the metal oxide in the tunnel barrier layer 8 is less prone to change from a polycrystalline state to a single crystalline state, resulting in a weaker Tunnel Magnetoresistance (TMR) effect for the magnetic tunnel junction.

In addition, after annealing treatment, the grain size of Ta atoms in the seed layer 1 is easy to be increased, and correspondingly, the roughness of the surface of the seed layer 1 is increased, and the roughness of the surface of the seed layer 1 is easy to be transferred into the magnetic tunnel junction, so that the interface roughness between the film layers of the magnetic tunnel junction is improved, and therefore, the perpendicular anisotropy between the film layers of the magnetic tunnel junction is poor, and the magnetic resistance of the magnetic tunnel junction is relatively small.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming an electrode layer on the substrate; forming a first seed layer on the electrode layer, the step of forming the first seed layer comprising: forming an initial seed layer on the electrode layer; performing first cooling treatment on the initial seed layer; after the first cooling treatment is carried out, carrying out second cooling treatment on the initial seed layer, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment; a magnetic tunnel junction stack structure is formed on the first seed layer.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 2, a substrate is provided.

The substrate is used to provide a process platform for forming a magnetic random access memory (Magnetic Random Access Memory, MRAM). In particular, the MRAM device is a spin-transfer Torque magnetoresistive random access memory (SPIN TRANSFER Torque-MRAM, STT-MRAM).

The substrate includes: a first inter-metal dielectric layer 100 and an interconnect line 101 located in the first inter-metal dielectric layer 100.

The first intermetal dielectric layer 100 is used to electrically isolate the interconnect line 101.

In this embodiment, the material of the first intermetal dielectric layer 100 is a low-k dielectric material, which is beneficial to reduce parasitic capacitance between the interconnection lines 101 and reduce the RC delay of the later stage.

It should be noted that, the substrate further includes a transistor, the first inter-metal dielectric layer 100 is typically formed on the transistor, the transistor includes a gate structure, source and drain doped regions located at two sides of the gate structure, and a contact plug (not shown in the figure) contacting with the source and drain doped regions is further formed in the substrate.

The interconnect line 101 is for plug connection with the contact hole.

In this embodiment, the interconnection line 101 is a first metal layer (M1), and the first metal layer refers to a metal layer closest to the contact hole plug.

In this embodiment, the material of the interconnection line 101 is copper. In other embodiments, the material of the interconnection line may be a conductive material such as tungsten, aluminum, cobalt, etc., according to a practical process.

The substrate further comprises: a dielectric layer 102 on the first intermetal dielectric layer 100 and covering the interconnect 101; a conductive plug 103 penetrating the dielectric layer 102, the conductive plug 103 being connected to the interconnection line 101.

In this embodiment, the material of the dielectric layer 102 is a low-k dielectric material, an ultra-low k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, silicon oxycarbide, or other dielectric material.

Specifically, the material of the dielectric layer 102 is a low-k dielectric material, which is beneficial to reducing parasitic capacitance between the back-end interconnect structures, and thus beneficial to reducing back-end RC delay. Specifically, the material of the dielectric layer 102 is SiCOH.

And forming a bottom electrode on the substrate, wherein the conductive plug 103 is used for realizing the electrical connection between the contact hole plug in the substrate and the bottom electrode.

The conductive plug 103 may be one or more of Cu, W, al, tiN, taN, ti. In this embodiment, the conductive plug 103 is made of Cu.

Referring to fig. 3, an electrode layer 104 is formed on the substrate.

In this embodiment, the Electrode layer 104 is a Bottom Electrode (BE), and the Electrode layer 104 is used to electrically connect the subsequent magnetic tunnel junction stack structure and the conductive plug 103.

Specifically, the material of the electrode layer 104 includes one or more of TaN, ta, ti and TiN. In this embodiment, the electrode layer 104 has a single-layer structure, and the material of the electrode layer 104 includes TaN.

In this embodiment, the electrode layer 104 is formed using an atomic layer deposition (Atomic layer deposition, ALD) process. The atomic layer deposition process is based on Self-limiting reaction process of atomic layer deposition process, and the film obtained by deposition can reach the thickness of single-layer atoms, because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be favorable for accurately controlling the thickness of the electrode layer 104, and in addition, the film prepared by ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good shape retention and the like, and is favorable for improving the thickness uniformity and film quality of the electrode layer 104. In other embodiments, the electrode layer may also be formed using a physical vapor deposition process, depending on the actual process.

Referring to fig. 4, a first seed layer 105 is formed on the electrode layer 104, and the step of forming the first seed layer 105 includes: forming an initial seed layer (not shown) on the electrode layer 104; performing first cooling treatment on the initial seed layer; and after the first cooling treatment is performed, performing a second cooling treatment on the initial seed layer, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment.

In the method for forming a semiconductor structure provided in the embodiment of the present invention, a first seed layer 105 is formed on the electrode layer 104, and the step of forming the first seed layer 105 includes: forming an initial seed layer on the electrode layer 104; performing first cooling treatment on the initial seed layer, wherein the first cooling treatment is slow cooling, so that crystals in the initial seed layer slowly shrink, and the deformation of crystal grains is small, so that the top surface of the initial seed layer has excellent adhesiveness, the formation quality of the magnetic tunnel junction laminated structure is good, the subsequent patterning of the magnetic tunnel junction laminated structure is performed, and the tunneling magnetic resistance of the formed magnetic tunnel junction unit is high; in addition, after the first cooling treatment is performed, the initial seed layer is further subjected to a second cooling treatment, and the cooling rate of the second cooling treatment is greater than that of the first cooling treatment, so that the initial seed layer is converted from a crystalline state to an amorphous state, grains in the initial seed layer are thinned, the roughness of the top surface of the first seed layer 105 is smaller, the roughness of the interface of the corresponding first seed layer 105 and the magnetic tunnel junction laminated structure is smaller, the interface roughness of each film layer in the magnetic tunnel junction laminated structure is smaller, and the corresponding magnetic tunnel junction unit has a higher magnetic resistance ratio. In summary, the first seed layer is beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction cell, and can enable the semiconductor structure to have excellent electrical properties.

The top surface of the first seed layer 105 has higher flatness and smoothness, so that a good interface state can be provided for the subsequent formation of the magnetic tunnel junction laminated structure, and the formation quality of the magnetic tunnel junction laminated structure is better.

In this embodiment, the material of the first seed layer 105 includes Ta. Ta has better ductility and can provide a good interface state for the subsequent formation of the second seed layer and the magnetic tunnel stack structure.

In the step of forming the first seed layer 105, the first seed layer 105 is preferably not too thick or too thin. If the first seed layer 105 is too thick, it is easy to take too much process time to form the first seed layer 105, and the electrical property of the subsequently formed magnetic tunnel junction stack structure is also caused to deviate, which is not beneficial to improving the magnetic resistance ratio of the magnetic tunnel junction stack structure, and correspondingly, is not beneficial to improving the magnetic resistance ratio of the magnetic tunnel junction unit. If the first seed layer 105 is too thin, it is not easy to provide a good interface state for the subsequent formation of the second seed layer, and accordingly the formation quality of the magnetic tunnel junction stack structure is poor, resulting in a relatively small magnetic resistance of the magnetic tunnel junction unit. In this embodiment, in the step of forming the first seed layer 105, the thickness of the first seed layer 105 isTo

In this embodiment, the initial seed layer is formed using a physical vapor deposition process (Physical Vapor Deposition, PVD). The physical vapor deposition process has the advantages of simple process, little pollution, low process cost, compact film formation, strong bonding force with other film structures, and the like. In other embodiments, the initial seed layer may also be formed using an atomic layer deposition process (Atomic Layer Deposition, ALD) or a chemical vapor deposition process (chemical vapor deposition, CVD).

The physical vapor deposition process comprises the following steps: DC magnetron sputtering process and RF magnetron sputtering process

Specifically, the initial seed layer is formed by a direct current magnetron sputtering process (DC sputtering). In other embodiments, the initial seed layer may also be formed using a radio frequency magnetron sputtering process (RF sputtering).

The step of forming the initial seed layer by adopting a direct current magnetron sputtering process comprises the following steps: the target is arranged at the positive electrode of the direct current voltage in the chamber, the direct current voltage is applied in the chamber, the reaction gas is introduced into the chamber, the reaction gas is ionized in the chamber to form plasma, the plasma bombards the target under the action of the direct current voltage, and atoms bombarded in the target are deposited on the electrode layer 104 to form the initial seed layer.

In this embodiment, a Ta target is disposed in the positive electrode of the chamber.

In this embodiment, in the process of forming the initial seed layer by using a dc magnetron sputtering process, the sputtered ions include Ar. In other embodiments, the sputter ions may also include He.

In the process of forming the initial seed layer by using the direct current magnetron sputtering process, the process temperature is not too high or too low. If the process temperature is too high, the lattice size of the formed initial seed layer is too large, and the surface roughness of the formed initial seed layer is large. If the process temperature is too low, the diffusion rate between Ta atoms is too slow in the sputtering process, resulting in poor uniformity of each region of the initial seed layer formed, and thus, poor uniformity of each region of the subsequently formed magnetic tunnel junction stack structure. In this example, the process temperature is 20℃to 350 ℃.

The step of forming the first seed layer 105 includes: and performing first cooling treatment on the initial seed layer.

In the first cooling treatment process, the cooling liquid comprises water, and the water is adopted as the cooling liquid, so that the cost is saved. In other embodiments, liquid nitrogen or liquid helium may also be used as the cooling liquid.

It should be noted that, in the first cooling process, the pressure of the chamber should not be too large or too small. If the chamber pressure is too high, the roughness of the top surface of the initial seed layer is increased, and the roughness of the interface between the corresponding subsequently formed first seed layer 105 and the magnetic tunnel junction stacked structure is relatively high, and the roughness of the interface between each film layer in the magnetic tunnel junction stacked structure is relatively high, so that the magnetic tunnel junction unit formed by the subsequently patterned magnetic tunnel junction stacked structure has relatively low magnetoresistance ratio. If the pressure of the chamber is too small, the temperature reduction rate of the initial seed layer is too slow in the process of the first temperature reduction treatment, which results in a long process time of the first temperature reduction treatment, which is not beneficial to improving the formation efficiency of the first seed layer 105. In this embodiment, the chamber pressure is 100mTorr to 800mTorr during the first cooling process.

It should be noted that, in the process of the first cooling treatment, the cooling rate should not be too high. If the cooling rate is too high, the crystal of the initial seed layer is too fast in shrinkage, and the crystal grains are easy to become large, so that the roughness of the surface of the initial seed layer after the first cooling treatment is relatively high, the roughness of the interface between the corresponding subsequently formed first seed layer 105 and the magnetic tunnel junction laminated structure is relatively high, and the interface roughness of each film layer in the magnetic tunnel junction laminated structure is relatively high, so that the magnetic tunnel junction unit has relatively low magnetic resistance ratio. In this embodiment, in the process of the first cooling treatment, the cooling rate is less than 10 kelvin per second.

After the first cooling treatment, the temperature of the initial seed layer is not too high or too low. If the temperature of the initial seed layer is too high after the first cooling treatment, the grain size of the initial seed layer after the first cooling treatment is easily larger, the roughness of the interface between the corresponding subsequently formed first seed layer 105 and the magnetic tunnel junction laminated structure is larger, and the roughness of the interface between each film layer in the magnetic tunnel junction laminated structure is larger, so that the magnetic tunnel junction unit has a lower magnetic resistance ratio. If the temperature of the initial seed layer is too low after the first cooling treatment, the grains of the initial seed layer are easy to shrink, the volume of the initial seed layer is reduced, the contact characteristic of the initial seed layer after the first cooling treatment is poor, and correspondingly, the contact characteristic between the subsequently formed first seed layer and the film layer structure formed on the first seed layer is poor, that is, the adhesiveness is poor, so that dislocation or shedding easily occurs in the subsequently formed film layer structure on the first seed layer 105, and therefore, the formation quality of the magnetic tunnel junction laminated structure is poor, and the magnetic tunnel junction unit has a lower magnetic resistance ratio. After the first cooling treatment, the temperature of the initial seed layer is reduced to 273-373 Kelvin.

The forming of the first seed layer 105 further includes: and after the initial seed layer is subjected to the first cooling treatment, the initial seed layer is subjected to the second cooling treatment.

In the second cooling treatment process, the cooling liquid comprises water, and the water is used as the cooling liquid, so that the cost is saved. In other embodiments, liquid nitrogen or liquid helium may also be used as the cooling liquid.

It should be noted that, in the second cooling process, the pressure of the chamber should not be too large or too small. If the chamber pressure is too high, the roughness of the top surface of the initial seed layer is increased, and the roughness of the interface between the corresponding subsequently formed first seed layer 105 and the magnetic tunnel junction stack structure is relatively high, and the interface roughness of each film layer in the magnetic tunnel junction stack structure is relatively high, so that the magnetic tunnel junction unit has a relatively low magnetoresistance ratio. If the pressure of the chamber is too small, the cooling rate of the initial seed layer is too slow in the process of the second cooling treatment, so that the process time of the second cooling treatment is long, and the formation efficiency of the first seed layer is not improved. In this embodiment, the chamber pressure is 100mTorr to 800mTorr during the second cooling process.

In the second cooling process, the cooling rate is not too low. If the cooling rate is too small, grains in the initial seed layer are easy to grow randomly, and accordingly, the lattice of the formed first seed layer 105 is too large, so that the roughness of the surface of the first seed layer 105 is too large. In this embodiment, in the second cooling process, the cooling rate is greater than 20 kelvin per second.

After the second cooling treatment, the temperature of the initial seed layer is not too high or too low. If the temperature of the initial seed layer is too high, lattice growth is easy to be caused, so that the roughness of the surface of the first seed layer 105 becomes larger, and the interface roughness of each film layer in the subsequently formed magnetic tunnel junction laminated structure is larger, so that the magnetic tunnel junction unit has a lower magnetic resistance ratio. If the temperature of the initial seed layer is too low, the adhesiveness of the formed first seed layer 105 is low, and the subsequent film layer structure formed on the first seed layer 105 is easy to be dislocated or fall off, so that the formation quality of the magnetic tunnel junction laminated structure is poor, and the magnetic tunnel junction unit has a low magnetic resistance ratio. After the second cooling treatment, the temperature of the initial seed layer is reduced to 90-150 Kelvin.

The roughness of the first seed layer 105 should not be too high. If the roughness of the first seed layer 105 is too large, the roughness of the top surface of the second seed layer subsequently formed on the first seed layer 105 is too large, and the roughness of the interface between the corresponding second seed layer and the subsequently formed magnetic tunnel junction laminated structure is relatively large, and the roughness of the interface between each film layer in the magnetic tunnel junction laminated structure is relatively large, so that the magnetic tunnel junction unit has relatively low magnetic resistance ratio. In this embodiment, the roughness of the first seed layer 105 is smaller than

Referring to fig. 5, after forming the first seed layer 105, a second seed layer 107 is formed on the first seed layer 105 before forming a magnetic tunnel junction stack structure.

The second seed layer 107 is used for blocking Ta in the first seed layer 105 from diffusing into a tunneling barrier layer of a subsequently formed magnetic tunnel junction stack structure, and in a subsequent annealing process, the content of single-crystalline metal oxide in the tunneling barrier layer is improved, so that the magnetic tunnel junction unit has a higher magnetoresistance ratio.

In this embodiment, the material of the second seed layer 107 includes Mo. Mo is stable in properties at high temperatures and is not easily diffused into the tunnel barrier during subsequent anneals. In addition, mo has smaller resistance, which is beneficial to reducing the power consumption of the semiconductor structure.

In the step of forming the second seed layer 107, the second seed layer 107 is preferably not too thick or too thin. If the second seed layer 107 is too thick, it is easy to take too much process time to form the second seed layer 107, and the electrical property of the subsequently formed magnetic tunnel junction stack structure may be further shifted, which is not beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction stack structure, and is correspondingly not beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction unit. If the second seed layer 107 is too thin, ta in the first seed layer 105 is likely to diffuse through the second seed layer 107 into the subsequently formed tunnel barrier layer 108, resulting in a relatively small magnetoresistance of the magnetic tunnel junction cell. In this embodiment, in the step of forming the second seed layer 107, the thickness of the second seed layer 107 isTo

In this embodiment, the second seed layer 107 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of simple process, little pollution, low process cost, compact film formation, strong bonding force with other film structures, and the like.

Specifically, the second seed layer 107 is formed by using a direct current magnetron sputtering process (DC sputtering). In other embodiments, the second seed layer may also be formed using a radio frequency magnetron sputtering process (RF sputtering).

The step of forming the second seed layer 107 by using a dc-stacked plasma process includes: a target is arranged at the positive electrode of the direct current voltage in the chamber, the direct current voltage is applied in the chamber, the reaction gas is introduced into the chamber, the reaction gas is ionized in the chamber to form plasma, the plasma bombards the target under the action of the direct current voltage, and atoms bombarded in the target are deposited on the first seed layer 105 to form the second seed layer 107.

In this embodiment, a Mo target is disposed in the positive electrode of the chamber.

In this embodiment, in the process of forming the second seed layer 107 by using a dc magnetron sputtering process, the sputtered ions include Ar. In other embodiments, the sputter ions may also include He.

In the process of forming the second seed layer 107 by using the dc magnetron sputtering process, the process temperature should not be too high or too low. If the process temperature is too high, ta atoms in the first seed layer 105 are likely to diffuse into the second seed layer 107, resulting in a poor film quality of the formed second seed layer 107, so that the second seed layer 107 cannot well block Ta diffusion in the first seed layer 105 in the subsequent process. If the process temperature is too low, the diffusion rate between Mo atoms is too slow during the sputtering process, resulting in poor uniformity of each region of the formed second seed layer 107, which is likely to result in poor uniformity of each region of the subsequently formed magnetic tunnel junction stack structure. In this example, the process temperature is 20℃to 30 ℃.

It should be noted that, in the process of forming the second seed layer 107 by using the dc magnetron sputtering process, the chamber pressure should not be too high or too low. If the chamber pressure is too low, the deposition rate of Mo atoms generated by the bombardment of the Mo target material by the sputtered ions is too slow, so that the crystal orientation of the second seed layer 107 is not easy to be consistent, and the density of the formed second seed layer 107 is poor. If the chamber pressure is too high, mo atoms bombarded in the Mo-containing target collide violently during deposition, which may easily result in excessive roughness of the top surface of the formed second seed layer 107. In this embodiment, the chamber pressure is 100mTorr to 800mTorr.

In other embodiments, the second seed layer may also be formed using an atomic layer deposition process (Atomic Layer Deposition, ALD) or a chemical vapor deposition process (chemical vapor deposition, CVD).

Referring to fig. 6 to 10, a magnetic tunnel junction stack structure is formed on the first seed layer 105.

The magnetic tunnel junction stack structure provides for the subsequent formation of a magnetic tunnel junction cell that is used as the basic memory cell.

Specifically, the forming step of the magnetic tunnel junction laminated structure includes:

As shown in fig. 6 to 8, a fixed magnetic layer 106 (PINNING LAYER) is formed on the first seed layer 105 (as shown in fig. 8).

The fixed magnetic layer 106 has a fixed magnetic direction.

In this embodiment, the fixed magnetic layer 106 includes: an antiferromagnetic layer 1061 (antiferro-magnetic, AFM), a coupling layer 1062 on the antiferromagnetic layer 1061, and a pinned layer 1063 on the coupling layer 1062.

Specifically, the fixed magnetic layer 106 is formed on the second seed layer 107.

As shown in fig. 6, an antiferromagnetic layer (SYNTHETIC ANTIFERROMAGNET, SAF) 1061 is formed on the first seed layer 105.

In operation of the semiconductor structure, the antiferromagnetic layer 1061 is used to fix the magnetization direction of the pinned layer to be formed later, and to prevent the magnetization direction from being changed due to the influence of the direction of the induced magnetic field generated when the current in the bit line or word line flows because the coercive force of the pinned layer is not large enough.

Specifically, the antiferromagnetic layer 1061 includes a stacked structure of alternating deposited Co layers and Pt layers. The greater the number of Co and Pt layers in the antiferromagnetic layer 1061, the greater the perpendicular anisotropy of the corresponding antiferromagnetic layer 1061.

In this embodiment, the antiferromagnetic layer 1061 is formed by a physical vapor deposition process. In other embodiments, the antiferromagnetic layer may also be formed using a chemical vapor deposition process or an atomic layer deposition process.

As shown in fig. 7, a coupling layer 1062 is formed on the antiferromagnetic layer 1061.

In operation of the semiconductor structure, the coupling layer 1062 magnetically couples the antiferromagnetic layer 1061 to the subsequently pinned layer 1063, which facilitates improved perpendicular anisotropy of the pinned magnetic layer and better pinning of the subsequently formed pinned layer.

Specifically, the material of coupling layer 1062 includes a non-tantalum metal. The material of the coupling layer 1062 includes a non-tantalum metal, meaning that the coupling layer 1062 does not contain a Ta element, thereby reducing the probability of atoms in the coupling layer 1062 diffusing into a subsequently formed tunnel barrier layer, which material is more easily transformed into an amorphous state during a subsequent anneal. In this embodiment, the coupling layer 1062 includes Ru. In other embodiments, the coupling layer may also comprise other suitable materials, such as Ti, cu, or Ag.

In this embodiment, the coupling layer 1062 is formed by a physical vapor deposition process. In other embodiments, the coupling layer may also be formed using a chemical vapor deposition or atomic layer deposition process.

As shown in fig. 8, a pinned layer 1063 is formed on the coupling layer 1062.

The pinned layer 1063 has a strong coercive force and is less susceptible to changing the magnetization direction by the direction of an induced magnetic field generated when a current in a bit line or a word line flows.

The pinned layer 1063 includes a material containing Fe. Specifically, the materials of the pinned layer 1063 include: feCoB, coFeTa, niFe and FePt. In this embodiment, the material of the pinned layer 1063 includes FeCoB.

In this embodiment, the pinned layer 1063 is formed using a physical vapor deposition process. In other embodiments, the pinned layer may also be formed using a chemical vapor deposition or atomic layer deposition process.

As shown in fig. 9, the forming step of the magnetic tunnel junction stack structure further includes: a tunnel barrier layer 108 is formed on the fixed magnetic layer 106.

The tunnel barrier layer 108 serves to fix the electrical isolation between the magnetic layer 106 and a subsequently formed magnetic free layer while allowing electrons to tunnel through the tunnel barrier layer 108 under appropriate conditions.

Specifically, the material of the tunnel barrier layer 108 includes MgO, alO, alN or AlON. In this embodiment, the material of the tunnel barrier layer 108 includes MgO.

In this embodiment, the tunnel barrier layer 108 is formed using an electron beam evaporation process (Electron Beam Evaporation, EBE). In other embodiments, the tunneling barrier layer may also be formed using an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

As shown in fig. 10, the forming step of the magnetic tunnel junction stack structure further includes: a magnetic free layer 109 is formed on the tunnel barrier layer 108.

The magnetic free layer 109, tunneling barrier layer 108, and fixed magnetic layer 106 form a magnetic tunnel junction stack that provides for the subsequent formation of a magnetic tunnel junction cell.

The magnetic free layer 109 has a free magnetic orientation, and a Spin Transfer Torque (STT) effect is typically used to change or switch the magnetic polarity of the magnetic free layer 109, parallel or opposite to the magnetization direction of the fixed magnetic layer 106, when the magnetic tunnel junction cell is in operation, thereby enabling the magnetic tunnel junction cell to be in a low resistance state or a high configuration.

In this embodiment, the material of the magnetic free layer 109 includes FeCo, coNi, coFeB, feB, fePt, fePd and alloys of Fe, co, and Ni.

In this embodiment, the magnetic free layer 109 is formed by a physical vapor deposition process. In other embodiments, the magnetic free layer may also be formed using chemical vapor deposition or atomic layer deposition processes.

The method for forming the semiconductor structure further comprises the following steps: and after the magnetic tunnel junction laminated structure is formed, annealing the magnetic tunnel junction laminated structure.

The annealing treatment can make MgO in the tunnel barrier layer 108 change from a polycrystalline state to a single crystalline state, so that a Tunnel Magnetoresistance (TMR) effect of the magnetic tunnel junction laminated structure is stronger, and the magnetoresistance of a corresponding magnetic tunnel junction unit is larger; and the annealing treatment can magnetize the magnetic particles in the fixed magnetic layer 106 and the magnetic free layer 109, so that the spin directions of the magnetic particles in the fixed magnetic layer 106 and the magnetic free layer 109 are ordered, and the Tunnel Magnetoresistance (TMR) effect of the subsequently formed magnetic tunnel junction unit is stronger.

After annealing treatment, a non-magnetic insulating layer and a cap layer are formed on the magnetic tunnel junction laminated structure, and before the non-magnetic insulating layer and the cap layer are formed, the magnetic tunnel junction laminated structure is annealed, so that ions in the non-magnetic insulating layer and the cap layer are not easy to diffuse into the tunnel barrier layer 108, and the magnetic resistance ratio of the magnetic tunnel junction laminated structure is improved.

It should be noted that, in the annealing process, the grains of Ta atoms in the first seed layer 105 are not significantly increased, and the roughness of the top surface of the first seed layer 105 is not significantly increased, so that the magnetic tunnel junction stack structure is less affected by the surface roughness of the top surface of the first seed layer 105, and the surface roughness of the interface between the film layers of the magnetic tunnel junction stack structure is not easily increased, so that the vertical anisotropy still has relatively large between the film layers of the magnetic tunnel junction stack structure, which is favorable for the magnetic tunnel junction stack structure to have relatively large magnetoresistance ratio, and the corresponding subsequently formed magnetic tunnel junction unit has relatively large magnetoresistance ratio.

In this embodiment, the annealing is performed by means of strong magnetic field annealing.

Referring to fig. 11, a non-magnetic insulating layer 110 is formed on the magnetic free layer 109.

The nonmagnetic insulating layer 110 causes a magnetic field and an electric field to be contained between the magnetic free layer 109 and the fixed magnetic layer 106. The nonmagnetic insulating layer 110 helps reduce the switching current density of the magnetic tunnel junction cell switching from one orientation (e.g., parallel orientation) to another orientation (e.g., antiparallel orientation) when the semiconductor structure is in operation.

Specifically, the material of the nonmagnetic insulating layer 110 includes MgO, alO, alN or AlON. In this embodiment, the material of the nonmagnetic insulating layer 110 includes MgO.

In this embodiment, the nonmagnetic insulating layer 110 is formed by a physical vapor deposition process. In other embodiments, the non-magnetic insulating layer may also be formed using a chemical vapor deposition or atomic layer deposition process.

With continued reference to fig. 11, a cap layer 111 is formed on the nonmagnetic insulating layer 110.

The cap layer 111 can protect the magnetic tunnel junction stack structure from damage during subsequent etching.

In this embodiment, the cap layer 111 has a stacked structure. The capping layer 111 has a laminated structure, so that the magnetic tunnel junction laminated structure can be better protected. Specifically, the capping layer 111 is a stacked structure formed by a Ru layer and a Ta layer. In other embodiments, the capping layer 111 may also have a single layer structure, including only a Ta layer or only a Ru layer.

Referring to fig. 12, a top electrode 112 is formed on the cap layer 111.

The Top Electrode 112 is a Top Electrode (TE), and the Top Electrode 112 is used to electrically connect a subsequently formed magnetic tunnel junction cell with a metal layer formed on the magnetic tunnel junction cell.

In this embodiment, the material of the top electrode 112 is one or more of TaN, ta, ti and TiN. In this embodiment, the top electrode 112 has a single-layer structure, and the material of the top electrode 112 is Ta.

Referring to fig. 13, the method for forming the semiconductor structure further includes: after the cap layer 111 is formed, the magnetic tunnel junction stack structure is patterned to form a plurality of magnetic tunnel junction cells 200.

Specifically, during the formation of the magnetic tunnel junction cell 200: the electrode layer 104, the first seed layer 105, the nonmagnetic insulating layer 110, the cap layer 111, and the top electrode 112 are also patterned.

In this embodiment, dry etching is used for patterning. The dry etching process has anisotropic etching characteristics and good etching profile control, is favorable for enabling the morphology of the magnetic tunnel junction unit 200 to meet the process requirements, and can take the dielectric layer 102 as an etching stop position in the dry etching process, so that the conductive plug 103 in the dielectric layer 102 is not easy to damage; in addition, by changing the etching gas, the magnetic tunnel junction stack structure, the electrode layer 104, the first seed layer 105, the nonmagnetic insulating layer 110, the cap layer 111, and the top electrode 112 can be etched in the same etching apparatus, simplifying the process steps.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate; an electrode layer 104 on the substrate; the first seed layer 105 is located on the electrode layer 104, the first seed layer 105 is formed by sequentially performing a first cooling treatment and a second cooling treatment, and the cooling rate of the second cooling treatment is greater than that of the first cooling treatment; a magnetic tunnel junction cell 200 is located on the first seed layer 105.

In the semiconductor structure provided by the embodiment of the invention, the first seed layer 105 is subjected to the first cooling treatment, and the first cooling treatment is slow cooling, so that the crystal in the initial seed layer is slowly contracted, and the deformation of the crystal grains is small, so that the top surface of the initial seed layer has excellent adhesiveness, the formation quality of the magnetic tunnel junction unit 200 positioned on the first seed layer 105 is better, and the magnetic tunnel junction unit has higher tunneling magnetoresistance ratio; and performing a second cooling treatment on the initial seed layer, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment, so that the initial seed layer is converted from a crystalline state to an amorphous state, grains in the initial seed layer are thinned, the roughness of the top surface of the first seed layer 105 is smaller, and the roughness of the interface between the corresponding first seed layer 105 and the magnetic tunnel junction unit 200 is smaller, so that the interface roughness of each film layer in the magnetic tunnel junction unit 200 is smaller, and the magnetic tunnel junction unit 200 has a higher magnetic resistance ratio. In summary, the first seed layer 105 is advantageous for increasing the magnetoresistance ratio of the magnetic tunnel junction cell 200, enabling the semiconductor structure to have excellent electrical properties.

The substrate is used to provide a process platform for forming a magnetic random access memory. In particular, the MRAM device is a spin-transfer torque magnetoresistive random access memory.

The interconnect line 101 is for plug connection with the contact hole.

The conductive plugs 103 are used to electrically connect the contact hole plugs in the substrate with the electrode layer 104.

The Electrode layer 104 is a Bottom Electrode (BE), and the Electrode layer 104 is used to electrically connect the magnetic tunnel junction cell 200 with the conductive plug 103.

The first seed layer 105 is formed by a first cooling treatment and a second cooling treatment, and the top surface of the first seed layer 105 has a lower roughness, that is, the first seed layer 105 has a higher flatness and smoothness, and the first seed layer 105 has a higher adhesiveness, so that the magnetic tunnel junction unit 200 on the first seed layer 105 has a better formation quality.

In this embodiment, the material of the first seed layer 105 includes Ta. Ta has a good ductility.

The first seed layer 105 is preferably not too thick or too thin. If the first seed layer 105 is too thick, it takes too much process time to form the first seed layer 105, and the electrical property of the magnetic tunnel junction cell 200 may be shifted, which is not beneficial to improving the magnetic resistance ratio of the magnetic tunnel junction cell 200. The magnetic tunnel junction cell 200 is formed by patterning the magnetic tunnel junction stack structure, and if the first seed layer 105 is too thin, it is not easy to provide a good interface state for forming the magnetic tunnel junction stack structure, and accordingly the formation quality of the magnetic tunnel junction cell 200 is poor, resulting in a relatively small magnetoresistance of the magnetic tunnel junction cell 200. In this embodiment, the thickness of the first seed layer 105 isTo

The semiconductor structure further includes: a second seed layer 107 is located between the first seed layer 105 and the magnetic tunnel junction cell 200.

The second seed layer 107 is used to block Ta in the first seed layer 105 from diffusing into the tunneling barrier layer 108 of the magnetic tunnel junction cell 200, which is advantageous to make the content of the metal oxide in the single crystalline state in the tunneling barrier layer 108 higher, so that the magnetic tunnel junction cell 200 has a higher magnetoresistance ratio.

In this embodiment, the material of the second seed layer 107 includes Mo. In the process of forming the magnetic tunnel junction cell 200, the magnetic tunnel junction stack structure is typically annealed, and Mo is stable at high temperature and is not easily diffused into the tunnel barrier layer 108. In addition, mo has smaller resistance, which is beneficial to reducing the power consumption of the semiconductor structure.

The second seed layer 107 is not too thick or too thin. If the second seed layer 107 is too thick, it may take too much process time to form the second seed layer 107, and the electrical property of the magnetic tunnel junction cell 200 may be further shifted, which is not beneficial to improving the magnetic resistance ratio of the magnetic tunnel junction cell 200. If the second seed layer 107 is too thin, ta in the first seed layer 105 is likely to diffuse through the second seed layer 107 into the tunnel barrier layer 108, resulting in a relatively small magnetic resistance of the magnetic tunnel junction cell 200. In this embodiment, the thickness of the second seed layer 107 isTo

The magnetic tunnel junction stack structure is used as a basic memory cell.

The magnetic tunnel junction cell 200 includes: a fixed magnetic layer 106, a tunneling barrier layer 108 on the fixed magnetic layer 106, and a magnetic free layer 109 on the tunneling barrier layer 108.

The fixed magnetic layer 106 has a fixed magnetic direction.

Wherein the fixed magnetic layer 106 includes an antiferromagnetic layer 1061, a coupling layer 1062 on the antiferromagnetic layer 1061, and a pinned layer 1063 on the coupling layer 1062.

In operation of the semiconductor structure, the antiferromagnetic layer 1061 is used to fix the magnetization direction of the pinned layer 1063, thereby avoiding a change in magnetization direction due to insufficient coercivity of the pinned layer 1063, which is affected by the direction of the induced magnetic field generated when a current in a bit line or word line flows.

In operation of the semiconductor structure, the coupling layer 1062 magnetically couples the antiferromagnetic layer 1061 and the pinned layer 1063 together, which facilitates improving the perpendicular anisotropy of the pinned magnetic layer 106 and better pinning the electron spin direction of the pinned layer 1063.

Specifically, the material of coupling layer 1062 includes a non-tantalum metal. The material of the coupling layer 1062 includes a non-tantalum metal, meaning that the coupling layer 1062 does not contain a Ta element, thereby reducing the probability of atoms in the coupling layer 1062 diffusing into the tunnel barrier layer 108, where the amorphous metal oxide content is higher. In this embodiment, the coupling layer 1062 includes Ru. In other embodiments, the coupling layer may also comprise other suitable materials, such as Ti, cu, or Ag.

The tunnel barrier layer 108 serves to electrically isolate the fixed magnetic layer 106 from the magnetic free layer 109 while allowing electrons to tunnel through the tunnel barrier layer 108 under appropriate conditions.

The magnetic free layer 109 has a free magnetic orientation, and a Spin Transfer Torque (STT) effect is typically used to change or switch the magnetic polarity of the magnetic free layer 109 parallel or opposite to the magnetization direction of the fixed magnetic layer 106 when the magnetic tunnel junction cell 200 is in operation, thereby enabling the magnetic tunnel junction cell 200 to be in a low resistance state or a high configuration.

The nonmagnetic insulating layer 110 causes a magnetic field and an electric field to be contained between the magnetic free layer 109 and the fixed magnetic layer 106. The nonmagnetic insulating layer 110 helps reduce the switching current density of the magnetic tunnel junction cell 200 when it is in operation from one orientation (e.g., parallel orientation) to another orientation (e.g., antiparallel orientation).

The semiconductor structure further includes: and a cap layer 111 on the nonmagnetic insulating layer 110. The cap layer 111 can protect the magnetic tunnel junction cell 200 from damage.

In this embodiment, the cap layer 111 has a stacked structure. The capping layer 111 has a laminated structure, so that the magnetic tunnel junction laminated structure can be better protected. Specifically, the capping layer 111 is a stacked structure formed by a Ru layer and Ta layer. In other embodiments, the capping layer 111 may also have a single layer structure, including only a Ta layer or only a Ru layer.

The semiconductor structure further includes: a top electrode 112 is located on the cap layer 111.

The Top Electrode 112 is a Top Electrode (TE), and the Top Electrode 112 is used to electrically connect the magnetic tunnel junction cell 200 with a metal layer formed on the magnetic tunnel junction cell 200.

The semiconductor structure of this embodiment may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

Providing a substrate;

Forming an electrode layer on the substrate;

Forming a first seed layer on the electrode layer, the step of forming the first seed layer comprising: forming an initial seed layer on the electrode layer; performing first cooling treatment on the initial seed layer; after the first cooling treatment is carried out, carrying out second cooling treatment on the initial seed layer, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment;

In the process of the first cooling treatment, the cooling rate is less than 10 Kelvin per second, and the technological parameters of the first cooling treatment comprise: the chamber pressure is 100mTorr to 800mTorr; in the first cooling treatment process, the cooling liquid comprises water; after the first cooling treatment, the temperature of the initial seed layer is reduced to 273-373 Kelvin; in the second cooling treatment process, the cooling rate is greater than 20 Kelvin per second, and the second cooling treatment process parameters comprise: the chamber pressure is 100mTorr to 800mTorr; in the second cooling treatment process, the cooling liquid comprises water; after the second cooling treatment, the temperature of the initial seed layer is reduced to 90-150 Kelvin;

A magnetic tunnel junction stack structure is formed on the first seed layer.

2. The method of forming a semiconductor structure of claim 1, wherein a second seed layer is formed on the first seed layer after the first seed layer is formed and prior to forming a magnetic tunnel junction stack structure.

3. The method of claim 1, wherein the initial seed layer is formed using a plasma enhanced atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

4. The method of forming a semiconductor structure of claim 1, wherein a material of the first seed layer comprises Ta.

5. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the first seed layer, a thickness of the first seed layer isTo

6. The method of claim 1, wherein forming the initial seed layer using a rf magnetron sputtering process or a dc magnetron sputtering process comprises: the sputtered ions comprise Ar, the target comprises Ta, the process temperature is 20 ℃ to 350 ℃, and the chamber pressure is 100mTorr to 800mTorr.

7. The method of claim 2, wherein the second seed layer is formed using a plasma enhanced atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

8. The method of forming a semiconductor structure of claim 2, wherein a material of the second seed layer comprises Mo.

9. The method of forming a semiconductor structure according to claim 2, wherein in the step of forming the second seed layer, a thickness of the second seed layer isTo

10. The method of claim 2, wherein forming the second seed layer using a rf magnetron sputtering process or a dc magnetron sputtering process comprises: the sputtering ions comprise Ar, the target comprises Mo target, the process temperature is 20 ℃ to 30 ℃, and the chamber pressure is 100mTorr to 800mTorr.

11. The method of forming a semiconductor structure of claim 3 or 7, wherein the physical vapor deposition process comprises a radio frequency magnetron sputtering process or a direct current magnetron sputtering process.

12. A semiconductor structure formed by the method of forming a semiconductor structure as claimed in any one of claims 1 to 11, comprising:

A substrate;

An electrode layer on the substrate;

The first seed layer is positioned on the electrode layer, and is formed by sequentially carrying out first cooling treatment and second cooling treatment, wherein the cooling rate of the second cooling treatment is greater than that of the first cooling treatment;

And a magnetic tunnel junction unit located on the first seed layer.

13. The semiconductor structure of claim 12, wherein the semiconductor structure further comprises: and a second seed layer on the first seed layer.

14. The semiconductor structure of claim 12 or 13, wherein the material of the first seed layer comprises Ta.

15. The semiconductor structure of claim 13, wherein a material of the second seed layer comprises Mo.

16. The semiconductor structure of claim 12 or 13, wherein the first seed layer has a roughness less than