CN113327988A - Triode display with VDMOS device structure - Google Patents

Triode display with VDMOS device structure Download PDF

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Publication number
CN113327988A
CN113327988A CN202110594705.0A CN202110594705A CN113327988A CN 113327988 A CN113327988 A CN 113327988A CN 202110594705 A CN202110594705 A CN 202110594705A CN 113327988 A CN113327988 A CN 113327988A
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layer
thin film
sub
driving
pixel
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杜晓松
郭华飞
沈秋华
宋东
杨晋苏
张婷
杨长春
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Changzhou University
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Changzhou University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses a triode display with a VDMOS device structure, which comprises a plurality of pixels, wherein each pixel comprises three sub-pixel units; the driving back plate bears a plurality of pixels; the sub-pixel unit comprises a VDMOS device, wherein the VDMOS device is arranged on the driving backboard and covers at least one through hole. The invention reduces the response time, improves the display brightness, and has the display functions of high resolution, high brightness, high contrast and low response time.

Description

Triode display with VDMOS device structure
Technical Field
The invention relates to a triode display based on a VDMOS device structure, belonging to the field of display manufacturing.
Background
With the continuous development of display technology, the application range of display panels is wider and wider, and the requirements of people on the display panels are higher and higher. For example, the display panel is applied to products such as mobile phones, computers, tablet computers, electronic books, information query machines, wearable devices and the like. As the application range of display panels is expanded, higher and higher requirements are put on display technologies and display devices. The traditional LED/OLED display has certain limitations and cannot meet more requirements of people on visual experience at present.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a triode display with a VDMOS device structure, which realizes the display functions of high resolution, high brightness, high contrast and low response time.
The invention mainly adopts the technical scheme that:
a triode display of VDMOS device structure comprising:
the pixel comprises a plurality of pixels, wherein each pixel comprises three sub-pixel units, including a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the driving back plate is provided with a plurality of regularly arranged through holes, and the sub-pixel unit covers at least one through hole; the driving back plate bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode, a VDMOS device, an ITO/TiN thin film layer and an LED light-emitting unit, wherein the anode is arranged on the driving backboard and covers at least one via hole, the VDMOS device is arranged on one side, away from the driving backboard, of the anode, the ITO/TiN thin film layer comprises an ITO thin film layer and a TiN thin film layer which are stacked up and down, the TiN thin film layer is arranged on one side, away from the driving backboard, of the VDMOS device, the ITO thin film layer is arranged on one side, away from the driving backboard, of the TiN thin film layer, and the LED light-emitting unit is arranged on one side, away from the driving backboard, of the ITO thin film layer.
Preferably, the VDMOS device includes an NPN-type semiconductor layer, an SiN sidewall protection layer, a gate insulating layer, and a gate, the NPN-type semiconductor layer is located on a side of the anode away from the driving backplate, the ITO/TiN thin film layer is disposed on a side of the NPN-type semiconductor layer away from the driving backplate, the SiN sidewall protection layer is disposed around an upper surface of the ITO/TiN thin film layer to form an SiN trench, the gate insulating layer is coated on outer sidewalls of the SiN sidewall protection layer, the ITO/TiN thin film layer, and the NPN-type semiconductor layer, the gate is disposed on a sidewall of the gate insulating layer, a vertical cross section of the gate insulating layer is an L-shaped structure, and a bottom surface of the gate is in contact with the gate insulating layer.
Preferably, the LED light-emitting unit includes an RGB OLED light-emitting layer and a drain, the RGB OLED light-emitting layer is located on one side of the ITO/TiN thin film layer in the SiN groove away from the driving backplane, and a red OLED light-emitting material is in the RGB OLED light-emitting layer of the red sub-pixel unit; a green OLED light-emitting material is arranged in the RGB OLED light-emitting layer of the green sub-pixel unit; the RGB OLED light-emitting layer of the blue sub-pixel unit is a blue OLED light-emitting material, and the drain electrode is located on one side, far away from the driving back plate, of the RGB OLED light-emitting layer.
Preferably, the VDMOS device includes an NPN-type semiconductor layer, a gate electrode, and a gate insulating layer, the NPN-type semiconductor layer is located on a side of the anode away from the driving backplane, the gate insulating layer is plated on outer sidewalls of the NPN-type semiconductor layer and the anode, and the gate electrode covers a side edge of the gate insulating layer.
Preferably, the LED light-emitting unit includes a bonding metal layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer, the bonding metal layer is grown on one side of the ITO/TiN thin film layer away from the driving backplane in a bonding manner, and the first semiconductor layer is located on one side of the bonding metal layer away from the driving backplane; the light emitting layer is arranged on one side, away from the driving backboard, of the first semiconductor layer; the second semiconductor layer is arranged on one side of the light-emitting layer far away from the driving backboard; the light emitting layers in the red, green and blue sub-pixel units emit blue light.
Preferably, the LED light-emitting unit is an OLED white light layer, and the OLED white light layer is located on one side of the ITO/TiN thin film layer, which is far away from the driving backboard, and is in contact with the ITO/TiN thin film layer.
Preferably, the device also comprises a first film packaging layer, a common cathode and a second film packaging layer, wherein,
the first film packaging layer covers the upper surfaces of the VDMOS device, the LED light-emitting unit and the driving back plate, a first electrode groove is formed in the corresponding first film packaging layer in each sub-pixel unit, a part of the drain electrode is exposed, a second electrode groove is formed in the corresponding first film packaging layer between every two sub-pixel units, and the projection of the second electrode groove on the driving back plate is located between the two sub-pixel units;
the common cathode grows on one side, far away from the driving back plate, of the first thin film packaging layer and covers the first electrode groove and the second electrode groove, and the common cathode is in contact with the drain electrode through the first electrode groove;
the second film packaging layer grows on one side of the common cathode, which is far away from the driving back plate, and covers the common cathode.
Preferably, the device also comprises a first film packaging layer, a common cathode and a second film packaging layer, wherein,
the first film packaging layer is packaged and covers the upper surfaces of the VDMOS device, the ITO/TiN film layer, the LED light-emitting units and the driving back plate, electrode grooves are formed in the first film packaging layers corresponding to the sub-pixel units, and the bottoms of the electrode grooves in the sub-pixel units are exposed out of the upper surfaces of the LED light-emitting units;
the common cathode is arranged on a layer, far away from the driving back plate, of the first film packaging layer and covers the electrode groove, and in the sub-pixel unit, the common cathode is in contact with the upper surface of the LED light-emitting unit through the electrode groove;
the second film packaging layer is positioned on one side, away from the driving back plate, of the common cathode and covers the common cathode, first grooves are formed in the second film packaging layers corresponding to the red sub-pixel units and the green sub-pixel units, colored conversion layers are arranged in the first grooves, red quantum dot materials are filled in the colored conversion layers in the red sub-pixel units, green quantum dot materials are filled in the colored conversion layers in the green sub-pixel units, the first grooves are overlapped with projections of the VDMOS devices on the driving back plate, second grooves are further formed in the second film packaging layer, and vertical projections of the second grooves on the driving back plate are positioned between vertical projections of the adjacent sub-pixel units on the driving back plate; an isolation layer is arranged on one side, away from the driving back plate, of the second thin film packaging layer, the isolation layer covers the color conversion layer and the second groove, an anti-crosstalk layer is further arranged in the second groove, and the anti-crosstalk layer covers the isolation layer on the bottom and the side wall of the second groove.
Preferably, the organic electroluminescent device further comprises a first thin film encapsulation layer, a common cathode, a second thin film encapsulation layer and an RGB filter layer, wherein,
the first thin film packaging layer is filled in gaps among the VDMOS devices, and the top surface of the first thin film packaging layer is flush with the ITO/TiN thin film layer;
the common cathode is arranged on one side of the OLED white light layer far away from the driving backboard;
the second thin film packaging layer is arranged on one side of the common cathode, which is far away from the driving back plate;
RGB filter layer includes red filter unit R, green filter unit G, blue filter unit B and black matrix, and interval arrangement sets up in proper order on second film encapsulation layer upper surface, red filter unit R, green filter unit G and blue filter unit B overlap with the projection of the VDMOS device in each sub-pixel unit on the drive backplate respectively, the black matrix centers on red filter unit R, green filter unit G and blue filter unit B's periphery sets up.
Preferably, the packaging structure further comprises a glass packaging layer which is bonded to the topmost layer of the whole packaging structure through UV glue.
Has the advantages that: the invention provides a triode display with a VDMOS device structure, wherein a vertical oxide transistor (VDMOS) device is prepared on the surface of a driving backboard through a semiconductor process to drive an OLED display unit, so that a novel transistor micro-display with low power consumption and quick response is obtained. The intrinsic amplification is provided for the current carrier through the conductance gain of the transistor, the electrical noise in the micro-display device is obviously reduced, and the high-gain driving can be realized for the high-resolution micro-display, so that the rapid and clear display of a static image and a dynamic video under low current becomes possible.
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FIG. 1 is a schematic view of step S1 in example 1;
FIG. 2 is a schematic view of step S2 in example 1;
FIG. 3 is a schematic view of step S3 in example 1;
fig. 4 is a schematic view of step S4 in embodiment 1, which is a schematic view of the overall structure of the present invention;
FIG. 5 is a pixel arrangement scheme optimized in example 1;
FIG. 6 is a schematic view of step S1 in example 2;
FIG. 7 is a schematic view of step S2 in example 2;
FIG. 8 is a schematic view of step S3 in example 2;
FIG. 9 is a schematic view of step S4 in example 2;
FIG. 10 is a view showing step S5 in example 2;
fig. 11 is a schematic view of step S6 in embodiment 2, that is, a schematic view of the entire structure in embodiment 2;
FIG. 12 is an optimized pixel arrangement scheme in example 2;
FIG. 13 is a schematic view of step S1 in example 3;
FIG. 14 is a view showing step S2 in example 3;
FIG. 15 is a schematic view of step S3 in example 3;
FIG. 16 is a view showing step S4 in example 3;
FIG. 17 is a schematic view of step S5 in example 3;
FIG. 18 is a view showing step S6 in example 3;
FIG. 19 is a view showing step S7 in example 3;
FIG. 20 is a view showing step S8 in example 3;
FIG. 21 is a view showing step S9 in example 3;
FIG. 22 is a view showing step S10 in example 3;
fig. 23 is a schematic view of step S11 in embodiment 3, that is, a schematic view of the entire structure in embodiment 3;
FIG. 24 is an optimized pixel arrangement scheme in example 3;
in the figure: the pixel structure comprises a red sub-pixel unit 1-1, a green sub-pixel unit 1-2, a blue sub-pixel unit 1-3, a driving back plate 2, a via hole 3, an anode 4, a VDMOS device 5, an NPN type semiconductor layer 5-1, an SiN side wall protection layer 5-2, a grid insulation layer 5-3, a grid 5-4, an open slot 5-5, an ITO/TiN thin film layer 6, an LED light-emitting unit 7, an RGB OLED light-emitting layer 7-1, a drain 7-2, a white OLED layer 7-3, a bonding metal layer 7-4, a first semiconductor layer 7-5, a light-emitting layer 7-6, a second semiconductor layer 7-7, an LED substrate 7-8, a first thin film packaging layer 8, a first electrode slot 8-1, a second electrode slot 8-2, an electrode slot 8-3, a common cathode 9, a second thin film packaging layer 10, The color filter comprises a first groove 10-1, a color conversion layer 10-2, a second groove 10-3, a glass packaging layer 11, UV glue 12, a red light filtering unit R13-1, a green light filtering unit G13-2, a blue light filtering unit B13-3, a black matrix 13-4, an isolating layer 14 and an anti-crosstalk layer 15.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example 1: a triode display of VDMOS device structure comprising:
the pixel comprises three sub-pixel units, namely a red sub-pixel unit 1-1, a green sub-pixel unit 1-2 and a blue sub-pixel unit 1-3;
the driving back plate 2 is provided with a plurality of regularly arranged through holes 3, and the sub-pixel unit covers at least one through hole 2; the driving back plate bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode 4, a VDMOS device 5, an ITO/TiN thin film layer 6 and an LED light-emitting unit, wherein the anode 4 is arranged on the driving backboard 2 and covers at least one via hole 3, the VDMOS device 5 is arranged on one side, away from the driving backboard 2, of the anode 4, the ITO/TiN thin film layer 6 comprises an ITO thin film layer and a TiN thin film layer which are vertically stacked, the TiN thin film layer is arranged on one side, away from the driving backboard, of the VDMOS device 5, the ITO thin film layer is arranged on one side, away from the driving backboard 2, of the TiN thin film layer, and the LED light-emitting unit is arranged on one side, away from the driving backboard 2, of the ITO thin film layer 6.
The VDMOS device 5 comprises an NPN type semiconductor layer 5-1, a SiN side wall protection layer 5-2, a grid electrode insulation layer 5-3 and a grid electrode 5-4, the NPN type semiconductor layer 5-1 is located on the side of the anode 4 remote from the driving backplate 2, the ITO/TiN thin film layer 6 is arranged on one side of the NPN type semiconductor layer 5-1 far away from the driving backboard 2, the SiN side wall protection layer 5-2 is arranged on the periphery of the upper surface of the ITO/TiN thin film layer 6 to form a SiN groove, the grid insulation layer 5-3 is coated on the outer side walls of the SiN side wall protection layer, the ITO/TiN thin film layer 6 and the NPN type semiconductor layer 5-1, the grid electrode 5-4 is arranged on the side wall of the grid electrode insulating layer 5-3, the vertical section of the grid electrode insulating layer 5-3 is of an L-shaped structure, and the bottom surface of the grid electrode 5-4 is in contact with the grid electrode insulating layer 5-3.
The LED light-emitting unit comprises an RGB OLED light-emitting layer 7-1 and a drain electrode 7-2, the RGB OLED light-emitting layer 7-1 is positioned on one side, away from the driving backboard 2, of the ITO/TiN thin film layer 6 in the SiN groove, and a red OLED light-emitting material is arranged in the RGB OLED light-emitting layer 7-1 of the red sub-pixel unit 1-1; a green OLED light-emitting material is arranged in the RGB OLED light-emitting layer 7-1 of the green sub-pixel unit 1-2; the RGB OLED light emitting layer 7-1 of the blue sub-pixel unit 1-3 is a blue OLED light emitting material, and the drain 7-2 is located on one side of the RGB OLED light emitting layer 7-1 away from the driving backboard 2.
The driving back panel comprises a first thin film packaging layer 8, wherein the first thin film packaging layer 8 covers the upper surfaces of a VDMOS device 5, an LED light-emitting unit and a driving back panel 2, a first electrode groove 8-1 is formed in the first thin film packaging layer 8 corresponding to each sub-pixel unit, a part of a drain electrode 7-2 is exposed, a second electrode groove 8-2 is further formed in the first thin film packaging layer 8 corresponding to each two sub-pixel units, the projection of the second electrode groove 8-2 on the driving back panel 2 is located between the two sub-pixel units, and the bottom surface of the second electrode groove 8-2 is flush with the top surface of a grid electrode 5-4;
and the common cathode 9 grows on one side of the first thin film packaging layer 8, which is far away from the driving back plate 2, and covers the first electrode groove 8-1 and the second electrode groove 8-2, and the common cathode 9 is in contact with the drain electrode 7-2 through the first electrode groove 8-1.
And a second thin film encapsulation layer 10, wherein the second thin film encapsulation layer 10 is grown on one side of the common cathode 9 far away from the driving back plate 2 and covers the common cathode 9.
The glass packaging layer 11 is bonded to the second film packaging layer 10 through UV glue 12, and the UV glue 12 is located in the frame area of the second film packaging layer 10.
In example 1, the specific steps of preparing a triode display with a VDMOS device structure are as follows:
s1, forming a plurality of via holes 3 which are regularly arranged on a driving backboard 2, filling conductive materials in the via holes 3, forming a plurality of anodes 4 on the upper surface of the driving backboard 2 and contacting with the upper surface of the via holes 3, forming an NPN type semiconductor layer 5-1 on one side of the anode 4 far away from the driving backboard 2, forming an ITO/TiN thin film layer 6 on one side of the NPN type semiconductor layer 5-1 far away from the driving backboard 2, preparing SiN side wall protection layers 5-2 on the periphery of the upper surface of the ITO/TiN thin film layer 6 to form an SiN groove, printing RGB OLED luminescent materials on the ITO/TiN thin film layer 6 in the SiN groove by adopting electrofluid to form an RGB OLED luminescent layer 7-1, and then growing a drain electrode 7-2 on the RGB OLED luminescent layer 7-1 by adopting an atomic layer deposition method; then, growing a part of first thin film packaging layer 8 on the surface of the drain electrode 7-2; in the invention, the drain electrode 7-2 is an Al film layer, and the thickness of the Al film layer is 100 nm.
S2, growing a gate insulating layer 5-3 on the anode 4, the outer side walls of the NPN type semiconductor layer 5-1 and the SiN side wall protective layer 5-2 and the driving back plate 2 by adopting a chemical vapor deposition method, and plating a gate 5-4 on one side of the gate insulating layer 5-3 away from the driving back plate 2 by adopting an epitaxial growth technology;
s3, sequentially processing a grid electrode 5-4 and a grid electrode insulating layer 5-3 by adopting a spacer etch process, then continuing to grow a first thin film packaging layer 8, and carrying out patterning treatment on the first thin film packaging layer 8 to form a plurality of first electrode grooves 8-1 and second electrode grooves 8-2;
s4, preparing a common cathode 9 on the side of the first film packaging layer 8 far away from the driving backboard 2, then forming a second film packaging layer 10 on the side of the common cathode 9 far away from the driving backboard 2, and finally adhering a glass packaging layer 11 on the upper surface of the second film packaging layer 11 by using UV glue 12.
In embodiment 1, the material of the first thin film encapsulation layer 8 and the second thin film encapsulation layer 10 may be an organic thin film, an inorganic thin film, or an inorganic thin film stacked on an organic thin film.
In example 1, the cathode was an Al film.
In example 1, the gate insulating layer 5-3 was prepared using SiO2, SiN, or Al2O 3; the grid is prepared by adopting a p-Si semiconductor; the anode 4 is made of metal oxide, including indium tin oxide, indium zinc oxide, or aluminum zinc oxide.
In example 1, the plated gate insulating layer may be formed by a chemical vapor deposition method or an atomic layer deposition method, and the gate may be formed by a molecular beam epitaxy technique.
The optimized pixel arrangement scheme of example 1 is shown in fig. 5, and one pixel includes two green sub-pixel units, one red sub-pixel unit and one blue sub-pixel unit. In terms of spatial distribution, four vertexes of a square pixel unit respectively comprise a green sub-pixel unit positioned at two opposite vertexes, and a red sub-pixel unit and a blue sub-pixel unit positioned at the other two vertexes, and the side length of the square pixel unit is equal to that of the pixel pich. Four sets of red sub-pixel elements are grouped together, four sets of blue sub-pixel elements are grouped together, four sets of green sub-pixel elements are grouped together, and each group shares a mask opening. Specifically, two green sub-pixel units, one red sub-pixel unit and one blue sub-pixel unit are located on the same plane and arranged in a field shape, and four sub-pixel units with the same color are arranged in a concentrated manner. The field-shaped structure is in array arrangement, which is beneficial to the compactness of pixels and improves the display effect of the pixels.
The pixel arrangement optimization scheme shown in fig. 5, in combination with the high-resolution driving backplane, can realize a high-resolution real RGB display screen body of 1000ppi or more, thereby realizing high-resolution patterning, which is no longer limited by the physical limit of the high-resolution metal mask FMM.
Example 2: as shown in fig. 11, a triode display of VDMOS device structure includes:
the pixel comprises three sub-pixel units, namely a red sub-pixel unit 1-1, a green sub-pixel unit 1-2 and a blue sub-pixel unit 1-3;
the driving back plate 2 is provided with a plurality of regularly arranged through holes 3, and the sub-pixel unit covers at least one through hole 3; the driving back plate 2 bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode 4, a VDMOS device 5, an ITO/TiN thin film layer 6 and an LED light-emitting unit, wherein the anode 4 is arranged on the driving backboard 2 and covers at least one via hole 3, the VDMOS device 5 is arranged on one side, away from the driving backboard 2, of the anode 4, the ITO/TiN thin film layer 6 comprises an ITO thin film layer and a TiN thin film layer which are vertically stacked, the TiN thin film layer is arranged on one side, away from the driving backboard 2, of the VDMOS device 5, the ITO thin film layer is arranged on one side, away from the driving backboard 2, of the TiN thin film layer, and the LED light-emitting unit is arranged on one side, away from the driving backboard 2, of the ITO thin film layer.
The VDMOS device 5 comprises an NPN type semiconductor layer 5-1, a grid 5-4 and a grid insulating layer 5-3, the NPN type semiconductor layer 5-1 is located on one side, away from the driving backboard 2, of the anode 4, the grid insulating layer 5-3 is plated on the outer side walls of the NPN type semiconductor layer 5-1 and the anode 4, and the grid 5-4 covers the side edge of the grid insulating layer 5-3.
The LED light-emitting unit is an OLED white light layer, and the OLED white light layer 7 is located on one side, away from the driving backboard 2, of the ITO/TiN thin film layer 6 and is in contact with the ITO/TiN thin film layer 6.
The first thin film packaging layer 8 is filled in gaps among the VDMOS devices 5, and the top surface of the first thin film packaging layer 8 is flush with the ITO/TiN thin film layer 6;
a common cathode 9, wherein the common cathode 9 is arranged on one side of the OLED white light layer 7 far away from the driving backboard 2;
the second thin film packaging layer 10 is arranged on one side, away from the driving back plate 2, of the common cathode 9;
the RGB light filter layer comprises a red light filter unit R13-1, a green light filter unit G13-2, a blue light filter unit B13-3 and a black matrix 13-4 which are sequentially arranged on the upper surface of the second thin film packaging layer 10 at intervals, the red light filter unit R13-1, the green light filter unit G13-2 and the blue light filter unit B13-3 are respectively overlapped with the projections of the VDMOS devices 5 in the sub-pixel units on the driving backboard 2, and the black matrix 13-4 is arranged around the peripheries of the red light filter unit R13-1, the green light filter unit G13-2 and the blue light filter unit B13-3.
Glass packaging layer 11, glass packaging layer 11 passes through UV glue 13 and bonds in RGB filter layer top, UV glues 12 frame regions that are located RGB filter layer.
The specific steps of fabricating the light emitting diode display of the VDMOS device structure in embodiment 2 are as follows:
s1, as shown in FIG. 6, forming a plurality of via holes 3 regularly arranged on the driving backboard 2, filling conductive materials in the via holes 3, forming a plurality of anodes 4 on the upper surface of the driving backboard 2 and contacting with the upper surfaces of the via holes 3, forming an NPN type semiconductor layer 5-1 on the upper surface of the anode 3, and simultaneously carrying out patterning treatment on the NPN type semiconductor layer 5-1;
s2, as shown in FIG. 7, sequentially plating a gate insulating layer 5-3 and a gate electrode 5-4 on the outer surfaces of the NPN type semiconductor layer 5-1 and the anode 4;
s3, processing a grid electrode 5-4 and a grid electrode insulating layer 5-3 in sequence by adopting a Spacer etch process to obtain a VDMOS device 5, wherein the grid electrode insulating layer 5-3 is plated on the outer side walls of an NPN type semiconductor layer 5-1 and an anode 4, the grid electrode 5-4 covers the side edge of the grid electrode insulating layer 5-3, and an open slot 5-5 is formed on the upper surface of the NPN type semiconductor layer 5-1;
s4, as shown in FIG. 9, an ITO/TiN thin film layer 6 is formed on the opening of the upper surface of the NPN type semiconductor layer 4-3 by plating, and the periphery of each VDMOS device 4 is filled with a first thin film packaging layer 8;
s5, forming a white light OLED layer 7-3, a common cathode 9 and a second film packaging layer 10 on the upper surfaces of the ITO/TiN film layer 6 and the first film packaging layer 8 in sequence by adopting an evaporation process as shown in the figure 10;
s6, as shown in FIG. 11, preparing RGB filter layers on the upper surface of the second film encapsulation layer 9 in sequence, so that the black matrix 13-4 surrounds the red filter unit R13-1, the green filter unit G13-2 and the blue filter unit B13-3, and finally bonding the glass encapsulation layer 11 on the RGB filter layers by using UV glue 12.
In example 2, SiO was used for the gate insulating layer 5-32SiN or Al2O3Preparing to obtain; the grid 5-4 is prepared by adopting a p-Si semiconductor; the anode 4 is made of metal oxide, including indium tin oxide, indium zinc oxide, or aluminum zinc oxide.
In example 2, the gate insulating layer may be formed by cvd or ald, and the gate 5-4 may be formed by molecular beam epitaxy.
In embodiment 2, the material of the first thin film encapsulation layer 8 and the second thin film encapsulation layer 10 may be an organic thin film, an inorganic thin film, or an inorganic thin film stacked on an organic thin film.
In embodiment 2, the RGB filter layer includes a red filter cell R13-1 (CF-R), a green filter cell G13-2 (CF-G), and a blue filter cell B13-3 (CF-B). Correspondingly, the red filter unit R13-1 comprises a red filter, the green filter unit G13-2 comprises a green filter, and the blue filter unit B13-3 comprises a blue filter. The black matrix enclosure 13-4 is disposed around the peripheries of the red filter cell R13-1, the green filter cell G13-2, and the blue filter cell B13-3. The red light filtering unit R13-1, the green light filtering unit G13-2 and the blue light filtering unit B13-3 are respectively arranged in one-to-one correspondence with the VDMOS devices, the projection of each light filtering unit on the driving backboard is at least partially overlapped with the projection of the VDMOS device on the driving backboard, and the projection of each light filtering unit on the driving backboard is not smaller than the projection of the VDMOS device on the driving backboard. The projection of the black matrix on the driving back plate is staggered with the projection of the filtering unit on the driving back plate, the black matrix plays a role in shading light, and the problems that the image contrast displayed by the display panel is reduced and incomplete images appear are solved.
The ITO/TiN thin film layer 6 in example 2 is an ITO thin film layer and a TiN thin film layer provided on top of each other, and the TiN thin film layer is in contact with the NPN-type semiconductor layer. The ITO/TiN film layer is used for improving work function ratio.
The optimized pixel arrangement scheme of the present invention is shown in fig. 12, where one pixel includes a strip-shaped sub-pixel unit G, a square-shaped sub-pixel unit R, and a sub-pixel unit B. In terms of spatial distribution, four vertexes of a square pixel unit respectively comprise a strip-shaped sub-pixel unit G, a sub-pixel unit R and a sub-pixel unit B which are positioned at the other two vertexes, and the side length of the square pixel unit is equal to the width of a pixel. The four sets of sub-pixel cells R are in one group, the four sets of sub-pixel cells B are in one group, the two sets of sub-pixel cells G are in one group, and each group shares one mask opening.
The sub-pixel unit G, the sub-pixel unit R and the sub-pixel unit B are located on the same plane. The sub-pixel units R and the sub-pixel units B are arranged in a field shape, and four sub-pixel units with the same color are arranged in a concentrated mode. The two sub-pixel units G are arranged side by side in a concentrated manner. The field-shaped structure is arranged in an array mode, so that the compactness of pixels is facilitated, and the display effect of the pixels is improved.
The pixel optimization arrangement scheme shown in fig. 12, in combination with the high-resolution driving backplane, can realize a high-resolution real RGB display screen body of 1000ppi or more, thereby realizing high-resolution patterning, which is no longer limited by the physical limit of the high-resolution metal mask FMM.
Example 3: as shown in fig. 23, a triode display of VDMOS device structure includes:
the pixel comprises three sub-pixel units, namely a red sub-pixel unit 1-1, a green sub-pixel unit 1-2 and a blue sub-pixel unit 1-3;
the driving back plate 2 is provided with a plurality of regularly arranged through holes 3, and the sub-pixel unit covers at least one through hole 3; the driving back plate 2 bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode 4, a VDMOS device 5, an ITO/TiN thin film layer 6 and an LED light-emitting unit, wherein the anode 4 is arranged on the driving backboard 2 and covers at least one via hole 3, the VDMOS device 5 is arranged on one side, away from the driving backboard 2, of the anode 4, the ITO/TiN thin film layer 6 comprises an ITO thin film layer and a TiN thin film layer which are vertically stacked, the TiN thin film layer is arranged on one side, away from the driving backboard 2, of the VDMOS device 5, the ITO thin film layer is arranged on one side, away from the driving backboard, of the TiN thin film layer, and the LED light-emitting unit is arranged on one side, away from the driving backboard 2, of the ITO thin film layer.
The VDMOS device 5 comprises an NPN type semiconductor layer 5-1, a grid electrode 5-4 and a grid electrode insulating layer 5-3, the NPN type semiconductor layer 5-1 is located on one side, away from the driving backboard, of the anode 4, the grid electrode insulating layer is plated on the outer side walls of the NPN type semiconductor layer 5-1 and the anode 4, and the grid electrode 5-4 covers the side edge of the grid electrode insulating layer 5-4.
The LED light-emitting unit 7 comprises a bonding metal layer 7-4, a first semiconductor layer 7-5, a light-emitting layer 7-6 and a second semiconductor layer 7-7, wherein the bonding metal layer 7-4 grows on one side, away from the driving backboard 2, of the ITO/TiN thin film layer 6 in a bonding mode, and the first semiconductor layer 7-5 is located on one side, away from the driving backboard 2, of the bonding metal layer 7-4; the light emitting layer 7-6 is arranged on one side of the first semiconductor layer 7-7 far away from the driving backboard 2; the second semiconductor layer 7-7 is arranged on one side of the light-emitting layer 7-6 far away from the driving backboard 2; the light emitting layers in the red sub-pixel unit 1-1, the green sub-pixel unit 1-2, and the blue sub-pixel unit 1-3 emit blue light.
The driving unit comprises a first thin film packaging layer 8, the first thin film packaging layer 8 is used for packaging and coating the upper surfaces of a VDMOS device 5, an ITO/TiN thin film layer 6, an LED light-emitting unit 7 and a driving backboard 2, electrode grooves 8-3 are formed in the first thin film packaging layer 8 corresponding to the sub-pixel units, and the bottoms of the electrode grooves 8-3 in the sub-pixel units are exposed out of the upper surfaces of the LED light-emitting units (second semiconductor layers 7-7);
the common cathode 9 is arranged on a layer, away from the driving back plate 2, of the first thin film packaging layer 8, and covers the electrode grooves 8-3, and in the sub-pixel unit, the common cathode 9 is in contact with the upper surface of the LED light-emitting unit 7 through the electrode grooves 8-3;
a second thin film encapsulation layer 10, wherein the second thin film encapsulation layer 10 is positioned on one side of the common cathode 9 far away from the driving back plate 2, and covers the common cathode 9, a first groove 10-1 is arranged on the second film packaging layer 10 corresponding to the red sub-pixel unit 1-1 and the green sub-pixel unit 1-2, a colored conversion layer 10-2 is arranged in the first groove 10-1, a red quantum dot material is filled in the colored conversion layer 10-2 in the red sub-pixel unit, a green quantum dot material is filled in the colored conversion layer 10-2 in the green sub-pixel unit, the first recess 10-1 overlaps the projection of the VDMOS device 5 onto the driving backplane 2, a second groove 10-3 is further formed in the second thin film encapsulation layer 10, and a vertical projection of the second groove 10-3 on the driving back plate 2 is located between vertical projections of adjacent sub-pixel units on the driving back plate 2; an isolation layer 14 is arranged on one side of the second thin film package 10, which is far away from the driving back plate, the isolation layer 14 covers the color conversion layer 10-2 and the second groove 10-3, a crosstalk prevention layer 15 is further arranged in the second groove 10-3, and the crosstalk prevention layer 15 covers the isolation layer 14 on the bottom and the side wall of the second groove 10-3.
And the glass packaging layer 11 is bonded to the topmost layer of the whole packaging structure through UV glue 13.
The specific preparation steps of the triode display with the VDMOS device structure in the embodiment 3 are as follows:
s1, as shown in fig. 13, forming a plurality of via holes 3 regularly arranged on the driving backplate 2, filling the via holes 3 with a conductive material, forming a plurality of anodes 4 on the upper surface of the driving backplate 2 and contacting the upper surfaces of the via holes 3, and forming an NPN type semiconductor layer 5-1 on the upper surface of the anodes 4, and simultaneously patterning the NPN type semiconductor layer 5-1, as shown in fig. 1.
S2, as shown in FIG. 14, a gate insulating layer 5-3 and a gate electrode 5-5 are sequentially plated on the outer surfaces of the NPN type semiconductor layer 5-1 and the anode 4, wherein the gate insulating layer 5-3 may be made of SiO2SiN or Al2O3(ii) a The material of the gate 5-5 may be a p-Si semiconductor.
S3, as shown in fig. 15, processing the gate 5-4 and the gate insulating layer 5-3 in sequence by using a Spacer etch process to obtain the VDMOS device 5, so that the gate insulating layer 5-3 is plated on outer sidewalls of the NPN type semiconductor layer 5-1 and the anode 4, the gate 5-4 covers a side of the gate insulating layer 5-3, and an open slot 5-5 is formed on an upper surface of the NPN type semiconductor layer 5-1, wherein the anode material may be a bond metal.
S4, as shown in fig. 16, an ITO/TiN thin film layer 6 is formed by plating on the open groove 5-5 on the upper surface of the NPN type semiconductor layer 5-1, and the periphery of each VDMOS device 5 is filled with the first thin film encapsulation layer 8.
S5, as shown in FIG. 17, depositing a bonding metal layer 6 on the driving backboard 2, directly bonding the bonding metal layer with a prefabricated LED substrate 7-8, and then peeling off the LED substrate 7-8, wherein the prefabricated LED substrate 7-8 is sequentially provided with a first semiconductor layer 7-5, a light emitting layer 7-6 and a second semiconductor layer 7-7 from top to bottom, namely the second semiconductor layer 7-7 is attached to the LED substrate 7-8, and the first semiconductor layer 7-5 can be made of P-type gallium nitride (P-GaN); the material of the second semiconductor layer 7-7 may be N-type gallium nitride (N-GaN); the material of the light-emitting layer 7-6 may be, for example, a Multiple Quantum Well (MQW).
And S6, as shown in FIG. 18, patterning the bonding metal layer 7-4, the first semiconductor layer 7-5, the light emitting layer 7-6 and the second semiconductor layer 7-7.
S7: as shown in fig. 19, the first thin film encapsulation layer 8 continues to grow on the periphery of the LED light emitting unit 7 and the upper surface of the first thin film encapsulation layer 8, and at the same time, the first thin film encapsulation layer 8 is subjected to patterning processing to obtain an electrode groove 8-3, so that the bottom of the electrode groove 8-3 is in contact with the upper surface of the second semiconductor layer 7-7.
S8: as shown in fig. 20, an Al thin film layer is grown on the first thin film encapsulation layer 8 and the side of the electrode groove 8-3 away from the driving backplate 2 as a common cathode 9 of each sub-pixel unit, wherein the Al thin film layer is in contact with the second semiconductor layer 7-7.
S9, as shown in FIG. 21, growing a second thin film encapsulation layer 10 on the upper surface of the common cathode 9, and carrying out patterning treatment on the second thin film encapsulation layer to obtain a first groove 10-1 and a second groove 10-3; the material of the first film encapsulation layer 11 and the second film encapsulation layer 13 in the present invention may be an organic film, an inorganic film, or an inorganic film stacked on an organic film.
S10, printing red and green quantum dots by using an electrofluid in the first groove 10-1 to form a color conversion layer 10-2, wherein the color conversion layer 10-2 of the red sub-pixel unit 1-1 prints the red quantum dots by using the electrofluid and the color conversion layer 10-2 of the green sub-pixel unit 1-2 prints the green quantum dots by using the electrofluid, as shown in FIG. 22; and then preparing an isolation layer 14 on one side of the second thin film packaging layer 10 far away from the driving back plate 2 by adopting an atomic layer deposition method, covering the color conversion layer 10-2 and the second groove 10-3, and then preparing an anti-crosstalk layer 15 in the second groove 10-3, covering the bottom and the side wall of the second groove 10-3. The isolation layer 14 may be made of aluminum oxide for protecting the color conversion layer 10-2, and the crosstalk prevention layer 15 may be made of aluminum.
And S11, finally, adhering the glass sealing layer 16 to the upper surface of the isolation layer 14 by using the UV glue 17, as shown in fig. 23.
The scheme for optimizing pixel arrangement of the present invention is shown in fig. 24, and one pixel includes a sub-pixel unit R, a sub-pixel unit G, a sub-pixel unit B and a blank sub-pixel. In the spatial distribution, four vertexes of a square pixel unit are respectively a sub-pixel unit R, a sub-pixel unit G, a sub-pixel unit B and a blank sub-pixel, and the side length of the square pixel unit is equal to the pixel width. The four sets of sub-pixel cells R are in one group, the four sets of sub-pixel cells B are in one group, the four sets of sub-pixel cells G are in one group, and each group shares one mask opening.
Specifically, the sub-pixel unit R, the sub-pixel unit G, the sub-pixel unit B and the blank sub-pixel are located on the same plane. The sub-pixel units R, the sub-pixel units G, the sub-pixel units B and the blank sub-pixels are arranged in a field shape, four sub-pixel units with the same color are arranged in a concentrated mode, and four blank sub-pixels are arranged in a concentrated mode. The field-shaped structure is in array arrangement, which is beneficial to the compactness of pixels and improves the display effect of the pixels.
The pixel arrangement optimization scheme shown in fig. 24, in combination with the high-resolution driving backplane, can realize a high-resolution real RGB display screen body of 1000ppi or more, thereby realizing high-resolution patterning, which is no longer limited by the physical limit of the high-resolution metal mask FMM.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A triode display with a VDMOS device structure is characterized by comprising:
the pixel comprises a plurality of pixels, wherein each pixel comprises three sub-pixel units, including a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the driving back plate is provided with a plurality of regularly arranged through holes, and the sub-pixel unit covers at least one through hole; the driving back plate bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode, a VDMOS device, an ITO/TiN thin film layer and an LED light-emitting unit, wherein the anode is arranged on the driving backboard and covers at least one via hole, the VDMOS device is arranged on one side, away from the driving backboard, of the anode, the ITO/TiN thin film layer comprises an ITO thin film layer and a TiN thin film layer which are stacked up and down, the TiN thin film layer is arranged on one side, away from the driving backboard, of the VDMOS device, the ITO thin film layer is arranged on one side, away from the driving backboard, of the TiN thin film layer, and the LED light-emitting unit is arranged on one side, away from the driving backboard, of the ITO thin film layer.
2. The VDMOS device structured triode display device according to claim 1, wherein the VDMOS device comprises an NPN semiconductor layer, an SiN sidewall protection layer, a gate insulating layer and a gate, the NPN semiconductor layer is located on one side of the anode away from the driving backboard, the ITO/TiN thin film layer is arranged on one side of the NPN semiconductor layer away from the driving backboard, the SiN sidewall protection layer is arranged around the upper surface of the ITO/TiN thin film layer to form an SiN groove, the gate insulating layer is coated on the outer sidewalls of the SiN sidewall protection layer, the ITO/TiN thin film layer and the NPN semiconductor layer, the gate is arranged on the sidewall of the gate insulating layer, the vertical section of the gate insulating layer is in an L-shaped structure, and the bottom surface of the gate is in contact with the gate insulating layer.
3. The VDMOS device structured triode display device according to claim 2, wherein the LED light emitting unit comprises an RGB OLED light emitting layer and a drain electrode, the RGB OLED light emitting layer is located on the side of the ITO/TiN thin film layer far away from the driving backboard in the SiN groove, and the RGB OLED light emitting layer of the red sub-pixel unit is made of red OLED light emitting materials; a green OLED light-emitting material is arranged in the RGB OLED light-emitting layer of the green sub-pixel unit; the RGB OLED light-emitting layer of the blue sub-pixel unit is a blue OLED light-emitting material, and the drain electrode is located on one side, far away from the driving back plate, of the RGB OLED light-emitting layer.
4. The triode display of VDMOS device structure of claim 1, wherein the VDMOS device comprises an NPN semiconductor layer on the side of the anode away from the driving backplate, a gate electrode plated on the outer sidewall of the NPN semiconductor layer and the anode, and a gate insulating layer covering the side of the gate insulating layer.
5. The VDMOS device structure triode display according to claim 4, wherein the LED light-emitting unit comprises a bonding metal layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer, the bonding metal layer is grown on the side, away from the driving backboard, of the ITO/TiN thin film layer in a bonding mode, and the first semiconductor layer is located on the side, away from the driving backboard, of the bonding metal layer; the light emitting layer is arranged on one side, away from the driving backboard, of the first semiconductor layer; the second semiconductor layer is arranged on one side of the light-emitting layer far away from the driving backboard; the light emitting layers in the red, green and blue sub-pixel units emit blue light.
6. The VDMOS device structured triode display according to claim 4, wherein the LED light emitting unit is an OLED white light layer located on a side of the ITO/TiN thin film layer away from the driving backplane and in contact with the ITO/TiN thin film layer.
7. The VDMOS device structured triode display of claim 3, further comprising a first thin film encapsulation layer, a common cathode, and a second thin film encapsulation layer, wherein,
the first film packaging layer covers the upper surfaces of the VDMOS device, the LED light-emitting unit and the driving back plate, a first electrode groove is formed in the corresponding first film packaging layer in each sub-pixel unit, a part of the drain electrode is exposed, a second electrode groove is formed in the corresponding first film packaging layer between every two sub-pixel units, and the projection of the second electrode groove on the driving back plate is located between the two sub-pixel units;
the common cathode grows on one side, far away from the driving back plate, of the first thin film packaging layer and covers the first electrode groove and the second electrode groove, and the common cathode is in contact with the drain electrode through the first electrode groove;
the second film packaging layer grows on one side of the common cathode, which is far away from the driving back plate, and covers the common cathode.
8. The VDMOS device structured triode display of claim 5, further comprising a first thin film encapsulation layer, a common cathode, and a second thin film encapsulation layer, wherein,
the first film packaging layer is packaged and covers the upper surfaces of the VDMOS device, the ITO/TiN film layer, the LED light-emitting units and the driving back plate, electrode grooves are formed in the first film packaging layers corresponding to the sub-pixel units, and the bottoms of the electrode grooves in the sub-pixel units are exposed out of the upper surfaces of the LED light-emitting units;
the common cathode is arranged on a layer, far away from the driving back plate, of the first film packaging layer and covers the electrode groove, and in the sub-pixel unit, the common cathode is in contact with the upper surface of the LED light-emitting unit through the electrode groove;
the second film packaging layer is positioned on one side, away from the driving back plate, of the common cathode and covers the common cathode, first grooves are formed in the second film packaging layers corresponding to the red sub-pixel units and the green sub-pixel units, colored conversion layers are arranged in the first grooves, red quantum dot materials are filled in the colored conversion layers in the red sub-pixel units, green quantum dot materials are filled in the colored conversion layers in the green sub-pixel units, the first grooves are overlapped with projections of the VDMOS devices on the driving back plate, second grooves are further formed in the second film packaging layer, and vertical projections of the second grooves on the driving back plate are positioned between vertical projections of the adjacent sub-pixel units on the driving back plate; an isolation layer is arranged on one side, away from the driving back plate, of the second thin film packaging layer, the isolation layer covers the color conversion layer and the second groove, an anti-crosstalk layer is further arranged in the second groove, and the anti-crosstalk layer covers the isolation layer on the bottom and the side wall of the second groove.
9. The VDMOS device structured triode display of claim 6, further comprising a first thin film encapsulation layer, a common cathode, a second thin film encapsulation layer, and an RGB filter layer, wherein,
the first thin film packaging layer is filled in gaps among the VDMOS devices, and the top surface of the first thin film packaging layer is flush with the ITO/TiN thin film layer;
the common cathode is arranged on one side of the OLED white light layer far away from the driving backboard;
the second thin film packaging layer is arranged on one side of the common cathode, which is far away from the driving back plate;
RGB filter layer includes red filter unit R, green filter unit G, blue filter unit B and black matrix, and interval arrangement sets up in proper order on second film encapsulation layer upper surface, red filter unit R, green filter unit G and blue filter unit B overlap with the projection of the VDMOS device in each sub-pixel unit on the drive backplate respectively, the black matrix centers on red filter unit R, green filter unit G and blue filter unit B's periphery sets up.
10. The triode display of VDMOS device structures of claims 7-9, further comprising a glass encapsulation layer bonded to the topmost layer of the overall encapsulation structure by UV glue.
CN202110594705.0A 2021-05-28 2021-05-28 Triode display with VDMOS device structure Pending CN113327988A (en)

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