CN113327986A - Gate electrode luminous triode display - Google Patents
Gate electrode luminous triode display Download PDFInfo
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- CN113327986A CN113327986A CN202110592846.9A CN202110592846A CN113327986A CN 113327986 A CN113327986 A CN 113327986A CN 202110592846 A CN202110592846 A CN 202110592846A CN 113327986 A CN113327986 A CN 113327986A
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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Abstract
The invention discloses a gate electrode luminous triode display, comprising: each pixel comprises three sub-pixel units, namely a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit; the driving back plate bears a plurality of pixels and is used for driving the sub-pixel units to emit light; the sub-pixel unit comprises an anode, a semiconductor layer, a plurality of gate electrodes, an ITO/TiN thin film layer and a light emitting layer. The invention reduces the response time, improves the display brightness, and has the display functions of high resolution, high brightness, high contrast and low response time.
Description
Technical Field
The invention relates to a gate electrode-based light-emitting triode display, belonging to the field of display manufacturing.
Background
With the continuous development of display technology, the application range of display panels is wider and wider, and the requirements of people on the display panels are higher and higher. For example, the display panel is applied to products such as mobile phones, computers, tablet computers, electronic books, information query machines, wearable devices and the like. As the application range of display panels is expanded, higher and higher requirements are put on display technologies and display devices. The traditional LED/OLED display has certain limitations and cannot meet more requirements of people on visual experience at present.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a gate electrode light-emitting triode display which realizes the display functions of high resolution, high brightness, high contrast and low response time.
The invention mainly adopts the technical scheme that:
a gate electrode light emitting triode display comprising:
each pixel comprises three sub-pixel units, namely a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the driving back plate is provided with a plurality of regularly arranged through holes, and the sub-pixel unit covers at least one through hole; the driving back plate bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode, a VDMOS device, an ITO/TiN thin film layer and a light-emitting unit, wherein the anode is arranged on the upper surface of the driving backboard and at least covers one via hole, the VDMOS device is positioned on one side, far away from the driving backboard, of the anode, the ITO/TiN thin film layer comprises an ITO thin film layer and a TiN thin film layer which are stacked up and down, the TiN thin film layer is arranged on one side, far away from the driving backboard, of the VDMOS device, the ITO thin film layer is arranged on one side, far away from the driving backboard, of the TiN thin film layer, and the light-emitting unit is arranged on one side, far away from the driving backboard, of the ITO thin film layer.
Preferably, the VDMOS device includes an NPN-type semiconductor layer and a plurality of gate electrodes, the NPN-type semiconductor layer is located on a side of the anode away from the driving backplane, a plurality of independent gate electrodes are disposed in the NPN-type semiconductor layer, each gate electrode includes a gate insulating layer and a gate, the gate has a V-shaped structure, and the gate insulating layers cover inner and outer sides of the gate.
Preferably, the VDMOS device includes an NPN-type semiconductor layer and a plurality of gate electrodes, the NPN-type semiconductor layer is located on a side of the anode away from the driving backplane, a plurality of independent gate electrodes are disposed in the NPN-type semiconductor layer, each gate electrode includes a gate insulating layer and a gate, the gate has a rectangular structure, and the gate insulating layer is of a rectangular frame structure and covers the periphery of the gate.
Preferably, the light emitting unit is an RGB OLED light emitting layer, and the material of the RGB OLED light emitting layer in the red sub-pixel unit is a red OLED light emitting material; the material of the RGB OLED light-emitting layer in the green sub-pixel unit is a green OLED light-emitting material; the material of the RGB OLED light-emitting layer in the blue sub-pixel unit is a blue OLED light-emitting material.
Preferably, the light emitting unit is an LED light emitting unit, the LED light emitting unit includes a first bonding metal layer, a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a second bonding metal layer, the first bonding metal layer is bonded and grown on one side of the ITO/TiN thin film layer away from the driving backplane, and the first semiconductor layer is located on an upper surface of the first bonding metal layer; the light emitting layer is arranged on the upper surface of the first semiconductor layer; the second semiconductor layer is arranged on the upper surface of the light-emitting layer, and the second bonding metal layer is positioned on one side, far away from the driving backboard, of the second semiconductor layer; the light emitting layer in the red sub-pixel unit emits red light, the light emitting layer in the green sub-pixel unit emits green light, and the light emitting layer in the blue sub-pixel unit emits blue light.
Preferably, the pixel structure further comprises a first film packaging layer, wherein the first film packaging layer is filled between the sub-pixel units, and the upper surface of the first film packaging layer is flush with the upper surface of the RGB OLED light emitting layer.
Preferably, the display panel further comprises a first film packaging layer, the first film packaging layer is filled between the sub-pixel units and covers the upper surfaces of the VDMOS device, the ITO/TiN film layer, the LED light-emitting unit and the driving backplane, the first film packaging layer corresponding to each of the sub-pixel units is provided with an electrode groove, and the bottom of the electrode groove in each of the sub-pixel units is exposed out of the upper surface of part of the LED light-emitting unit.
Preferably, the organic light emitting diode further comprises a common cathode, wherein the common cathode is positioned on one side of the first thin film packaging layer far away from the driving back plate and covers the RGB OLED light emitting layers.
Preferably, the display panel further comprises a common cathode, the common cathode is arranged on a layer of the first film packaging layer far away from the driving back plate and covers the electrode groove, and in the sub-pixel unit, the common cathode is in contact with the upper surface of the LED light-emitting unit through the electrode groove.
Preferably, the solar cell further comprises a second film packaging layer and a glass packaging layer, wherein the second film packaging layer grows on one side, far away from the upper surface of the driving backboard, of the common cathode, the glass packaging layer is connected to one side, far away from the driving backboard, of the second film packaging layer through UV glue, and the UV glue is located in a frame area of the second film packaging layer.
Has the advantages that: the invention provides a gate electrode light-emitting triode display.A vertical oxide transistor (VDMOS) device driving display unit is prepared on the surface of a back plate by a semiconductor process, and the VDMOS device has the advantages of high carrier mobility, low response time, simplification of an external circuit and the like. The intrinsic amplification is provided for the current carrier through the conductance gain of the transistor, the electrical noise in the micro-display device is obviously reduced, and the high-gain driving can be realized for the high-resolution micro-display, so that the rapid and clear display of a static image and a dynamic video under low current becomes possible.
Drawings
FIG. 1 is a schematic view illustrating step S1 of this embodiment 1;
fig. 2 is a schematic view of step S2 in the embodiment 1;
fig. 3 is a schematic view of step S3 in the embodiment 1;
fig. 4 is a schematic view of step S4 in the embodiment 1;
FIG. 5 is a schematic view illustrating step S5 of the present embodiment 1;
fig. 6 is a schematic view of step S6 in the embodiment 1; the invention is the overall structure schematic diagram of the invention;
FIG. 7 is a schematic diagram of an optimized pixel arrangement in the present embodiment 1;
FIG. 8 is a schematic view of step S1 in example 2;
FIG. 9 is a schematic view of step S2 in example 2;
FIG. 10 is a view showing step S3 in example 2;
FIG. 11 is a schematic view of step S4 in example 2;
FIG. 12 is a view showing step S5 in example 2;
FIG. 13 is a view showing step S6 in example 2;
FIG. 14 is a view showing step S7 in example 2;
FIG. 15 is a schematic view of step S9 in example 2;
FIG. 16 is a view showing step S10 in example 2;
fig. 17 is a schematic view of step S11 in embodiment 2, that is, a schematic view of the entire structure in embodiment 2;
FIG. 18 is an optimized pixel arrangement scheme in example 2;
in the figure: the pixel structure comprises a red sub-pixel unit 1-1, a green sub-pixel unit 1-2, a blue sub-pixel unit 1-3, a driving back plate 2, a via hole 3, an anode 4, a VDMOS device 5, an NPN type semiconductor layer 5-1, a gate electrode 5-2, a gate insulating layer 5-3, a gate 5-4, a rectangular groove 5-5, an ITO/TiN thin film layer 6, a light emitting unit 7, an RGB OLED light emitting layer 7-1, a first bonding metal layer 7-2, a first semiconductor layer 7-3, a light emitting layer 7-4, a second semiconductor layer 7-5, a second bonding metal layer 7-6, a first thin film packaging layer 9, a second thin film packaging layer 10, a common cathode 11, a glass packaging layer 12 and UV glue 13.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Real-time 1: as shown in fig. 6, a gate electrode light emitting triode display includes:
each pixel comprises three sub-pixel units, namely a red sub-pixel unit 1-1, a green sub-pixel unit 1-2 and a blue sub-pixel unit 1-3;
the driving back plate 2 is provided with a plurality of regularly arranged through holes 3, and the sub-pixel unit covers at least one through hole 3; the driving back plate 2 bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode 4, a VDMOS device 5, an ITO/TiN thin film layer 6 and a light-emitting unit 7, wherein the anode 4 is arranged on the upper surface of the driving backboard 2 and at least covers one via hole 3, the VDMOS device 5 is positioned on one side, away from the driving backboard 2, of the anode 4, the ITO/TiN thin film layer 6 comprises an ITO thin film layer and a TiN thin film layer which are stacked up and down, the TiN thin film layer is arranged on one side, away from the driving backboard, of the VDMOS device, the ITO thin film layer is arranged on one side, away from the driving backboard, of the TiN thin film layer, and the light-emitting unit 7 is arranged on one side, away from the driving backboard 2, of the ITO thin film layer.
The VDMOS device 5 comprises an NPN type semiconductor layer 5-1 and a plurality of gate electrodes 5-2, the NPN type semiconductor layer 5-1 is located on one side, away from the driving backboard 2, of the anode 4, the plurality of independent gate electrodes 5-2 are arranged in the NPN type semiconductor layer 5-1, the gate electrodes 5-2 comprise gate insulation layers 5-3 and gate electrodes 5-4, the gate electrodes 5-4 are of V-shaped structures, and the gate insulation layers 5-3 wrap the inner side and the outer side of the gate electrodes 5-4.
The light-emitting unit 7 is an RGB OLED light-emitting layer 7-1, and the material of the RGB OLED light-emitting layer 7-1 in the red sub-pixel unit 1-1 is a red OLED light-emitting material; the material of the RGB OLED light-emitting layer 7-1 in the green sub-pixel unit 1-2 is a green OLED light-emitting material; the material of the RGB OLED light-emitting layer 7-1 in the blue sub-pixel unit 1-3 is a blue OLED light-emitting material.
The first thin film packaging layer 9 is filled between the sub-pixel units, and the upper surface of the first thin film packaging layer 9 is flush with the upper surface of the RGB OLED light-emitting layer 7-1.
And the common cathode 11 is positioned on one side of the first thin film packaging layer 9 far away from the driving back plate 2 and covers the RGB OLED light-emitting layer 7-1.
A second thin film encapsulation layer 10, the second thin film encapsulation layer 10 is grown on the common cathode 11 at the side far away from the upper surface of the driving back plate 2,
the glass packaging layer 12 is bonded to one side, far away from the driving back plate 2, of the second film packaging layer 10 through UV glue 13, and the UV glue 13 is located in the frame area of the second film packaging layer 10.
The gate electrode light emitting triode display in embodiment 1 is specifically prepared by the following steps:
s1, as shown in FIG. 1, forming a plurality of regularly arranged via holes 3 on a driving backboard 2, filling a conductive material in the via holes 3, then forming a plurality of anodes 4 on the upper surface of the driving backboard 2 and contacting with the upper surface of the via holes 3, then forming an NPN type semiconductor layer 5-1 on the anodes 4 and the upper surface of the driving backboard 2, and simultaneously carrying out patterning treatment on the NPN type semiconductor layer 5-1 to enable the NPN type semiconductor layer 5-1 to be positioned on one side of the anodes 4, which is far away from the driving backboard 2, and forming a plurality of V-shaped grooves on the NPN type semiconductor layer 5-1, and then sequentially plating a grid insulating layer 5-3 and a grid 5-4 in the V-shaped grooves and the upper surface of the NPN type semiconductor layer 5-1 to enable the grid 5-4 to be in a V-shaped structure;
s2, as shown in FIG. 2, carrying out patterning treatment on the gate insulating layer 5-3 and the gate 5-4, wherein the exposed part of the gate insulating layer 5-3 after the patterning treatment is higher than the upper surface of the NPN type semiconductor layer 5-1, and the exposed part of the gate 5-4 is higher than the upper surface of the gate insulating layer 5-3;
s3, as shown in FIG. 3, depositing a gate insulating layer 5-3 on the inner side of the gate 5-4 and the upper surface of the NPN type semiconductor layer 5-1, and patterning the gate insulating layer to make the gate 5-4 be V-shaped, and the gate insulating layer 5-3 completely covers the gate 5-4 to form a gate electrode 5-2;
s4, as shown in FIG. 4, continuing to deposit N-type semiconductor material on the upper surface of the NPN-type semiconductor layer 5-1 and filling the N-type semiconductor material between the gate electrodes 5-2 to form a new NPN-type semiconductor layer 5-1, and then sequentially plating a TiN thin film layer and an ITO thin film layer on the upper surface of the new NPN-type semiconductor layer 5-1 and performing patterning treatment on the TiN thin film layer and the ITO thin film layer to cover the upper surface of the semiconductor layer 5; in the invention, the ITO/TiN film layer is used for improving the work function ratio.
S5, as shown in FIG. 5, printing the RGB OLED light-emitting layer by using electrofluid on the side of the ITO thin film layer 7 far away from the driving backboard 2, wherein the OLED-R light-emitting material is printed by using electrofluid in the RGB OLED light-emitting layer 7-1 of the red sub-pixel unit 1-1; an OLED-G light-emitting material is printed in an RGB OLED light-emitting layer 7-1 of the green sub-pixel unit 1-2 by using electrofluids; an electrofluid is used in the RGB OLED light emitting layer 7-1 of the blue sub-pixel unit 1-3 to print an OLED-B light emitting material, then a first thin film packaging layer 9 is filled between the sub-pixel units, the upper surface of the first thin film packaging layer 9 is flush with the upper surface of the RGB OLED light emitting layer 7-1, then an atomic layer deposition method is adopted to generate a common electrode 11 on one side, far away from the driving backboard 2, of the RGB OLED light emitting layer 7-1 and the first thin film packaging layer 9, the common electrode 11 covers the first thin film packaging layer 9 and the light emitting layer 8, and then a second thin film packaging layer 10 is generated on one side, far away from the driving backboard 2, of the common cathode 11; the material of the first thin film encapsulation layer 9 and the second thin film encapsulation layer 10 in the present invention can be an organic thin film, an inorganic thin film, or an inorganic thin film stacked on an organic thin film.
And S6, finally, adhering the glass packaging layer 12 to the upper surface of the second film packaging layer 10 by using the UV glue 13, as shown in FIG. 6.
As shown in fig. 4 to 6, arrows on both sides of the gate electrode 6 indicate the flow direction of carriers.
In this embodiment 1, the size of each sub-pixel unit is 3-100 μm, the size of one gate electrode is 0.5 μm, and each sub-pixel unit carries a plurality of gate electrodes, which can be selected by those skilled in the art according to actual requirements.
The ITO/TiN thin film layer 6 in this example 1 is an ITO thin film layer and a TiN thin film layer provided vertically, and the TiN thin film layer is in contact with the NPN type semiconductor layer. The ITO/TiN film layer is used for improving work function ratio.
The optimized pixel arrangement scheme of this embodiment 1 is shown in fig. 7, where a pixel includes a red sub-pixel unit, a green sub-pixel unit, a blue sub-pixel unit, and a blank sub-pixel. In the spatial distribution, four vertexes of a square pixel unit are respectively a red sub-pixel unit, a green sub-pixel unit, a blue sub-pixel unit and a blank sub-pixel, and the side length of the square pixel unit is equal to the pixel width. Four sets of red sub-pixel elements are grouped together, four sets of blue sub-pixel elements are grouped together, four sets of green sub-pixel elements are grouped together, and each group shares a mask opening.
Specifically, the red sub-pixel unit, the green sub-pixel unit, the blue sub-pixel unit and the blank sub-pixel are located on the same plane. The red sub-pixel units, the green sub-pixel units, the blue sub-pixel units and the blank sub-pixels are arranged in a field shape, four sub-pixel units with the same color are arranged in a concentrated mode, and four blank sub-pixels are arranged in a concentrated mode. The field-shaped structure is in array arrangement, which is beneficial to the compactness of pixels and improves the display effect of the pixels.
The pixel arrangement optimization scheme shown in fig. 7, in combination with the high-resolution driving backplane, can realize a high-resolution real RGB display screen body of 1000ppi or more, thereby realizing high-resolution patterning, which is no longer limited by the physical limit of the high-resolution metal mask FMM.
The co-cathode in example 1 was an Al thin film, and the thickness of the Al thin film was 100 nm.
Example 2: as shown in fig. 17, a gate electrode light emitting triode display includes:
each pixel comprises three sub-pixel units, namely a red sub-pixel unit 1-1, a green sub-pixel unit 1-2 and a blue sub-pixel unit 1-3;
the driving back plate 2 is provided with a plurality of regularly arranged through holes 3, and the sub-pixel unit covers at least one through hole 3; the driving back plate 2 bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode 4, a VDMOS device 5, an ITO/TiN thin film layer 6 and a light-emitting unit 7, wherein the anode 4 is arranged on the upper surface of the driving backboard 2 and at least covers one via hole 3, the VDMOS device 5 is positioned on one side, away from the driving backboard 2, of the anode 4, the ITO/TiN thin film layer 6 comprises an ITO thin film layer and a TiN thin film layer which are vertically stacked, the TiN thin film layer is arranged on one side, away from the driving backboard 2, of the VDMOS device 5, the ITO thin film layer is arranged on one side, away from the driving backboard 2, of the TiN thin film layer, and the light-emitting unit 7 is arranged on one side, away from the driving backboard 2, of the ITO thin film layer.
The VDMOS device 5 comprises an NPN type semiconductor layer 5-1 and a plurality of gate electrodes 5-2, the NPN type semiconductor layer 5-1 is located on one side, away from the driving backboard 2, of the anode 4, the plurality of independent gate electrodes 5-2 are arranged in the NPN type semiconductor layer 5-1, the gate electrodes 5-2 comprise gate insulation layers 5-3 and gate electrodes 5-4, the gate electrodes 5-4 are of rectangular structures, and the gate insulation layers 5-3 are of rectangular frame structures and wrap the peripheries of the gate electrodes 5-4.
The light-emitting unit is an LED light-emitting unit, the LED light-emitting unit comprises a first bonding metal layer 7-2, a first semiconductor layer 7-3, a light-emitting layer 7-4, a second semiconductor layer 7-5 and a second bonding metal layer 7-6, the first bonding metal layer 7-6 is bonded and grown on one side, far away from the driving backboard, of the ITO/TiN thin film layer, and the first semiconductor layer 7-5 is located on the upper surface of the first bonding metal layer 7-6; the light emitting layer 7-4 is arranged on the upper surface of the first semiconductor layer 7-3; the second semiconductor layer 7-5 is arranged on the upper surface of the light emitting layer 7-4, and the second bonding metal layer 7-6 is positioned on one side of the second semiconductor layer far away from the driving back plate 2; the light emitting layer 7-4 in the red sub-pixel unit 1-1 emits red light, the light emitting layer 7-4 in the green sub-pixel unit 1-2 emits green light, and the light emitting layer 7-4 in the blue sub-pixel unit 1-3 emits blue light.
The first thin film packaging layer 9 is filled among the sub-pixel units and covers the upper surfaces of the VDMOS device 5, the ITO/TiN thin film layer 6, the LED light-emitting unit 7 and the driving backboard 2, the corresponding first thin film packaging layers 9 in the sub-pixel units are all provided with an electrode groove 9-1, and the bottoms of the electrode grooves 9-1 in the sub-pixel units are exposed out of the upper surfaces of the LED light-emitting units.
And the common cathode 11 is arranged on a layer of the first thin film packaging layer 9 far away from the driving back plate 2 and covers the electrode groove 9-1, and in the sub-pixel unit, the common cathode 11 is in contact with the upper surface of the LED light-emitting unit through the electrode groove 9-1.
A second thin film encapsulation layer 10, the second thin film encapsulation layer 10 is grown on the common cathode 11 at the side far away from the upper surface of the driving back plate 2,
the glass packaging layer 12 is bonded to one side, far away from the driving back plate 2, of the second film packaging layer 10 through UV glue 13, and the UV glue 13 is located in the frame area of the second film packaging layer 10.
The specific steps of the gate electrode light emitting triode display in the embodiment 2 are as follows:
s1, as shown in FIG. 8, forming a plurality of via holes 3 regularly arranged on the driving back plate 2, filling conductive materials in the via holes 3, forming a plurality of anodes 4 on the upper surface of the driving back plate 2 and contacting with the upper surfaces of the via holes 3, and forming NPN type semiconductor layers 5 on the anodes 4 and the upper surface of the driving back plate 2;
s2, as shown in fig. 9, patterning the NPN-type semiconductor layer 5 to make the semiconductor layer 5 located on the side of the anode 4 away from the driving back plate 2, and forming a plurality of rectangular grooves 5-5 on the NPN-type semiconductor layer 5;
s3, depositing and growing a gate insulation layer 5-3 on the rectangular groove 5-5 and the upper surface of the NPN type semiconductor layer 5-1 as shown in figure 10;
s4, as shown in figure 11, depositing and growing a grid 5-4 in the rectangular groove 5-5 with the grid insulating layer 5-3 growing on the surface, and carrying out grinding treatment on the grid 5-4 to enable the upper surface of the grid 5-4 to be flush with the upper surface of the grid insulating layer 5-3;
s5, as shown in fig. 12, the gate 5-4 in the rectangular groove 5-5 is etched such that the upper surface of the gate 6-2 is lower than the gate insulating layer 6-1,
s6, as shown in FIG. 13, continuing to deposit and grow a gate insulation layer 5-3 on the upper surfaces of the gate 5-4 and the gate insulation layer 5-3, and performing patterning treatment on the gate insulation layer 5-3 to make the gate insulation layer 5-3 wrap around the gate 5-4 to form a trench type gate electrode 5-2;
s7, as shown in FIG. 14, continuing to deposit N-type semiconductor on the upper surface of the NPN-type semiconductor layer 5-1 and filling the N-type semiconductor between the gate electrodes 5-2 to form a new NPN-type semiconductor layer 5-1, and then sequentially plating a TiN thin film layer and an ITO thin film layer on the upper surface and carrying out patterning treatment on the TiN thin film layer and the ITO thin film layer;
s8, filling and growing the first thin film packaging layer 9 among the sub-pixel units, so that the upper surface of the first thin film packaging layer 9 is flush with the upper surface of the ITO/TiN thin film layer 6;
s9, as shown in FIG. 15, bonding and connecting the side of the ITO/TiN thin film layer 6 far away from the driving backboard 2 with an RGB LED chip by adopting a bulk transfer and vacuum low-temperature bonding technology, wherein the RGB LED chip comprises a first bonding metal layer 7-2, a first semiconductor layer 7-3, a light emitting layer 7-4 and a second semiconductor layer 7-5, the first bonding metal layer 7-2, the first semiconductor layer 7-3, the light emitting layer 7-4 and the second semiconductor layer 7-5 are sequentially arranged from bottom to top, and the light emitting layer 7-4 of the red sub-pixel unit 1-1 is made of a red multi-quantum well structure light emitting material; a green multi-quantum well structure luminescent material is arranged in a luminescent layer 7-4 of the green sub-pixel unit 1-2; the light-emitting layer 7-4 of the blue sub-pixel unit 1-3 is a blue multi-quantum well structure light-emitting material; in this embodiment 2, the first bonding metal layer 7-2 may be a P-conductive material, the first semiconductor layer 7-3 may be N-GaN, the light-emitting layer 7-4 may be a multi-quantum well Material (MQW), the second semiconductor layer 7-5 may be an N-conductive material, and the second bonding metal layer 7-6 may be an N-conductive material.
S10, as shown in FIG. 16, continuing to fill and grow the first thin film encapsulation layer 9 among the sub-pixel units, and performing a patterning process on the first thin film encapsulation layer 9, correspondingly forming an electrode groove 9-1 in each sub-pixel unit, growing a common cathode 11 on the upper surface of the first thin film encapsulation layer 9, and enabling the common cathode 11 to be in contact with the second bonding metal layer 7-6 through the electrode groove 9-11;
and S11, growing a second thin film encapsulation layer 10 on the upper surface of the common cathode 11, and finally adhering the glass encapsulation layer 12 to the upper surface of the second thin film encapsulation layer 10 by using the UV glue 13, as shown in FIG. 17.
In embodiment 2, the material of the first thin film encapsulation layer 13 and the second thin film encapsulation layer 15 may be an organic thin film, an inorganic thin film, or an inorganic thin film stacked on an organic thin film.
In embodiment 2, the gate insulating layer is prepared using SiO2, SiN, or Al2O 3; the grid is prepared by adopting a p-Si semiconductor; the anode is made of metal oxide, including indium tin oxide, indium zinc oxide or aluminum zinc oxide.
In example 2, the plated gate insulating layer may be formed by a chemical vapor deposition method or an atomic layer deposition method, and the gate may be formed by a molecular beam epitaxy technique.
As shown in fig. 17, arrows on both sides of the gate electrode indicate the direction of flow of carriers.
In embodiment 2, the unit size of the sub-pixel is 3-100 μm, the size of one gate electrode is 0.5 μm, and each sub-pixel unit carries a plurality of gate electrodes, which can be selected by those skilled in the art according to actual needs.
The optimized pixel arrangement scheme in example 2 is shown in fig. 18, and one pixel includes two green sub-pixel units, one red sub-pixel unit, and one blue sub-pixel unit. In terms of spatial distribution, four vertexes of a square pixel unit respectively comprise a green sub-pixel unit positioned at two opposite vertexes, and a red sub-pixel unit and a blue sub-pixel unit positioned at the other two vertexes, and the side length of the square pixel unit is equal to that of the pixel pich. Four sets of red sub-pixel elements are grouped together, four sets of blue sub-pixel elements are grouped together, four sets of green sub-pixel elements are grouped together, and each group shares a mask opening. Specifically, two green sub-pixel units, one red sub-pixel unit and one blue sub-pixel unit are located on the same plane and arranged in a field shape, and four sub-pixel units with the same color are arranged in a concentrated manner. The field-shaped structure is in array arrangement, which is beneficial to the compactness of pixels and improves the display effect of the pixels.
The pixel arrangement optimization scheme shown in fig. 18, in combination with the high-resolution driving backplane, can realize a high-resolution real RGB display screen body of 1000ppi or more, thereby realizing high-resolution patterning, which is no longer limited by the physical limit of the high-resolution metal mask FMM.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A gate electrode light emitting diode display, comprising:
each pixel comprises three sub-pixel units, namely a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the driving back plate is provided with a plurality of regularly arranged through holes, and the sub-pixel unit covers at least one through hole; the driving back plate bears a plurality of pixels and is used for driving the sub-pixel units to emit light;
the sub-pixel unit comprises an anode, a VDMOS device, an ITO/TiN thin film layer and a light-emitting unit, wherein the anode is arranged on the upper surface of the driving backboard and at least covers one via hole, the VDMOS device is positioned on one side, far away from the driving backboard, of the anode, the ITO/TiN thin film layer comprises an ITO thin film layer and a TiN thin film layer which are stacked up and down, the TiN thin film layer is arranged on one side, far away from the driving backboard, of the VDMOS device, the ITO thin film layer is arranged on one side, far away from the driving backboard, of the TiN thin film layer, and the light-emitting unit is arranged on one side, far away from the driving backboard, of the ITO thin film layer.
2. The gate electrode light-emitting triode display of claim 1, wherein the VDMOS device comprises an NPN type semiconductor layer and a plurality of gate electrodes, the NPN type semiconductor layer is located on a side of the anode away from the driving backplate, a plurality of independent gate electrodes are arranged in the NPN type semiconductor layer, each gate electrode comprises a gate insulating layer and a gate, the gate is in a V-shaped structure, and the gate insulating layers cover the inner and outer sides of the gate.
3. The gate electrode light-emitting triode display of claim 1, wherein the VDMOS device comprises an NPN-type semiconductor layer and a plurality of gate electrodes, the NPN-type semiconductor layer is located on a side of the anode away from the driving backplate, a plurality of independent gate electrodes are arranged in the NPN-type semiconductor layer, each gate electrode comprises a gate insulating layer and a gate, each gate has a rectangular structure, and each gate insulating layer has a rectangular frame structure and is wrapped around the gate.
4. A gate electrode light-emitting diode display according to claim 2, wherein the light-emitting unit is an RGB OLED light-emitting layer, and the material of the RGB OLED light-emitting layer in the red sub-pixel unit is a red OLED light-emitting material; the material of the RGB OLED light-emitting layer in the green sub-pixel unit is a green OLED light-emitting material; the material of the RGB OLED light-emitting layer in the blue sub-pixel unit is a blue OLED light-emitting material.
5. The gate electrode light-emitting diode display according to claim 3, wherein the light-emitting unit is an LED light-emitting unit, the LED light-emitting unit comprises a first bonding metal layer, a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a second bonding metal layer, the first bonding metal layer is bonded and grown on one side of the ITO/TiN thin film layer far away from the driving backboard, and the first semiconductor layer is located on the upper surface of the first bonding metal layer; the light emitting layer is arranged on the upper surface of the first semiconductor layer; the second semiconductor layer is arranged on the upper surface of the light-emitting layer, and the second bonding metal layer is positioned on one side, far away from the driving backboard, of the second semiconductor layer; the light emitting layer in the red sub-pixel unit emits red light, the light emitting layer in the green sub-pixel unit emits green light, and the light emitting layer in the blue sub-pixel unit emits blue light.
6. The gate electrode light-emitting diode display according to claim 4, further comprising a first thin film encapsulation layer filled between each sub-pixel unit, wherein the upper surface of the first thin film encapsulation layer is flush with the upper surface of the RGB OLED light-emitting layer.
7. The gate electrode light-emitting diode display as claimed in claim 5, further comprising a first thin film encapsulation layer, wherein the first thin film encapsulation layer is filled between the sub-pixel units and covers the VDMOS device, the ITO/TiN thin film layer, the LED light-emitting units and the upper surface of the driving back plate, and an electrode groove is formed on the corresponding first thin film encapsulation layer of each sub-pixel unit, and the bottom of the electrode groove in each sub-pixel unit exposes a part of the upper surface of the LED light-emitting unit.
8. A gate electrode light-emitting diode display according to claim 6, further comprising a common cathode on the first thin film encapsulation layer on the side away from the driving backplane and overlying the RGB OLED light-emitting layers.
9. The gate electrode light-emitting diode display of claim 7, further comprising a common cathode disposed on a layer of the first thin film encapsulation layer away from the driving backplane and covering the electrode groove, wherein the common cathode in the sub-pixel unit is in contact with the upper surface of the LED light-emitting unit through the electrode groove.
10. The gate electrode light-emitting triode display according to claim 8 or 9, further comprising a second thin film encapsulation layer and a glass encapsulation layer, wherein the second thin film encapsulation layer is grown on the common cathode on the side away from the upper surface of the driving backboard, the glass encapsulation layer is bonded on the side of the second thin film encapsulation layer away from the driving backboard through UV glue, and the UV glue is located in the frame area of the second thin film encapsulation layer.
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